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Product Folder Sample & Buy Support & Community Tools & Software Technical Documents TLV314, TLV2314, TLV4314 SBOS754A – MARCH 2016 – REVISED MARCH 2016

TLVx314 3-MHz, Low-Power, Internal EMI Filter, RRIO, Operational Amplifier

1 Features 3 Description

• • • • • • • • • The TLV314 family of single-, dual-, and quadchannel operational amplifiers represents a new generation of low-power, general-purpose operational amplifiers. Rail-to-rail input and output swings (RRIO), low quiescent current (150 μA typically at 5 V) combine with a wide bandwidth of 3 MHz to make this family very attractive for a variety of battery-powered applications that require a good balance between cost and performance. Additionally, the TLV314 family architecture achieves a low input bias current of 1 pA, allowing for applications with MΩ source impedances.

1 Low Offset Voltage: 0.75 mV (typ)

Low Input Bias Current: 1 pA (typ) Wide Supply Range: 1.8 V to 5.5 V Rail-to-Rail Input and Output Gain Bandwidth: 3 MHz Low I Q : 250 µA/Ch (max) Low Noise: 16 nV/√Hz at 1 kHz Internal RF/EMI Filter Extended Temperature Range: –40°C to +125°C

The robust design of the TLV314 devices provides ease-of-use to the circuit designer: unity-gain stability, RRIO, capacitive loads of up to 300 pF, an integrated RF/EMI rejection filter, no phase reversal in overdrive conditions, and high electrostatic discharge (ESD) protection (4-kV HBM).

2 Applications

• • • • • • • White Goods Handheld Test Equipment Portable Blood Glucose Systems Remote Sensing Active Filters Industrial Automation Battery-Powered Electronics These devices are optimized for low-voltage operation as low as 1.8 V (±0.9 V) and up to 5.5 V (±2.75 V), and are specified over the extended industrial temperature range of –40°C to +125°C. The TLV314 (single) is available in both 5-pin SC70 and SOT-23 packages. The TLV2314 (dual) is offered in 8-pin SOIC and VSSOP packages. The quadchannel TLV4314 is offered in a 14-pin TSSOP package.

Device Information (1) EMIRR vs Frequency

PART NUMBER 120 110 TLV314 EMIRR IN+ (dB)

100 90 TLV2314 80 70 TLV4314 60 PACKAGE BODY SIZE (NOM)

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

50 40 30 20 10 0 10M 100M 1G

Frequency (Hz)

10G 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

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Table of Contents

1 2 3 4 5 6 7 Features .................................................................. 1 Applications ........................................................... 1 Description ............................................................. 1 Revision History..................................................... 2 Device Comparison Table..................................... 3 Pin Configuration and Functions ......................... 3 Specifications......................................................... 6 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 8 Absolute Maximum Ratings ...................................... 6 ESD Ratings.............................................................. 6 Recommended Operating Conditions....................... 6 Thermal Information: TLV314 ................................... 7 Thermal Information: TLV2314 ................................. 7 Thermal Information: TLV4314 ................................. 7 Electrical Characteristics........................................... 8 Typical Characteristics .............................................. 9 Typical Characteristics ............................................ 10 Detailed Description ............................................ 13 8.1 Overview ................................................................. 13 8.2 Functional Block Diagram ....................................... 13 8.3 Feature Description................................................. 14 8.4 Device Functional Modes........................................ 15 9 Application and Implementation ........................ 16

9.1 Application Information............................................ 16 9.2 Typical Application ................................................. 16 9.3 System Examples ................................................... 17 10 Power Supply Recommendations ..................... 18

10.1 Input and ESD Protection ..................................... 18 11 Layout................................................................... 19

11.1 Layout Guidelines ................................................. 19 11.2 Layout Example .................................................... 19 12 Device and Documentation Support ................. 20

12.1 12.2 12.3 12.4 12.5 12.6 12.7 Device Support...................................................... 20 Documentation Support ........................................ 20 Related Links ........................................................ 20 Community Resources.......................................... 20 Trademarks ........................................................... 20 Electrostatic Discharge Caution ............................ 20 Glossary ................................................................ 20 13 Mechanical, Packaging, and Orderable

Information ........................................................... 20

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Original (March 2016) to Revision A

• 2 Page

Released to production .......................................................................................................................................................... 1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated

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5 Device Comparison Table

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8-Pin SOIC or VSSOP

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14-Pin TSSOP

Top View 14 OUT D 13 -IN D

+IN A A B D C Pin Functions: TLV4314 PIN

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNIT 7 V Supply voltage Signal input pins Voltage (2) Current (2)

(V–) – 0.5 (V+) + 0.5 V

–10 10 mA Output short-circuit (3) Continuous

Specified, T A Temperature –40 (2)

(3)

125 Junction, T J 150 Storage, T stg

MIN V S Supply voltage MAX Single supply 1.8 5.5 Dual supply ±0.9 ±2.75 –40 125 Specified temperature range 6 NOM Submit Documentation Feedback UNIT V °C Copyright © 2016, Texas Instruments Incorporated

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7.7 Electrical Characteristics

V S = 1.8 V to 5.5 V; at T A = 25°C, R L = 10 kΩ connected to V S / 2, V CM = V S / 2, and V OUT = V S / 2 (unless otherwise noted) (1)

PARAMETER TEST CONDITIONS MIN TYP MAX

UNIT

OFFSET VOLTAGE

V OS Input offset voltage V CM = (V S +) – 1.3 V, T A = 25°C

PSRR Power-supply rejection ratio V CM = (V S +) – 1.3 V, T A = 25°C ±30

mV

μV/°C 2

±135 µV/V

dB

INPUT VOLTAGE RANGE

V CM CMRR Common-mode voltage range T A = 25°C Common-mode rejection ratio

(V–) – 0.2 72

(V+) + 0.2 96 V dB 75

INPUT BIAS CURRENT

I B Input bias current T A = 25°C ±1.0 pA I OS Input offset current T A = 25°C ±1.0 pA Input voltage noise (peak-to-peak) f = 0.1 Hz to 10 Hz, T A = 25°C 5 μV PP

NOISE nV/√Hz fA/√Hz OPEN-LOOP GAIN A OL Open-loop voltage gain Phase margin

dB

°

FREQUENCY RESPONSE GBW Gain-bandwidth product SR Slew rate (3) V S = 5 V, G = 1, T A = 25°C 1.5 V/μs t S Settling time To 0.1%, V S = 5 V, 2-V step , G = 1, T A = 25°C 3 μs

Overload recovery time V S = 5 V, V IN × gain > V S , T A = 25°C 8 μs Total harmonic distortion + noise (4) V S = 5 V, V O = 1 V RMS , G = 1, f = 1 kHz, R

THD+N MHz 0.005% OUTPUT

R O Open-loop output impedance V S = 5.5 V, f = 100 Hz, T A = 25°C 570 Ω POWER SUPPLY

V S Specified voltage range I Q Quiescent current per amplifier, over temperature 1.8

5.5 V 250 µA TEMPERATURE T stg

(1)

(2) (3) (4)

8 Specified range –40 125 °C

Storage range –65 150 °C

Parameters with minimum or maximum specification limits are 100% production tested at 25ºC, unless otherwise noted. Overtemperature limits are based on characterization and statistical analysis. Specified by design and characterization; not production tested. Signifies the slower value of the positive or negative slew rate. Third-order filter; bandwidth = 80 kHz at –3 dB.

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7.8 Typical Characteristics

Table 1. Table of Graphs

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7.9 Typical Characteristics

0 180

120 - 20 170

100 - 40

80 - 60

60 - 80

40 - 100

20 - 120

0 - 140 90

• 20 - 160

10M 80 1 10 100 1k 10k 100k 1M Quiescent Current ( m A/Ch)

140 Phase (°) Gain (dB)

at T A = 25°C, R L = 10 kΩ connected to V S / 2, V CM = V S / 2, and V OUT = V S / 2 (unless otherwise noted)

160

150

140

130

120

110

100 1.5 2 2.5 3 4 3.5 4.5 5 5.5 6 Supply Voltage (V) Frequency (Hz)

Figure 1. Open-Loop Gain and Phase vs Frequency Figure 2. Quiescent Current vs Supply

1000 12 600 Offset Voltage ( m V)

Percent of Amplifiers (%)

800 10 8 6 4 400

200

0

• 200

• 400

• 600 2

• 800 0

-1.4 -1.3 -1.2 -1.1 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 - 1000

-2.75 -2 -1.25 -0.5 0 0.5 1.25 2 2.75 Common-Mode Voltage (V) Offset Voltage (mV)

Figure 4. Offset Voltage vs Common-Mode Voltage Figure 3. Offset Voltage Production Distribution

1000 100 Input Bias Current (pA)

Voltage Noise (nv/ ÖHz )

900

700

I B 600

500

400

300

200

I OS 100

10 0

10 10 800 100 1k 10k 100k -50 -25 0 25 50 75 100 125 150

Frequency (Hz) Temperature (°C)

Figure 5. Input Voltage Noise Spectral Density vs

Frequency Figure 6. Input Bias and Offset Current vs Temperature Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated

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Typical Characteristics (continued)

3 70 2 60

50 1

Overshoot (%)

Output Voltage Swing (V)

at T A = 25°C, R L = 10 kΩ connected to V S / 2, V CM = V S / 2, and V OUT = V S / 2 (unless otherwise noted)

25°C 0 125°C -40°C - 1 40 30 20

• 2 10 0 - 3

5 0 10 15 20 25 30 35 0 40 200 400 600 800 1000 1200

Capacitive Load (pF) Output Current (mA)

Figure 7. Output Voltage Swing vs Output Current

(Over Temperature)

Figure 8. Small-Signal Overshoot vs Load Capacitance 1 0.75

V IN 0.5 Voltage (V)

Voltage (25 mV/div)

V IN 0.25 0 - 0.25

V OUT

• 1

Figure 9. Small-Signal Pulse Response (Noninverting) Figure 10. Large-Signal Pulse Response (Noninverting) 4 - 60

3 Channel Separation (dB)

V IN V OUT Voltage (1 V/div)

2

1

0

• 1

• 2 - 80 - 100 - 120

• 3

• 140 - 4

0 250 500 750 1000 100 1k 10k 100k 1M 10M

Frequency (Hz) Time (125 m s/div)

Figure 11. No Phase Reversal Figure 12. Channel Separation vs Frequency (TLV2314)

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Typical Characteristics (continued)

at T A = 25°C, R L = 10 kΩ connected to V S / 2, V CM = V S / 2, and V OUT = V S / 2 (unless otherwise noted)

120 110 EMIRR IN+ (dB)

100 90 80 70 60 50 40 30 20 10 0 10M 100M 1G

Frequency (Hz)

10G

Figure 13. Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR IN+) vs Frequency 12 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated

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8 Detailed Description

8.1 Overview

The TLV314 is a family of low-power, rail-to-rail input and output operational amplifiers specifically designed for portable applications. These devices operate from 1.8 V to 5.5 V, are unity-gain stable, and suitable for a wide range of general-purpose applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected to any point between V+ and ground. The input common-mode voltage range includes both rails, and allows the TLV314 series to be used in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in low-supply applications, and makes these devices ideal for driving sampling analog-to-digital converters (ADCs). The TLV314 features 3-MHz bandwidth and 1.5-V/μs slew rate with only 150-μA supply current per channel, providing good ac performance at very low power consumption. DC applications are also well served with a very low input noise voltage of 14 nV/√Hz at 1 kHz, low input bias current (0.2 pA), and an input offset voltage of 0.5 mV (typical).

8.2 Functional Block Diagram

V+ Reference Current V IN+ V INV BIAS1 Class AB

Control Circuitry V O V BIAS2 V - (Ground)

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8.3 Feature Description

8.3.1 Operating Voltage The TLV314 series of operational amplifiers is fully specified and ensured for operation from 1.8 V to 5.5 V. In addition, many specifications apply from –40°C to +125°C. Parameters that vary significantly with operating voltages or temperature are provided in the Typical Characteristics section. Bypass power-supply pins with 0.01-μF ceramic capacitors.

8.3.2 Rail-to-Rail Input The input common-mode voltage range of the TLV314 series extends 200 mV beyond the supply rails. This performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a P-channel differential pair; see the Functional Block Diagram section. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.3 V to 200 mV above the positive supply, and the P-channel pair is on for inputs from 200 mV below the negative supply to approximately (V+) – 1.3 V. There is a small transition region, typically (V+) – 1.4 V to (V+) – 1.2 V, in which both pairs are on. This 200-mV transition region can vary up to 300 mV with process variation. Thus, the transition region (both stages on) can range from (V+) – 1.7 V to (V+) – 1.5 V on the low end, up to (V+) – 1.1 V to (V+) – 0.9 V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can be degraded compared to device operation outside this region.

8.3.3 Rail-to-Rail Output Designed as a micro-power, low-noise operational amplifier, the TLV314 delivers a robust output drive capability. A class AB output stage with common-source transistors is used to achieve full rail-to-rail output swing capability. For resistive loads up to 10 kΩ, the output typically swings to within 5 mV of either supply rail regardless of the power-supply voltage applied. Different load conditions change the ability of the amplifier to swing close to the rails; see Figure 7.

8.3.4 Common-Mode Rejection Ratio (CMRR) The CMRR for the TLV314 is specified in several ways so the best match for a given application can be used; see the Electrical Characteristics table. First, the CMRR of the device in the common-mode range below the transition region [V CM < (V+) – 1.3 V] is given. This specification is the best indicator of the capability of the device when the application requires using one of the differential input pairs. Second, the CMRR over the entire common-mode range is specified at (V CM = –0.2 V to 5.7 V). This last value includes the variations measured through the transition region (see Figure 4).

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Feature Description (continued)

8.3.5 Capacitive Load and Stability The TLV314 is designed to be used in applications where driving a capacitive load is required. As with all operational amplifiers, there may be specific instances where the TLV314 can become unstable. The particular operational amplifier circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether or not an amplifier is stable in operation. An operational amplifier in the unity-gain (1 V/V) buffer configuration that drives a capacitive load exhibits a greater tendency to be unstable than an amplifier operated at a higher noise gain. The capacitive load, in conjunction with the operational amplifier output resistance, creates a pole within the feedback loop that degrades the phase margin. The degradation of the phase margin increases when capacitive loading increases. When operating in the unity-gain configuration, the TLV314 remains stable with a pure capacitive load up to approximately 1 nF. The equivalent series resistance (ESR) of some very large capacitors (C L greater than 1 μF) is sufficient to alter the phase characteristics in the feedback loop such that the amplifier remains stable. Increasing the amplifier closed-loop gain allows the amplifier to drive increasingly larger capacitance. This increased capability is evident when measuring the overshoot response of the amplifier at higher voltage gains; see Figure 8. One technique for increasing the capacitive load drive capability of the amplifier operating in a unity-gain configuration is to insert a small resistor (typically 10 Ω to 20 Ω) in series with the output, as shown in Figure 14. This resistor significantly reduces the overshoot and ringing associated with large capacitive loads. One possible problem with this technique, however, is that a voltage divider is created with the added series resistor and any resistor connected in parallel with the capacitive load. The voltage divider introduces a gain error at the output that reduces the output swing.

V+ R S V OUT Device

10 W to 20 W V IN

R L C L Figure 14. Improving Capacitive Load Drive 8.3.6 EMI Susceptibility and Input Filtering Operational amplifiers vary with regard to the susceptibility of the device to electromagnetic interference (EMI). If conducted EMI enters the operational amplifier, the dc offset observed at the amplifier output can shift from its nominal value when EMI is present. This shift is a result of signal rectification associated with the internal semiconductor junctions. Although all operational amplifier pin functions can be affected by EMI, the signal input pins are likely to be the most susceptible. The TLV314 operational amplifier family incorporates an internal input low-pass filter that reduces the amplifiers response to EMI. Both common-mode and differential mode filtering are provided by this filter. The filter is designed for a cutoff frequency of approximately 80 MHz (–3 dB), with a roll-off of 20 dB per decade. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. The EMI rejection ratio (EMIRR) metric allows operational amplifiers to be directly compared by the EMI immunity. Figure 13 illustrates the results of this testing on the TLV314. Detailed information can also be found in application report, EMI Rejection Ratio of Operational Amplifiers (SBOA128), available for download from www.ti.com.

8.4 Device Functional Modes

The TLV314 family has a single functional mode. These devices are powered on as long as the power-supply voltage is between 1.8 V (±0.9 V) and 5.5 V (±2.75 V).

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9 Application and Implementation

NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TLV314 device is a low-power, rail-to-rail input and output operational amplifier specifically designed for portable applications. These devices operate from 1.8 V to 5.5 V, are unity-gain stable, and suitable for a wide range of general-purpose applications. The class AB output stage is capable of driving ≤ 10-kΩ loads connected to any point between V+ and ground. The input common-mode voltage range includes both rails, and allows the TLV314 device to be used in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in low-supply applications, and makes the device ideal for driving sampling analog-to-digital converters (ADCs). The TLV314 family of devices features a 3-MHz bandwidth and 1.5-V/μs slew rate with only 150-μA supply current per channel, providing good ac performance at very low power consumption. DC applications are also well served with a very-low input noise voltage of 14 nV/√Hz at 1 kHz, low-input bias current (0.2 pA), and an input offset voltage of 0.5 mV (typical).

9.2 Typical Application

A typical application for an operational amplifier is an inverting amplifier, as shown in Figure 15. An inverting amplifier takes a positive voltage on the input and outputs a signal inverted to the input, making a negative voltage of the same magnitude. In the same manner, the amplifier also makes negative input voltages positive on the output. In addition, amplification can be added by selecting the input resistor R I and the feedback resistor R F .

R F V SUP+ R I V OUT + V IN

V SUPFigure 15. Application Schematic 9.2.1 Design Requirements The supply voltage must be chosen to be larger than the input voltage range and the desired output range. The limits of the input common-mode range (V CM ) and the output voltage swing to the rails (V O ) must also be considered. For instance, this application scales a signal of ±0.5 V (1 V) to ±1.8 V (3.6 V). Setting the supply at ±2.5 V is sufficient to accommodate this application.

9.2.2 Detailed Design Procedure Determine the gain required by the inverting amplifier using Equation 1 and Equation 2:

V OUT A V V

IN

A V 16 1.8 0.5 3.6 (1)

(2)

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Typical Application (continued)

When the desired gain is determined, choose a value for R I or R F . Choosing a value in the kilo ohm range is desirable for general-purpose applications because the amplifier circuit uses currents in the milliamp range. This milliamp current range ensures the device does not draw too much current. The trade-off is that very large resistors (100s of kilo ohms) draw the smallest current but generate the highest noise. Very small resistors (100s of ohms) generate low noise but draw high current. This example uses 10 kΩ for R I , meaning 36 kΩ is used for R F . These values are determined by Equation 3:

R F A V R

I (3)

9.2.3 Application Curve

2

Input Output 1.5 Voltage (V)

1 0.5 0 -0.5 -1 -1.5 -2

Time

Figure 16. Inverting Amplifier Input and Output

9.3 System Examples

When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required. The simplest way to establish this limited bandwidth is to place an RC filter at the noninverting terminal of the amplifier, as Figure 17 shows.

R G R F R 1 V OUT V IN

Figure 17. Single-Pole, Low-Pass Filter Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated

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System Examples (continued)

If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this task, as Figure 18 shows. For best results, the amplifier must have a bandwidth that is eight to ten times the filter frequency bandwidth. Failure to follow this guideline can result in phase shift of the amplifier.

C 1 R 1 R 1 = R 2 = R C 1 = C 2 = C Q = Peaking factor

R 2 V IN

V OUT C 2 1

2pRC f -3 dB = R F

R F R G = R G ( 2 -

1 Q ( Figure 18. Two-Pole, Low-Pass, Sallen-Key Filter

10 Power Supply Recommendations

The TLV314 family is specified for operation from 1.8 V to 5.5 V (±0.9 V to ±2.75 V); many specifications apply from –40°C to +125°C. The Typical Characteristics section presents parameters that can exhibit significant variance with regard to operating voltage or temperature.

CAUTION Supply voltages larger than 7 V can permanently damage the device (see the Absolute Maximum Ratings table).

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement; see the Layout Guidelines section.

10.1 Input and ESD Protection

The TLV314 family incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of input and output pins, this protection primarily consists of current-steering diodes connected between the input and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as long as the current is limited to 10 mA as stated in the Absolute Maximum Ratings table. Figure 19 shows how a series input resistor can be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input, which must be kept to a minimum in noise-sensitive applications.

V+ I OVERLOAD 10-mA max

Device V OUT V IN

5 kW Figure 19. Input Current Protection 18 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated

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11 Layout

11.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and the

operational amplifier. Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications. • Separate grounding for analog and digital portions of the circuitry is one of the simplest and most

effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, see Circuit Board Layout Techniques, SLOA089. • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as

possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicularly is much better than crossing in parallel with the noisy trace. • Place the external components as close to the device as possible. Keep R F and R G close to the inverting

input in order to minimize parasitic capacitance, as shown in Figure 20. • Keep the length of input traces as short as possible. Always remember that the input traces are the most

sensitive part of the circuit. • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly

reduce leakage currents from nearby traces that are at different potentials.

11.2 Layout Example

• V IN

V OUT R G R F (Schematic Representation)

Place components Run the input traces close to the device and to each other to reduce as far away from parasitic errors. the supply lines

as possible.

V S+ R F N/C N/C

V IN +IN OUTPUT

R G Use a low-ESR, ceramic bypass

capacitor.

GND

VS± GND Use a low-ESR, ceramic

bypass capacitor.

VOUT

Ground (GND) plane on another layer.

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12 Device and Documentation Support

12.1 Device Support 12.2 Documentation Support

12.2.1 Related Documentation For related documentation, see the following: • EMI Rejection Ratio of Operational Amplifiers, SBOA128 • Circuit Board Layout Techniques , SLOA089 • QFN/SON PCB Attachment, SLUA271 • Quad Flatpack No-Lead Logic Packages, SCBA017

12.3 Related Links

Table 2 lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TLV314 Click here Click here Click here Click here Click here TLV2314 Click here Click here Click here Click here Click here TLV4314 Click here Click here Click here Click here Click here

12.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

12.5 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.7 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

20 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated

Product Folder Links: TLV314 TLV2314 TLV4314

PACKAGE OPTION ADDENDUM

www.ti.com 22-Jul-2026

PACKAGING INFORMATION

Orderable part number Status Material type

(1) (2)

Package | Pins Package qty | Carrier RoHS

(3)

Lead finish/ Ball material MSL rating/ Peak reflow

(4) (5)

Op temp (°C) Part marking

(6)

PACKAGE OPTION ADDENDUM

www.ti.com Orderable part number (1)

22-Jul-2026 Status Material type

(1) (2)

Package | Pins Package qty | Carrier RoHS

(3)

Lead finish/ Ball material MSL rating/ Peak reflow Op temp (°C) Part marking (4) (5) NIPDAU | SPOT AG (TOP SIDE)

Level-1-260C-UNLIM -40 to 125 12I (6)

TLV314IDCKT Active Production SC70 (DCK) | 5 250 | SMALL T&R Yes TLV314IDCKT.A Active Production SC70 (DCK) | 5 250 | SMALL T&R Yes SPOT AG (TOP SIDE) Level-1-260C-UNLIM -40 to 125 12I TLV314IDCKT.B Active Production SC70 (DCK) | 5 250 | SMALL T&R Yes SPOT AG (TOP SIDE) Level-1-260C-UNLIM -40 to 125 12I TLV4314IPWR Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU | SN Level-2-260C-1 YEAR -40 to 125 V4314 TLV4314IPWR.A Active Production TSSOP (PW) | 14 2000 | LARGE T&R Yes NIPDAU Level-2-260C-1 YEAR -40 to 125 V4314 Status: For more details on status, see our product life cycle.

(2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

(5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLV2314, TLV314, TLV4314 :

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com 22-Jul-2026 • Automotive : TLV2314-Q1, TLV314-Q1, TLV4314-Q1 NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jul-2026

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jul-2026 TAPE AND REEL BOX DIMENSIONS Width (mm)

W L H *All dimensions are nominal

PACKAGE OUTLINE

DCK0005A SOT - 1.1 max height

SCALE 5.600

SMALL OUTLINE TRANSISTOR C

2.4 1.8

1.4 1.1 PIN 1 INDEX AREA B 1.1 MAX A 5 1 NOTE 4 2X 0.65 1.3 0.1 C (0.15) 2 1.3 2.15 1.85

(0.1)

0.33 0.15 C A B 4 3 5X

0.1 4X 0 -12

NOTE 5 (0.9) 0.1 TYP 0.0 4X 4 -15 0.15

0.22 TYP 0.08 GAGE PLANE 8 TYP 0 0.46 TYP 0.26 SEATING PLANE 4214834/G 11/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-203. 4. Support pin may differ or may not be present. 5. Lead width does not comply with JEDEC.

6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed

0.25mm per side www.ti.com

EXAMPLE BOARD LAYOUT

DCK0005A SOT - 1.1 max height

SMALL OUTLINE TRANSISTOR 5X (0.95) PKG

1 5 5X (0.4)

SYMM (1.3) 2 2X (0.65)

3 4 (R0.05) TYP (2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X SOLDER MASK OPENING METAL EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK

DEFINED (PREFERRED)

SOLDER MASK

DEFINED SOLDER MASK DETAILS 4214834/G 11/2024

NOTES: (continued)

7. Publication IPC-7351 may have alternate designs.

8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DCK0005A SOT - 1.1 max height

SMALL OUTLINE TRANSISTOR PKG 5X (0.95)

1

5 5X (0.4)

SYMM

(1.3) 2 2X(0.65)

4 3 (R0.05) TYP (2.2)

SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL

SCALE:18X 4214834/G 11/2024

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

10. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

D0008A SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA

6X .050

[1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 )

4

5 B 8X .012-.020

[0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 )

SEE DETAIL A

.010 [0.25] .004-.010 [0.11-0.25] 0 - 8

.016-.050 [0.41-1.27] DETAIL A

(.041) [1.04] TYPICAL 4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 )

[1.55]

SYMM SEE

DETAILS 1

8 8X (.024)

[0.6] 6X (.050 )

[1.27] SYMM 5 4 (R.002 ) TYP

[0.05] (.213) [5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X METAL SOLDER MASK OPENING EXPOSED

METAL

.0028 MAX [0.07] ALL AROUND SOLDER MASK

OPENING METAL UNDER SOLDER MASK EXPOSED

METAL

.0028 MIN [0.07] ALL AROUND SOLDER MASK

DEFINED NON SOLDER MASK

DEFINED SOLDER MASK DETAILS 4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 )

[1.55] SYMM

1

8 8X (.024)

[0.6] 6X (.050 )

[1.27] SYMM 5 4 (R.002 ) TYP

[0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X 4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

PW0014A TSSOP - 1.2 mm max height

SCALE 2.500

SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A

0.1 C PIN 1 INDEX AREA

12X 0.65 14 1 2X 5.1 4.9 NOTE 3 3.9 4X (0 -12 )

7

8

14X B 4.5 4.3

NOTE 4 0.30 0.17 0.1 C A B 1.2 MAX (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE

0.15 0.05 0 -8 0.75 0.50

DETAIL A A 20 TYPICAL 4220202/B 12/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0014A TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE SYMM 14X (1.5)

(R0.05) TYP 1 14 14X (0.45)

SYMM 12X (0.65)

8 7 (5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X SOLDER MASK

OPENING METAL UNDER SOLDER MASK METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX ALL AROUND NON-SOLDER MASK

DEFINED (PREFERRED)

0.05 MIN ALL AROUND SOLDER MASK

DEFINED SOLDER MASK DETAILS 15.000 4220202/B 12/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0014A TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE 14X (1.5) SYMM (R0.05) TYP 1 14X (0.45) 14 SYMM 12X (0.65)

8 7 (5.8)

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL

SCALE: 10X 4220202/B 12/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DBV0005A SOT-23 - 1.45 mm max height

SCALE 4.000

SMALL OUTLINE TRANSISTOR C 3.0 2.6

1.75 1.45 PIN 1 INDEX AREA 1 A 5 (0.1) 2X 0.95 1.9 0.1 C B 3.05 2.75 1.9 2

(0.15)

4 0.5 5X

0.3 0.2 3 C A B NOTE 5 4X 0 -15 (1.1) 0.15 TYP 0.00

1.45 0.90 4X 4 -15 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/K 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.25 mm per side.

5. Support pin may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0005A SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR PKG 5X (1.1)

1

5 5X (0.6)

SYMM

(1.9) 2

2X (0.95)

3 4 (R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK

DEFINED (PREFERRED)

SOLDER MASK

DEFINED SOLDER MASK DETAILS 4214839/K 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0005A SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR PKG

5X (1.1)

1

5 5X (0.6)

SYMM (1.9) 2

2X(0.95)

4 3 (R0.05) TYP (2.6)

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL

SCALE:15X 4214839/K 08/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DGK0008A VSSOP - 1.1 mm max height

SCALE 4.000

SMALL OUTLINE PACKAGE C 5.05 TYP 4.75 A

0.1 C PIN 1 INDEX AREA SEATING

PLANE 6X 0.65 8 1 2X 3.1 2.9 NOTE 3 1.95 4

5

8X

B 3.1 2.9

NOTE 4 0.38 0.25 0.13 C A B 0.23 0.13 SEE DETAIL A

0.25 GAGE PLANE 1.1 MAX 0 -8 0.15 0.05 0.7 0.4

DETAIL A A 20 TYPICAL 4214862/A 04/2023 PowerPAD is a trademark of Texas Instruments. NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187.

www.ti.com

EXAMPLE BOARD LAYOUT

TM DGK0008A VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE SYMM 8X (1.4)

8X (0.45)

(R0.05) TYP 1 8 SYMM 6X (0.65)

5 4 SEE DETAILS (4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X SOLDER MASK

OPENING METAL UNDER SOLDER MASK METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX ALL AROUND

NON-SOLDER MASK

DEFINED (PREFERRED)

0.05 MIN ALL AROUND SOLDER MASK

DEFINED SOLDER MASK DETAILS 15.000 4214862/A 04/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

TM DGK0008A VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE SYMM (R0.05) TYP 8X (1.4)

8X (0.45) 1 8 SYMM 6X (0.65)

5 4 (4.4)

SOLDER PASTE EXAMPLE

SCALE: 15X 4214862/A 04/2023

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you fully indemnify TI and its representatives against any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale, TI’s General Quality Guidelines, or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Unless TI explicitly designates a product as custom or customer-specified, TI products are standard, catalog, general purpose devices. TI objects to and rejects any additional or different terms you may propose. IMPORTANT NOTICE Copyright © 2026, Texas Instruments Incorporated

Last updated 10/2025