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General Description APPLICATIONS n ADSL PCI modem cards n ADSL external modems n Cable drivers n Video line driver n Twisted pair driver/receiver n Power line communications Typical Application - ADSL Application
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sa The Comlinear CLC2000 and CLC4000 are dual and quad voltage feedback amplifiers that offer ±200mA of output current at 9.4V pp . The CLC2000 and CLC4000 are capable of driving signals to within 1V of the power rails. When connected as a differential line driver, the amplifier drives signals up to 18.8Vpp into a 25Ω load, which supports the peak upstream power levels for plies from 5V to 12V. It consumes only 7mA of supply current per channel. The combination of wide bandwidth, low noise, low distortion, and high output current capability makes the CLC2000 and CLC4000 ideally suited for Customer Premise ADSL or video line driving applications.
+Vs +
1/2 CLC2000
RfR o- =12.5Ω V o+ V OUT V o1/2 CLC2000 -Vs Ordering Information Part Number Package Pb-Free Operating Temperature Range Packaging Method CLC2000ISO8X SOIC-8 Yes -40°C to +85°C Reel CLC2000ISO8 SOIC-8 Yes -40°C to +85°C Rail CLC4000ISO14X SOIC-14 Yes -40°C to +85°C Reel CLC4000ISO14 SOIC-14 Yes -40°C to +85°C Rail Moisture sensitivity level for all parts is MSL-1.
Exar Corporation 48720 Kato Road, Fremont CA 94538, USA www.exar.com Tel. +1 510 668-7000 - Fax. +1 510 668-7001 C omlinear
Rev 1D FEATURES n 9.4V pp output drive into R L = 25Ω n Using both amplifiers, 18.8V pp differential output drive into R L = 25Ω
n 0.009%/0.06˚ differential gain/ phase error
n 4.5nV/√Hz input voltage noise n 2.7pA/√Hz input current noise n 7mA supply current n Fully specified at 5V and 12V supplies Data Sheet
CLC2000 Pin Assignments CLC2000 Pin Configuration
Pin Name 1 OUT1 Output, channel 1 OUT2 2 -IN1 Negative input, channel 1 -IN2 3 +IN1 Positive input, channel 1
4 -V S Negative supply 5 +IN2 Positive input, channel 2 6 -IN2 Negative input, channel 2 7 OUT2 Output, channel 2 8 +V S Positive supply 1 8 +V S
-IN1 2 7
+IN1 3 6
-V S 4 +IN2 5 CLC4000 Pin Assignments
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sa CLC4000 Pin Configuration OUT1 1 14
-IN1 2 13
+IN1 3 12
+VS 4 11
+IN2 5 10
-IN2 6 9 OUT2 7 8 Description C omlinear
Rev 1D Pin No. OUT1 OUT4
-IN4
+IN4
-VS
| Pin No. | Pin Name | Description |
|---|---|---|
| 1 | OUT1 | Output, channel 1 |
| 2 | -IN1 | Negative input, channel 1 |
| 3 | +IN1 | Positive input, channel 1 |
| 4 | -V S | Negative supply |
| 5 | +IN2 | Positive input, channel 2 |
| 6 | -IN2 | Negative input, channel 2 |
| 7 | OUT2 | Output, channel 2 |
| 8 | +V S | Positive supply |
| CLC4000 Pin Assignments | CLC4000 Pin Assignments | CLC4000 Pin Assignments |
| Pin No. | Pin Name | Description |
| od1 | OUT1 | Output, channel 1 |
| uc2 | -IN1 | Negative input, channel 1 |
| t 3 t | +IN1 | Positive input, channel 1 |
| a 4 ( | or +V S | Positive supply |
| re5 | pr+IN2 | Positive input, channel 2 |
| ma 6 no | od-IN2 | Negative input, channel 2 |
| y 7 | lo OUT2 uc | Output, channel 2 |
| n ot8 | ng OUT3 ts | Output, channel 3 |
| 9 | be e r-IN3 ) | Negative input, channel 3 |
| 10 | +IN3 b o | mPositive input, channel 3 |
| 11 | rd-V S ein | Negative ensupply |
| 12 | +IN4 ere | gPositive tioinput, channel 4 |
| 13 | -IN4 d | ma Negative neinput, channel 4 |
| 14 | OUT4 | (OOutput, nu channel d in4 |
Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots.
Supply Voltage Input Voltage Range Min Max Unit 0 -V s -0.5V ±7 or 14 +V s +0.5V V V C omlinear
Rev 1D Parameter Reliability Information Parameter Min Max Unit
150 150 260 °C °C °C da
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sa Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Package Thermal Resistance 8-Lead SOIC 14-Lead SOIC Typ -65 100 88 °C/W °C/W Notes: Package thermal resistance (q JA ), JDEC standard, multi-layer test boards, still air. ESD Protection Product Human Body Model (HBM) Charged Device Model (CDM)
2.5kV 2kV
Recommended Operating Conditions Parameter Operating Temperature Range Supply Voltage Range ©2007-2013 Exar Corporation Min -40 ±2.5 3/18 Typ Max Unit
+85 ±6.5 °C V Rev 1D Data Sheet
Electrical Characteristics T A = 25°C, V s = 5V, R f = R g = 510Ω, R L = 100Ω to V S /2, G = 2; unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response
-3dB Bandwidth G = +1, V OUT = 0.2V pp, R f = 0 422 MHz BW SS BW LS -3dB Bandwidth G = +2, V OUT = 0.2V pp 236 MHz Large Signal Bandwidth G = +2, V OUT = 2V pp 68 BW 0.1dB MHz 0.1dB Gain Flatness G = +2, V OUT = 0.2V pp 77 MHz Time Domain Response
Rise and Fall Time V OUT = 1V step; (10% to 90%) 3.7 ns t S Settling Time to 0.1% V OUT = 2V step 20 ns OS Overshoot V OUT = 0.2V step 6 % SR Slew Rate V OUT = 2V step 200 V/µs
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nt R , t F DC Performance V IO Input Offset Voltage dV IO Average Drift I IO Input Offset Current I b Input Bias Current dI bni Average Drift 0.3 mV 0.383 µV/°C 0.2 µA 10 µA 2.5 nA/°C
Non-inverting 2.5 MΩ
1 pF 0.4 to 4.6 V 80 dB
Input Characteristics R IN Input Resistance C IN Input Capacitance
CMIR Common Mode Input Range
CMRR Common Mode Rejection Ratio DC Output Characteristics R O V OUT I SC Output Resistance Output Voltage Swing Short-Circuit Output Current ©2007-2013 Exar Corporation 4/18 Rev 1D C omlinear
Rev 1D UGBW Data Sheet
Electrical Characteristics T A = 25°C, V s = 12V, R f = R g = 510Ω, R L = 100Ω to V S /2, G = 2; unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response
-3dB Bandwidth G = +1, V OUT = 0.2V pp, R f = 0 510 MHz BW SS BW LS -3dB Bandwidth G = +2, V OUT = 0.2V pp 250 MHz Large Signal Bandwidth G = +2, V OUT = 4V pp 35 BW 0.1dB MHz 0.1dB Gain Flatness G = +2, V OUT = 0.2V pp 32 MHz Time Domain Response
Rise and Fall Time V OUT = 4V step; (10% to 90%) 13.3 ns t S Settling Time to 0.1% V OUT = 2V step 20 ns OS Overshoot V OUT = 0.2V step 2 % SR Slew Rate V OUT = 4V step 210 V/µs
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t R , t F DC Performance V IO dV IO Input Offset Voltage (1)
Average Drift I IO Input Offset Current (1) I b Input Bias Current (1) dI bni Average Drift -6 0.3 6
0.383 -2 73 mV µV/°C 0.2 2 10 20 µA µA 2.5 nA/°C 81 dB PSRR Power Supply Rejection Ratio (1) DC
Non-inverting 2.5 MΩ
1 pF 0.6 to 11.4 V 70 79 dB Closed Loop, DC 0.01 Ω
dB 12 mA Input Characteristics R IN Input Resistance C IN Input Capacitance
CMIR Common Mode Input Range
CMRR Common Mode Rejection Ratio (1) DC Output Characteristics R O V OUT I SC Output Resistance Output Voltage Swing Short-Circuit Output Current 10.5 V
Notes: 1. 100% tested at 25°C ©2007-2013 Exar Corporation 5/18 Rev 1D C omlinear
Rev 1D UGBW Data Sheet
Typical Performance Characteristics T A = 25°C, V s = 12V, R f = 510Ω, R L = 100Ω to V S /2, G = 2; unless otherwise noted.
Non-Inverting Frequency Response (V S =5V)
1 2 0 1
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aG = 1 R f = 0 -1 -2
R L = 150Ω -3
-5 R L = 1kΩ 0 -1 -2
R L = 150Ω -3
-5 V OUT = 0.2V pp V OUT = 0.2V pp
R L = 25Ω -6 R L = 25Ω -6 0.1 1 10 100 1000 0.1
Frequency (MHz)
©2007-2013 Exar Corporation 1 10
Frequency (MHz)
6/18 Rev 1D C omlinear
Rev 1D Non-Inverting Frequency Response Data Sheet
Typical Performance Characteristics - Continued T A = 25°C, V s = 12V, R f = 510Ω, R L = 100Ω to V S /2, G = 2; unless otherwise noted.
Frequency vs. C L Frequency vs. C L (V S = 5V)
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32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 100 1000
45
40
35
30
25
20
15
10
V OUT = 0.2V pp R S optimized for <1dB peaking 10 V OUT = 0.2V pp R S optimized for <1dB peaking 5
0 100 1000 10 100 C L (pf)
Frequency Response vs. V OUT 1 1000 C L (pF)
Frequency Response vs. V OUT (V S = 5V)
1 V OUT = 1V pp 0 -1
V OUT = 5V pp V OUT = 2V pp -2 -3
V OUT = 4V pp -4 V OUT = 1V pp 0 Normalized Gain (dB)
Normalized Gain (dB)
RS (Ω) R S (Ω)
Recommended R S vs. C L -5 -6 -1
V OUT = 2V pp -2 -3
V OUT = 3V pp -4 -5 -6 -7 -7
0.1 1 10 100 1000 0.1
Frequency (MHz)
©2007-2013 Exar Corporation 1 10 100 1000
Frequency (MHz)
7/18 Rev 1D C omlinear
Rev 1D 1 Data Sheet
Typical Performance Characteristics - Continued T A = 25°C, V s = 12V, R f = 510Ω, R L = 100Ω to V S /2, G = 2; unless otherwise noted.
Frequency Response vs. Temperature Frequency vs. Temperature (V S = 5V)
1
Normalized Gain (dB)
0 + 85degC -2 -3 -4 -5 -3 + 25degC -4
V OUT = 2V 0.2V pp pp
-7
0.1 -2
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sa -6 -1 1 V OUT = .2V 0.2V pp pp
-7 10 100 1000 0.1 1 Frequency (MHz)
-3dB Bandwidth vs. Output Voltage 275 1000 -3dB Bandwidth vs. Output Voltage (V S =5V)
225 225 200 -3dB Bandwidth (MHz) 200 175 150 125 100 75 175
150
125
100
75
50 50 25 25 0 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.5 1.0
V OUT (V PP )
2.5 3.0 2.0 Input Voltage Noise 1.5 V OUT (V PP )
Open Loop Transimpendance Gain/Phase vs. Frequency 100 250 250 -3dB Bandwidth (MHz)
10 Frequency (MHz)
©2007-2013 Exar Corporation 0.01 0.1 1 10 100 Frequency (MHz)
8/18 Rev 1D C omlinear
Rev 1D 1 Data Sheet
Typical Performance Characteristics - Continued T A = 25°C, V s = 12V, R f = 510Ω, R L = 100Ω to V S /2, G = 2; unless otherwise noted.
2nd Harmonic Distortion vs. R L 3rd Harmonic Distortion vs. R L -20 -30 -30
Distortion (dBc) Distortion (dBc)
-40 -50 -60 -70
R L = 1kΩ -80 -60 -70
R L = 1kΩ -80
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sa -90 da -100
0 5 -90 V OUT = 2V pp 10 15 20 0 5 10 Frequency (MHz)
3rd Harmonic Distortion vs. V OUT -30 -40 -50 10MHz -60 -70 Distortion (dBc)
-40 Distortion (dBc)
20 -20 -30 5MHz -80 -90 -50
10MHz -60 -70
5MHz -80 -90 1MHz -100 1MHz -100 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 0.5 0.75 1 1.25
Output Amplitude (V pp )
0.01 1.5 1.75 2 2.25 2.5 2.75 3 Output Amplitude (V pp )
Differential Gain & Phase AC Coupled Differential Gain & Phase DC Coupled 0.06 R L = 150Ω AC coupled into 220µF 0.0075
0.005 0.05 Diff Gain (%)
and Diff Phase (°)
Diff Gain (%)
and Diff Phase (°)
15 Frequency (MHz)
2nd Harmonic Distortion vs. V OUT -20 V OUT = 2V pp -100 DG 0.0025 0 -0.0025 -0.005
DP -0.0075 -0.01 DP 0.04
0.03
0.02
0.01
0 -0.01 DG
DC coupled V OUT = 2V pp -0.03 -0.7 -0.5 -0.3 -0.1 C omlinear
Rev 1D -20 0.1 0.3 0.5 0.7 -0.7 Input Voltage (V)
©2007-2013 Exar Corporation -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7
Input Voltage (V)
9/18 Rev 1D Data Sheet
Typical Performance Characteristics - Continued T A = 25°C, V s = 12V, R f = 510Ω, R L = 100Ω to V S /2, G = 2; unless otherwise noted.
2nd Harmonic Distortion vs. R L (V S =5V)
-20 -30 -30 Distortion
-70
R L = 1kΩ -80 -70
R L = 1kΩ -80
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sa -90 da -100
0 5 -90 V OUT = 2V pp 10 15 20 0 5 10 Frequency (MHz)
20 3rd Harmonic Distortion vs. V OUT (V S =5V)
-45 -45
-50 -50
10MHz -55 -55
-60 5MHz
-65
-70
-75
-80 Distortion (dBc) Distortion (dBc)
15 Frequency (MHz)
2nd Harmonic Distortion vs. V OUT (V S =5V)
10MHz -60
-65
-70 5MHz -75 1MHz -80 1MHz -85 -85
-90 -90
0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 0.5 0.75 1 1.25
Output Amplitude (V pp )
0.01 1.5 1.75 2 2.25 2.5 2.75 3 Output Amplitude (V pp )
Differential Gain & Phase AC Coupled (V S =5V) Differential Gain & Phase DC Coupled (V S =5V)
0.04 R L = 150Ω AC coupled into 220µF 0.0075 DG Diff Gain (%)
and Diff Phase (°)
Diff Gain (%)
and Diff Phase (°)
V OUT = 2V pp -100 0.005 0.0025 0 -0.0025 -0.005
DP -0.0075 R L = 150Ω DC coupled 0.03 0.02
DG 0.01 0 -0.01
DP -0.01 -0.02
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -0.4
Input Voltage (V)
©2007-2013 Exar Corporation -0.2 0 0.2 0.4
Input Voltage (V)
10/18 Rev 1D C omlinear
Rev 1D -20 Distortion (dBc)
3rd Harmonic Distortion vs. R L (V S =5V)
Data Sheet
Typical Performance Characteristics - Continued T A = 25°C, V s = 12V, R f = 510Ω, R L = 100Ω to V S /2, G = 2; unless otherwise noted.
Large Signal Pulse Response 9.0 6.1 8.0 6.05 7.0 Voltage (V)
6.15 6 V OUT = 2V pp
6.0 5.0 5.9 4.0
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sa 5.95 5.85
0 20 40 60 80 V OUT = 4V pp 100 3.0 120 140 160 180 200 0 20 40 60 80 Time (ns)
Small Signal Pulse Response (V S =5V)
2.65 100 120 140 160 180 200 Time (ns)
Large Signal Pulse Response (V S =5V)
4.5
V OUT = 3V pp 4.0 2.60
3.5
V OUT = 2V pp Voltage (V) Voltage (V)
2.55 2.50 2.45 3.0 2.5 2.0 1.5 2.40 1.0 2.35 0.5
0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80
Time (ns)
Crosstalk vs. Frequency 120 140 160 180 200 Crosstalk vs. Frequency (V S =5V)
-30 -30 -35 -35 -40 -40 -45 -45 -50 -50 Crosstalk (dB) Crosstalk (dB)
100 Time (ns)
-55 -60 -65 -70 -75 -55 -60 -65 -70 -75 -80 -80 V OUT = 2V pp -85 V OUT = 2V pp -85 -90 -90
0.1 1 10 100 0.1
Frequency (MHz)
©2007-2013 Exar Corporation 1 10 100
Frequency (MHz)
11/18 Rev 1D C omlinear
Rev 1D Voltage (V)
Small Signal Pulse Response Data Sheet
Typical Performance Characteristics - Continued T A = 25°C, V s = 12V, R f = 510Ω, R L = 100Ω to V S /2, G = 2; unless otherwise noted.
Closed Loop Output Impedance vs. Frequency CMRR vs. Frequency 1 CMRR (dB)
-30 0.1 0.01 -40 -50
-60
-70
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-20 -80 da 0.001
1k 10k 100k 1M 10M -90 100M 10 100 1k PSRR vs. Frequency 1M 10M 100M 1.25 1.00 -40 100k Input Voltage vs. Output Current
-30 10k Frequency (Hz) Frequency (Hz)
©2007-2013 Exar Corporation
12/18 Rev 1D C omlinear
Rev 1D -10 10 Data Sheet
Application Information Basic Operation +V s
6.8μF
Power Dissipation Input 0.1μF +
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aOutput -
0.1μF R g 6.8μF
-V s R f
Figure 1. Typical Non-Inverting Gain Circuit +V s R 1 Input R g 6.8μF Output -
0.1μF Maximum power levels are set by the absolute maximum junction rating of 150°C. To calculate the junction temperature, the package thermal resistance value Theta JA (Ө JA ) is used along with the total die power dissipation.
T Junction = T Ambient + (Ө JA × P D ) 0.1μF + Power dissipation is an important consideration in applications with low impedance DC, coupled loads. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond its intended operating range. Calculations below relate to a single amplifier. For the CLC2000/CLC4000, all amplifiers power contribution needs to be added for the total power dissipation.
R L R f 6.8μF -V s G = - (R f /R g ) For optimum input offset
voltage set R 1 = R f || R g
Figure 2. Typical Inverting Gain Circuit Where T Ambient is the temperature of the working environment. In order to determine P D , the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. P D = P supply - P load Supply power is calculated by the standard power equation. Power Supply and Decoupling P supply = V supply × I (RMS supply) The CLC2000 and CLC4000 can be powered with a low noise supply anywhere in the range from +5V to +13V. Ensure adequate metal connections to power pins in the PC board layout with careful attention paid to decoupling the power supply.
High quality capacitors with low equivalent series resistance (ESR) such as multilayer ceramic capacitors (MLCC) should be used to minimize supply voltage ripple and power dissipation.
©2007-2013 Exar Corporation Power delivered to a purely resistive load is: P load = ((V LOAD ) RMS2 ) / Rload eff The effective load resistor will need to include the effect of the feedback network. For instance, Rload eff in figure 1 would be calculated as: R L || (R f + R g )
13/18 Rev 1D C omlinear
Rev 1D Figures 1 and 2 illustrate typical circuit configurations for non-inverting, inverting, and unity gain topologies for dual supply applications. They show the recommended bypass capacitor values and overall closed loop gain equations.
Two decoupling capacitors should be placed on each power pin with connection to a local PC board ground plane. A large, usually tantalum, 10μF to 47μF capacitor is required to provide good decoupling for lower frequency signals and to provide current for fast, large signal changes at the CLC2000/CLC4000 outputs. It should be within 0.25” of the pin. A secondary smaller 0.1μF MLCC capacitor should located within 0.125” to reject higher frequency noise on the power line.
Data Sheet These measurements are basic and are relatively easy to perform with standard lab equipment. For design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. Here, P D can be found from Quiescent power can be derived from the specified I S values along with known supply voltage, V Supply . Load power can be calculated as above with the desired signal amplitudes using:
(V LOAD ) RMS = V PEAK / √2 Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, R S , between the amplifier and the load to help improve stability and settling performance. Refer to Figure 4. da
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sa ( I LOAD ) RMS = (V LOAD ) RMS / Rload eff Driving Capacitive Loads The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: Input + P DYNAMIC = (V S+ - V LOAD ) RMS × (I LOAD ) RMS - Maximum Power Dissipation (W)
SOIC-8 1 0.5 Figure 4. Addition of R S for Driving
Capacitive Loads 0 -40 -20 0 20 R L Table 1 provides the recommended R S for various capacitive loads. The recommended R S values result in <=1dB peaking in the frequency response. The Frequency Response vs. C L plots, on page 7, illustrates the response of the CLC2000.
SOIC-14 1.5 Output R g Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8 Lead SOIC packages.
2 C L R f Assuming the load is referenced in the middle of the power rails or V supply /2.
2.5 R s 40 60 80 Ambient Temperature (°C)
| C L (O(pF) BS | nu faR S (Ω) in | -3dB BW (MHz) th |
|---|---|---|
| 10 | ) ctu 40 | is 275 |
| 20 | 24.5 re | 250 |
| 50 | 20 | d 175 |
| 100 | 13.5 | 135 |
| 500 | 6 | 75 |
| 1000 | 5 | 45 |
Table 1: Recommended R S vs. C L Better thermal ratings can be achieved by maximizing PC board metallization at the package pins. However, be careful of stray capacitance on the input pins. In addition, increased airflow across the package can also help to reduce the effective Ө JA of the package.
©2007-2013 Exar Corporation For a given load capacitance, adjust R S to optimize the tradeoff between settling time and bandwidth. In general, reducing R S will increase bandwidth at the expense of additional overshoot and ringing.
14/18 Rev 1D C omlinear
Rev 1D P D = P Quiescent + P Dynamic - P Load In the event of a short circuit condition, the CLC2000/ CLC4000 has circuitry to limit output drive capability to ±1000mA. This will only protect against a momentary event. Extended duration under these conditions will cause junction temperatures to exceed 150°C. Due to internal metallization constraints, continuous output current should be limited to ±100mA.
Data Sheet Overdrive Recovery +Vs 3 Input Voltage (V)
0 -1 -2
Output -2
RfOutput Voltage (V)
2 0
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sa 1 Rf+ 4 da Input 1/2 CLC2000 6 V IN = 2.5V pp G = 5 2 + 1/2 CLC2000 -Vs Figure 6: Typical Differential Transmission Line Driver -4 -3 -6
0 20 40 60 80 100 120 140 160 180 200
Time (ns) Figure 5. Overdrive Recovery Using the CLC2000/CLC4000 as a Differential Line Driver The combination of good large signal bandwidth and high output drive capability makes the CLC2000/CLC4000 well suited for low impedance line driver applications, such as the upstream data path for a ADSL CPE modem. The dual channel configuration of the CLC2000 provides better channel matching than a typical single channel device, resulting in better overall performance in differential applications. When configured as a differential amplifier as in figure 6, it can easily deliver the 13dBm to a standard 100Ω twisted-pair CAT3 or CAT5 cable telephone network, as required in a ADSL CPE application. Differential circuits have several advantages over singleended configurations. These include better rejection of common mode signals and improvement of power-supply rejection. The use of differential signaling also improves overall dynamic performance. Total harmonic distortion (THD) is reduced by the suppression of even signal harmonics and the larger signal swings allow for an improved signal to noise ratio (SNR).
©2007-2013 Exar Corporation For any transmission requirement, the fundamental design parameters needed are the effective impedance of the transmission line, the power required at the load, and knowledge concerning the content of the transmitted signal. The basic design of such a circuit is briefly outlined below, using the ADSL parameters as a guideline. Data transmission techniques, such as ADSL, utilize amplitude modulation techniques which are sensitive to output clipping. A signal’s PEAK to RMS ratio, or Crest Factor (CF), can be used to determine the adequate peak signal levels to insure fidelity for a given signal. For an ADSL system, the signal consists of 256 independent frequencies with varying amplitudes. This results in a noise-like signal with a crest factor of about 5.3. If the driver does not have enough swing to handle the signal peaks, clipping will occur and amplitude modulated information can be corrupted, causing degradation in the signals Bit Error Rate. To determine the required swing, first use the specified load impedance to convert the RMS power to an RMS voltage. Then, multiply the RMS voltage by the crest factor to get the peak values. For example 13dBm, as referenced to 1mW, is ~20mW. 20mW into the 100Ω CAT5 impedance yields a RMS voltage of 1.413 VRMS . Using the ADSL crest factor of 5.3 yields ~ ±7.5V peak signals.
15/18 Rev 1D C omlinear
Rev 1D An overdrive condition is defined as the point when either one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the amplifier to return to its normal or linear operating point. The recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. The CLC2000/CLC4000 will typically recover in less than 40ns from an overdrive condition. Figure 5 shows the CLC2000 in an overdriven condition.
Data Sheet Evalutaion Board Schematics Evaluation board schematics and layouts are shown in Figures 7-9. These evaluation boards are built for dual- supply operation. Follow these steps to use the board in a single-supply application:
directly connected to the ground plane.
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sa In general, the CLC2000/CLC4000 can be used in any application where an economical and local hardwired connection is needed. For example, routing analog or digital video information for a in-cabin entertainment system. Networking of a local surveillance system also could be considered.
Layout Considerations General layout and supply bypassing play major roles in high frequency performance. Exar has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: • Include 6.8µF and 0.1µF ceramic capacitors for power supply decoupling • Place the 6.8µF capacitor within 0.75 inches of the power pin • Place the 0.1µF capacitor within 0.1 inches of the power pin • Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance Figure 7. CEB006 Schematic • Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts below for more information. Evaluation Board Information The following evaluation board is available to aid in the testing and layout of this device:
Evaluation Board # CEB006 CEB018 Products CLC2000 CLC4000 Figure 8. CEB006 Top View ©2007-2013 Exar Corporation 16/18 Rev 1D C omlinear
Rev 1D Line coupling through a 1:2 transformer is used to realize these levels. Standard back termination is used to match the characteristic 100Ω impedance of the CAT5 cable. For proper power transfer, this requires an effective 1:4 impedance match of 25Ω at the inputs of the transformer. To account for the voltage drop of the impedance matching resistors, the signal levels at the output of the amplifier need to be doubled. Thus each amplifier will swing ±3.75V about a centered common mode output voltage.
Data Sheet C omlinear
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Rev 1D 17/18 ©2007-2013 Exar Corporation Figure 11. CEB018 Top View Figure 9. CEB006 Bottom View Figure 12. CEB018 Bottom View Figure 10. CEB018 Schematic Data Sheet
Mechanical Dimensions