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Analog Integrated Circuits and Signal Processing https://doi.org/10.1007/s10470-019-01491-1 (0123456789().,-volV) (0123456789(). ,- volV)
Sinem Keleş 1 • Fatih Keleş 2 Received: 15 February 2019 / Revised: 15 February 2019 / Accepted: 21 June 2019 Ó Springer Science+Business Media, LLC, part of Springer Nature 2019 Abstract A novel four quadrant FGMOS analog multiplier having properties such as low voltage-low power and wide input linearity range is presented. Power consumption of the proposed multiplier is 26.2 nW and the input swing is rail-to-rail which is obtained by choosing the ratio of input capacitances to total capacitance of FGMOS transistors resulting a reduction in the transconductance. Other important features of the proposed multiplier are the bandwidth of 52.5 MHz and maximum THD of 2.04% (when the input voltages are at supply voltage level).
Keywords Low power Wide range Multiplier FGMOS Subthreshold Four quadrant Analog 1 Introduction In recent years, analog circuit structures using MOS transistors working in weak inversion are becoming increasingly important. The primary reason for this is the need for battery-powered and low-power electronic circuits that can be used in layouts such as biomedical devices that are small enough to be placed on the patient. Operating a MOS transistor under the threshold region provides many useful aspects. The power consumption for the circuits built with the subthreshold MOS transistors shows very small values. The drain current of the transistor is saturated at a few kT/ q, which allows the transistor to act as a current source in the range from the reference voltage to the supply voltage.
Four quadrant analog multipliers are said to be very important for designers because they take a big place in signal processing applications like modulators, frequency doublers, correlators, adaptive filters and convolvers, etc. There can be found so many four quadrant multipliers constructed by MOS transistors working in above threshold region (strong inversion) [1–4]. Nevertheless most of them do not meet continuous time micro-power systems [5]. The & Sinem Keleş
Fatih Keleş [email protected]
1 Istanbul Medeniyet University, Istanbul, Turkey 2 Istanbul University-Cerrahpasa, Istanbul, Turkey use of MOS transistors working in subthreshold region is one of the most familiar methods to ensure low power consumption. [5–9]. The main advantage of subthreshold operation in low power consumption is that it works at much smaller current levels than above threshold operation.
Although there are many ways of designing four quadrant multipliers in CMOS technology, the most commonly used ones are Gillbert cell [10] based methods some of them using modified versions while the original one was based on bipolar technique. Quarter square algebraic identity is another method to implement four quadrant analog multipliers which can easily be achieved by using the MOS transistors working in strong inversion. There are some other methods that have been reported in literature such as pulse width modulation technique, switched capacitors technique, etc. In most of the methods where the MOS transistor is operated above the threshold, it is seen that the linear range of the input signal can go up to several volts. Due to the quadratic current–voltage relationship of MOS transistors working above threshold region, wide input signal linearity range is relatively easy to be achieved while it is not so easy to obtain a large input signal linearity range for subthreshold operation because of the exponential current voltage relationship.
In an earlier study [5] four separate techniques are joined together to achieve a comparable linear range. In their technique they used well terminals in order to reduce the input transconductance. After that, transconductance is extra reduced by using some other techniques such as
Analog Integrated Circuits and Signal Processing source and gate degeneration. At last, they used bumplinearization to widen the input linearity range. Beside this combination of four different techniques input swing of our proposed multiplier is rail-to-rail which is obtained by rightly choosing the ratio of input capacitances to total capacitance of FGMOS transistors resulting a reduction in the transconductance. In an another earlier study [6] input linearity range was widened through using different FGMOS input capacitances. They used 0.9 V supply voltage in their circuit and obtained 87 nW power consumption while our proposed multiplier operates under 0.25 V supply voltage and consumes very low power of 26.2 nW.
In this paper, a novel four quadrant FGMOS analog multiplier having properties such as low voltage-low power and wide input linearity range is presented. Power consumption of the proposed multiplier is 26.2 nW and the input swing is rail-to-rail which is obtained by choosing the ratio of input capacitances to total capacitance of FGMOS transistors resulting a reduction in the transconductance. Other important features of the proposed multiplier are the bandwidth of 52.5 MHz and maximum THD of 2.04% (when the input voltages are at supply voltage level).
Rest of the paper is divided into several sections. In the second section, general characteristics of FGMOS transistor are mentioned. In the third section, structure and operation of the proposed FGMOS multiplier circuit is explained. In the fourth section, SPICE simulation results of the proposed circuit are presented and the fifth section is conclusion.
2 FGMOS transistors FGMOS transistors have been used in analog circuit designs in an exciting way in recent years [11–16]. Since FGMOS transistors are widely used in digital circuits [17, 18], they are already available in standard CMOS technology. For this reason, FGMOS transistors are used by analog designers in more applications nowadays. As a result, FGMOS transistors are used not only in digital circuits but also in analog circuit design. The FGMOS transistor is formed by isolating electrically the gate of a standard MOS transistor at the production stage and by placing multiple inputs on this isolated passage (FG) without any resistive connections. Although there are capacitive connections between the multiple inputs and FG, there is no resistive transition. Since FG is completely surrounded by high resistive material, it is a floating node in terms of dc operating point [11]. The equivalent schematic and equivalent circuit for an n-input n-channel FGMOS transistor are given in Figs. 1 and 2, respectively.
Since the voltages applied to the multiple inputs are capacitively connected to the FG, they control the voltage in the floating gate and tune the current flowing through the MOS transistor channel. The voltage at the FG is given by:
P C FGD V D þ C FGS V S þ C FGB V B þ C i V i V FG ¼ ð1Þ
C T C T ¼ C FGD þ C FGS þ C FGB þ n X
C i ð2Þ i¼1
The terms V FG , V D , V S and V B in the equations are the floating gate voltage, drain voltage, source voltage and bulk voltage, respectively. C i are input capacitances where i changes from 1 to n which corresponds the number of multiple inputs. C GB , C GS and C GD are the parasitic capacitances related to bulk, source and drain respectively; and C T is the sum of C GB , C GS , C GD and C i . C i C FGD ; C FGS ; C FGB ð3Þ
Parasitic capacitances are much smaller than the input ones in general and in accordance with the technique in [18], negligible terms of the equation are excluded and gate voltage is equal to the total weight of the input voltages according to the input capacity values.
Analog Integrated Circuits and Signal Processing The use of FGMOS transistors working in subthreshold region is one of the methods to ensure low power consumption as it is known from conventional MOS transistors. Furthermore, it is easier to overcome arithmetic operations required to be obtained in the circuit because of the multiple inputs of the FGMOS transistor and this simplifies the circuit topology while reducing the power consumption.
The drain current of an n-channel FGMOS transistor in subthreshold region (assuming that C i capacitances are much larger than C GD , C GS , C GB parasitic capacitances; V GS is smaller than V T ; bulk and source are short circuited and V DS is greater than 4U T ) is given below, where I D is the subthreshold drain current, n is the slope factor and U T is the thermal voltage.
VFGS I D ffi I O e nUT ð4Þ 3 Proposed circuit description Proposed multiplier circuit with FGMOS transistors operating in the subthreshold region is shown in Fig. 3. The most basic structure used to realize the analogue multiplier circuit is the Gilbert cell also known from the bipolar technique. The proposed FGMOS multiplier circuit is also based on Gillbert cell using the similarity of subthreshold behavior to bipolar technique. The proposed FGMOS multiplier consists of three FGMOS differential pairs formed as M1–M2, M3–M4 and M5–M6. Using FGMOS transistors in differential pairs in place of MOS transistors VDD M7 M8 I- I+ Iout Vgc M3 V3 M4 Vgc Vgc
M6 M5 V4
Vgc Vgc V1 M1 M2 V2
IB Fig. 3 Proposed ultra-low power FGMOS analog multiplier circuit increases the input swing as mentioned in our earlier study [2]. Drains of M3–M4 and M5–M6 differential pairs are cross connected and the sum of currents I 4 and I 5 gives the I- current in the circuit while the sum of currents I 3 and I 6 gives the I ? current. Differential inputs V 1 –V 2 and V 3 –V 4 are applied to the M1–M2 and cross connected differential pairs, respectively. The bias current I B is used as tail current to the differential pair M1–M2 while M1–M2 differential pair form tail transistors for the two differential pairs M3–M4 and M5–M6.
Assuming that all the transistors in the multiplier circuit are in the subthreshold region, transistor currents can be expressed as;
I B V FG1 V FG2 I 1 ¼ 1 þ tanh ð5Þ
2 2 I B V FG1 V FG2 1 tanh ð6Þ I 2 ¼
2 2 I 1 V FG3 V FG4 1 þ tanh ð7Þ I 3 ¼
2 2 I 1 V FG3 V FG4 1 tanh ð8Þ I 4 ¼
2 2 I 2 V FG3 V FG4 1 þ tanh ð9Þ I 5 ¼
2 2 I 2 V FG3 V FG4 1 tanh ð10Þ I 6 ¼
2 2
As can easily be seen from the equations, transistor currents are related to input voltages via tanh function similar to bipolar circuits. The sum of currents I 4 and I 5 gives the I - current in the circuit while the sum of currents I 3 and I 6 gives the I ? current. For I ? and I - currents, below equtions can be defined.
I 1 þ I 2 I 1 I 2 V FG3 V FG4 I þ ¼ þ tanh ð11Þ
2 2 2 I 1 þ I 2 I 1 I 2 V FG3 V FG4 tanh ð12Þ I ¼ 2 2 2
I ? current is mirrored with the help of the PMOS current mirror at the top of the circuit and reflected to the output similar to the transconductance amplifier. So the output current is defined as given below:
V FG3 V FG4 I o ¼ ð I 1 I 2 Þtanh ð13Þ
2 V FG1 V FG2 V FG3 V FG4 tanh ð14Þ I o ¼ I B tanh
2 2
Input swing of the proposed multiplier circuit is rail-torail which is obtained by rightly choosing the ratio of input capacitances to total capacitance of FGMOS transistors
Analog Integrated Circuits and Signal Processing 40nA
-0nA
-10nA
-20nA
-30nA -40nA
-140mV -120mV
I(Rout)
-100mV -80mV -60mV -40mV -20mV 0V 20mV 40mV 60mV 80mV 100mV 120mV 140mV
V 3 -V 4 Fig. 4 DC current outputs of the proposed multiplier circuit (I OUT = I out (V 3 –V 4 ), V 1 –V 2 is taken as parameter)
resulting a reduction in the transconductance. Voltages of the input floating gate transistors and transconductance qDI D /qDV in are given below.
V FG1 ¼ C 1 C 2
V 1 þ V GC C T C T ð15Þ
V FG2 ¼ C 1 C 2
V 2 þ V GC C T C T ð16Þ
V FG3 ¼ C 1 C 2
V 3 þ V GC C T C T ð17Þ C 1 C 1
V 3 V 4 ð23Þ C T C T oI O C 1 I B V FG3 V FG4 V FG1 V FG2 ¼ tanh sech 2 o ð V
1 V 2 Þ C T 2 2 2
ð24Þ oI O C 1 I B V FG1 V FG2
2 V FG3 V FG4 ¼ tanh sech o ð V 3 V 4 Þ C T 2 2 2
ð25Þ V FG4 ¼ C 1 C 2
V 4 þ V GC C T C T ð18Þ Relation (24) and (25) show that transconductance reduction is proportional to the factor C 1 /C T .
V FG5 ¼ C 1 C 2
V 3 þ V GC C T C T ð19Þ
V FG6 ¼ C 1 C 2
V 4 þ V GC C T C T ð20Þ
V FG1 V FG2 ¼ C 1 C 1
V 1 V 2 C T C T ð21Þ
V FG3 V FG4 ¼ C 1 C 1
V 3 V 4 C T C T ð22Þ
V FG5 V FG6 ¼ 4 Simulation results The proposed circuit was simulated using IBM 130 nm technology parameters. The supply voltage is V DD= 0.25 V and V GC is set to ground for FGMOS transistors. The bias current is I B = 100nA. The input capacitor value is C i = 2.7fF and values of C FGD and C FGS are calculated as 0.22 fF. The dimensions of input differential pair transistors M1, M2, M3, M4, M5 and M6 are W/L = 0.6 lm/ 0.3 lm, for M7 and M8 is W/L = 2.4 lm/0.3 lm. Figure 4 shows the DC current outputs of the proposed circuit when Analog Integrated Circuits and Signal Processing 40nA
30nA
10nA -0nA -10nA -20nA
-30nA
-40nA
-140mV -120mV
I(Routmos)
-100mV -80mV
I(Rout)
-60mV -40mV -20mV 0V 20mV 40mV 60mV 80mV 100mV 120mV 140mV
V 3 -V 4 Fig. 5 DC current outputs of the proposed multiplier and the CMOS counterpart V 1 –V 2 was taken as a parameter with the values - 125 mV, - 75 mV, - 25 mV, 25 mV, 75 mV and 125 mV whereas V 3 –V 4 was changed between - 125 mV and 125 mV.
Figure 5 shows the DC current outputs of the proposed multiplier and the CMOS counterpart (same circuit in Fig. 3 using MOS transistors instead of FGMOS transistors) together. During the simulation V 3 –V 4 is swept from - 125 to 125 mV while V 1 –V 2 is taken as a parameter with the values - 125 mV, 0 V, 125 mV for proposed multiplier and - 25 mV, 0 V, 25 mV for the CMOS counterpart. Remarkably increase in the input swing of proposed multiplier compared to the conventional one is seen from the figure clearly.
AC transfer characteristic of the proposed multiplier is given in Fig. 6. In Fig. 6 V 1 –V 2 is taken as DC 250 mV and the V 3 –V 4 is taken as AC 1 V. As it can be seen from the figure, bandwidth of the proposed multiplier is more than 50 MHz.
Figure 7 presents 300 kHz and 10 kHz sinusoidal inputs signals with 250 mV peak to peak amplitudes applied at V 1 –V 2 and V 3 –V 4 , respectively and the transient output waveform of the proposed multiplier is seen in Fig. 8.
Figure 9 shows the THD variation of the proposed circuit while changing V 3 –V 4 between 0 V and 125 mV (peak to peak 250 mV) and V 1 –V 2 is set to 250 mV DC.
THD of the proposed multiplier circuit when the input signals are at supply voltage level (V 1 –V 2 = 250 mV, V 3 – V 4(max) = 250 mV) is 2.042% for 5 kHz and 2.61% for 5 MHz, respectively.
Linearity extension obtained by the proposed multiplier has been investigated by using 300 kHz and 10 kHz input signals with 250 mV amplitude to the V 1 –V 2 and V 3 –V 4 respectively and examining the output intermodulation distortion properties with the aid of SPICE simulations. Intermodulation terms of f 1 ? f 2 = 310 kHz and f 1 - f 2- = 290 kHz are chosen as 0 dB and the other terms have been normalized to these values. The intermodulation terms sorted by SPICE simulations are given in Table 1. As it is clearly seen from the table, output intermodulation terms of the proposed multiplier are remarkably lower than those output intermodulation terms of the conventional multiplier topology (same circuit in Fig. 3 used MOS transistors instead of FGMOS transistors).
To examine the stability of the proposed multiplier relating to process variations, Monte Carlo analysis was run 100 times with 5% changes in the gate oxide thickness, V TH and input capacitances of all transistors. Figures 10 and 11 show the Monte Carlo analysis of - 3 dB bandwidth and transient output current of the proposed multiplier.
Analog Integrated Circuits and Signal Processing 400nA
I OUT / V 3 -V 4 350nA 300nA (52.515M,256.378n)
250nA 200nA 150nA
1.0 KHz I(Rout) 3.0KHz 10 KHz 30 KHz 100 KHz 300 KHz 1.0MHz 3.0MHz 10MHz 30MHz 100MHz 300MHz 1.0GHz
Frequency Fig. 6 AC transfer characteristic (I OUT /V 3 –V 4 ) of the proposed multiplier circuit (V 1 –V 2 is set to DC 250 mV)
150mV 100mV 50mV -0mV -50mV -100mV -150mV 0s 10us
V1 – V2 20us V3 – V4 30us 40us 50us 60us 70us 80us 90us 100us 110us 120us 130us 140us 150us 160us 170us 180us 190us 200us
Time Fig. 7 Input signals V 1 –V 2 and V 3 –V 4 of the proposed multiplier Figure 12 presents the transient output current of the proposed multiplier for different temperatures (25 °C, 50 °C and 100 °C) when using 300 kHz and 10 kHz input signals with 250 mV amplitude to the V 1 –V 2 and V 3 –V 4
respectively. Figure 12 confirms that the proposed multiplier is almost temperature-insensitive.
Performance of the proposed multiplier was compared to other previous subthreshold multiplier circuits reviewed in the literature. A comparison table presenting the Analog Integrated Circuits and Signal Processing 30nA 20nA 10nA -0nA -10nA -20nA -30nA 0s 10us 20us 30us 40us 50us 60us 70us 80us 90us
I(Rout)
100us 110us 120us 130us 140us 150us 160us 170us 180us 190us 200us Time Fig. 8 Transient output current of the proposed multiplier Table 1 Intermodulation products of the proposed multiplier and Frequency (kHz) Proposed multiplier Conventional multiplier - 17.58 270 - 36.46 290 0 0 300 - 72.38 - 41.02 310 0 0 330 - 36.57 - 17.77 570 - 85.47 - 75.37
performance of the proposed multiplier and other previous subthreshold works is given in Table 2 below. As it can be seen from the table, the proposed circuit has the lowest supply voltage, the lowest power consumption, the widest bandwidth and the lowest THD (except THD of [6]) between all other previous subthreshold works given in the table. The best performing low power realization was the one presented in [6]. Power consumption of our circuit is less than one-third of the power of the nearest competitor in [6].
A novel four quadrant FGMOS analog multiplier having properties such as low voltage-low power and wide input linearity range is presented. Power consumption of the proposed multiplier is 26.2 nW and the input swing is railto-rail which is obtained by choosing the ratio of input capacitances to total capacitance of FGMOS transistors resulting a reduction in the transconductance. Other important features of the proposed multiplier are the bandwidth of 52.5 MHz and maximum THD of 2.04% (when the input voltages are at supply voltage level).
Analog Integrated Circuits and Signal Processing
Fig. 10 Monte Carlo analysis of -3 dB bandwidth of the proposed multiplier circuit
Analog Integrated Circuits and Signal Processing 28nA
22nA
T=100C 20nA 18nA
ZOOM 16nA 14nA 12nA 23.55us23.6us 23.65us23.7us 23.75us23.8us 23.85us23.90us23.95us24us
I(Rout)
24.05us24.1us 24.15us24.2us 24.25us24.3us 24.35us24.4us 24.45us24.5us 24.55us24.6us 24.65us24.7us
Time 30nA 20nA 10nA -0nA -10nA -20nA -30nA
0s 5us
I(Rout)
10us 15us 20us 25us 30us 35us 40us 45us 50us 55us 60us 65us 70us 75us 80us 85us 90us 95us 100us
Time Fig. 12 Transient output voltage of the proposed multiplier circuit for different temperatures (25 °C, 50 °C and 100 °C)
Table 2 Comparison between the performances of the proposed multiplier and other previous subthreshold multipliers
Proposed multiplier Rodriguez [6] Hiretkar [8] Panigrahi [7] Pesavento [5] Liu [9] Supply voltage 0.25 V 0.9 V 0.5 V 0.5 V 5V 1.5 V Power dissipation 26.2 nW 87 nW 598 nW 714.3 nW 1 lW 6.7 lW Bandwidth THD 52.5 MHz 2.04% NA 0.313% 200.3 kHz NA 221 kHz 5.8% 10 kHz 3% 268 kHz 4.2% Process used 0.13 lm 0.35 lm 0.18 lm 0.18 lm 1.2 lm 0.35 lm
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