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MCP3465R

Two-Channel, 153.6 ksps, Low Noise 16-Bit Delta-Sigma ADC with Internal Voltage Reference Features General Description

• One Differential or Two Single-Ended Input

Channels • 16-Bit Resolution • Programmable Data Rate: Up to 153.6 ksps • Programmable Gain: 0.33x to 64x • 97.2 dB SINAD, -116 dBc THD, 120 dBc SFDR

• Low-Temperature Drift:

• Offset error drift: 4/Gain nV/°C (AZ_MUX = 1) - Gain error drift: 0.5 ppm/°C (Gain = 1x) • Low Noise: 2.3 µV RMS (Gain = 16x, 9600 SPS) • RMS Effective Resolution: 15.4 Bits Minimum (All

Gains, All OSR Combinations) • Wide Input Voltage Range: 0V to AV DD • Selectable Internal 2.4V Voltage Reference with

15 ppm/°C Drift • Differential Voltage Reference Inputs • Internal Oscillator or External Clock Selection • Ultra-Low Full Shutdown Current Consumption

(< 2.4 µA) • Internal Temperature Sensor • Burnout Current Sources for Sensor Open/Short

Detection • 16-Bit Digital Offset and Gain Error Calibration

Registers • Internal Conversions Sequencer (Scan Mode) for

Automatic Multiplexing • Advanced Security Features:

• 16-bit CRC for secure SPI communications - 16-bit CRC and IRQ for securing

configuration - Register map lock with 8-bit secure key - Monitor controls for system diagnostics • 20 MHz SPI-Compatible Interface with Mode 0,0

and 1,1 • AV DD : 2.7V-3.6V • DV DD : 1.8V-3.6V • Extended Temperature Range: -40°C to +125°C • Package: 2 mm x 2 mm x 0.55 mm 12-Lead UQFN The MCP3465R is a one differential channel or two single-ended channels, 16-Bit Delta-Sigma Analogto-Digital Converter (ADC) with a programmable data rate of up to 153.6 ksps. It offers integrated features, such as internal voltage reference, internal oscillator, temperature sensor and burnout sensor detection, in order to reduce system component count and total solution cost.

 2020-2021 Microchip Technology Inc.

The MCP3465R ADC is fully configurable with an Oversampling Ratio (OSR) from 32 to 98304 and gain from 1/3x to 64x. The device includes an internal sequencer (Scan mode) with multiple monitor channels and a 16-bit timer to be able to automatically create conversion loop sequences without needing MCU communications. Advanced security features, such as CRC and register map lock, can ensure configuration locking and integrity, as well as communication data integrity for secure environments. The device comes with a 20 MHz SPI-compatible serial interface. Communication is largely simplified with 8-bit commands, including various Continuous Read/Write modes and 16/32-bit multiple data formats that can be accessed by the Direct Memory Access (DMA) of an 8-bit, 16-bit or 32-bit MCU. The MCP3465R device is available in an ultra-small, 2 mm x 2 mm x 0.55 mm 12-Lead UQFN package and is specified over an extended temperature range from -40°C to +125°C.

Applications

• Precision Sensor Transducers and Transmitters:

Pressure, Strain, Flow and Force Measurement • Factory Automation and Process Controls • Portable Instrumentation • Temperature Measurements DS20006414C-page 1

MCP3465R

Package Type 12-Lead UQFN* (2 mm x 2 mm x 0.55 mm)

AV DD

DV DD

DGND

A. MCP3465R: Single Channel Device

12 11 10 A GND 1 9 SDO

EP 13 REFIN- 2 8 SDI CH1 5 6

CS 7 SCK 4

CH0 REFIN+ 3 *Includes Exposed Thermal Pad (EP); see Table 3-1.

Functional Block Diagram

REFIN+/OUT AV DD Voltage + 2.4V Reference - REFINDV DD AMCLK VREF_SEL DMCLK/DRCLK Clock Generation (RC Oscillator) V REF- V REF+ DMCLK V

IN+ V INCH0 CH1 TEMP Diodes + x SINC 3 Filter with Digital

Gain POR AV DD Monitoring A GND ANALOG SINC 1 Filter Offset/Gain Calibration Digital SPI Interface and control OSR[3:0] PRE[1:0]

SDO SDI SCK CS A/D

Converter Burnout Current Sources DS20006414C-page 2 - nd  2 Order Modulator with Analog

Gain Analog Differential Multiplexer A GND AV DD + POR DV DD Monitoring DIGITAL D GND  2020-2021 Microchip Technology Inc.

MCP3465R

1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings †

DV DD, AV DD ....................................................................................................................................................-0.3 to 4.0V Digital Inputs and Outputs w.r.t. D GND ............................................................................................ -0.3V to DV DD + 0.3V Analog Inputs w.r.t. A GND .................................................................................................................-0.3V to AV DD + 0.3V Current at Input Pins ...............................................................................................................................................±5 mA Current at Output and Supply Pins ...................................................................................................................... ±20 mA Storage Temperature .............................................................................................................................. -65°C to +150°C Ambient Temperature with Power Applied .............................................................................................. -65°C to +125°C Soldering Temperature of Leads (10 seconds) ..................................................................................................... +300°C Maximum Junction Temperature (T J ) ........................................................................................... .........................+150°C ESD on All Pins (HBM)  6.0 kV † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

 2020-2021 Microchip Technology Inc. DS20006414C-page 3

MCP3465R

ELECTRICAL CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV DD = 2.7V to 3.6V, DV DD = 1.8V to AV DD + 0.1V, MCLK = 4.9152 MHz, V REF = AV DD , ADC_MODE[1:0] = 11. All other register map bits to their default conditions,

Parameters Sym. Min. Typ. Max. Units V Conditions

Supply Requirements Analog Operating Voltage AV DD 2.7 — 3.6 Digital Operating Voltage DV DD 1.8 — AV DD + 0.1 V DV DD ≤ 3.6V Analog Operating Current AI DD — 0.56 0.81 mA BOOST[1:0] = 00, 0.5x

V REF = 2.4V internal

V REF = 2.4V internal

V REF = 2.4V internal

V REF = 2.4V internal Analog Operating Current AI DD Digital Operating Current DI DD — 0.25 0.37 mA (Note 8) Analog Partial Shutdown Current

Digital Partial Shutdown Current

Analog Full Shutdown Current AI DDS_FS — — 0.4 µA CONFIG0 = 0x00 with Full

Shutdown Fast-CMD Digital Full Shutdown Current DI DDS_FS — — 2 µA CONFIG0 = 0x00 with Full

Shutdown Fast-CMD V POR_A — 1.75 — V For analog circuits V POR_D — 1.2 — V For digital circuits POR Hysteresis V POR_HYS — 150 — mV POR Reset Time t POR — 1 — µs Power-on Reset (POR) Threshold Voltage Note 1:

2: 3: 4: 5:

This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. REFIN- must be connected to ground for single-ended measurements. Full-Scale Range (FSR) = 2 x V REF /Gain. This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between the two input pins of the channel selected with the input multiplexer. 6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical

Performance Curves”. 7: INL is the difference between the endpoints’ line and the measured code at the center of the quantization band. 8: DI DD is measured while no transfer is present on the SPI bus. 9: An external buffer is recommended for external use. 10: Start-up time is the reaction time to the SPI command. 11: Settling time depends on bypass caps on the REFIN+/OUT pin.

DS20006414C-page 4  2020-2021 Microchip Technology Inc.

MCP3465R

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV DD = 2.7V to 3.6V, DV DD = 1.8V to AV DD + 0.1V, MCLK = 4.9152 MHz, V REF = AV DD , ADC_MODE[1:0] = 11. All other register map bits to their default conditions,

Parameters Sym. Min. Typ. Max. Units Conditions Input Voltage at Input Pin CH N A GND – 0.1 — AV DD + 0.1 V Differential Input Range V IN -V REF /Gain — +V REF /Gain V Differential Input Impedance (Note 5)

Z IN — 510 — k Gain = 0.33x, proportional to

1/AMCLK — 260 — k Gain = 1x, proportional to

1/AMCLK — 150 — k Gain = 2x, proportional to

1/AMCLK — 80 — k Gain = 4x, proportional to

1/AMCLK — 40 — k Gain = 8x, proportional to

1/AMCLK — 20 — k Gain ≥ 16x, proportional to

1/AMCLK

Internal V REF Absolute Voltage I VREF -2% 2.4 +2% V Internal V REF Temperature Coefficient

(Note 2) Internal V REF Temperature Coefficient

(Note 2) Voltage Reference Buffer Short-Circuit Current I REF_SC — — 8 mA REFIN+/OUT shorted to A GND ,

Internal Reference Settling Time t VREF_SET — 12 — ms Settling to 10 ppm from final

value, bypass capacitor 1 µF (Notes 2, 11) Internal V REF Output Noise

Analog Inputs Analog Input Leakage Current During ADC Shutdown Analog inputs are measured with respect to A GND Internal Voltage Reference

Note 1:

2: 3: 4: 5:

This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. REFIN- must be connected to ground for single-ended measurements. Full-Scale Range (FSR) = 2 x V REF /Gain. This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between the two input pins of the channel selected with the input multiplexer. 6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical

Performance Curves”. 7: INL is the difference between the endpoints’ line and the measured code at the center of the quantization band. 8: DI DD is measured while no transfer is present on the SPI bus. 9: An external buffer is recommended for external use. 10: Start-up time is the reaction time to the SPI command. 11: Settling time depends on bypass caps on the REFIN+/OUT pin.

 2020-2021 Microchip Technology Inc. DS20006414C-page 5

MCP3465R

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV DD = 2.7V to 3.6V, DV DD = 1.8V to AV DD + 0.1V, MCLK = 4.9152 MHz, V REF = AV DD , ADC_MODE[1:0] = 11. All other register map bits to their default conditions,

Parameters Sym. Min. Typ. Max. Units Conditions

External Voltage Reference Input Reference Voltage Range (V REF + – V REF -)

External Noninverting Input Voltage Reference V REF + V REF - + 0.6 — AV DD V External Inverting Input Voltage Reference V REF - A GND — V REF + – 0.6 V Resolution 16 — — Bits OSR ≥ 256 (Note 1)

-(0.05 + 0.8/

— 0.05 + 0.8/ DC Performance No Missing Code Resolution Offset Error Offset Error Temperature Coefficient

Gain Error Gain Error Temperature Coefficient Integral Nonlinearity (Note 7)

AV DD Power Supply Rejection Ratio DV DD Power Supply Rejection Ratio DC PSRR — -110 — dB DV DD varies from 1.8V to 3.6V,

V IN = 0V DC Common-Mode Rejection Ratio DC CMRR — -126 — dB V INCOM varies from 0V to AV DD ,

V IN = 0V Note 1:

2: 3: 4: 5:

This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. REFIN- must be connected to ground for single-ended measurements. Full-Scale Range (FSR) = 2 x V REF /Gain. This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between the two input pins of the channel selected with the input multiplexer. 6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical

Performance Curves”. 7: INL is the difference between the endpoints’ line and the measured code at the center of the quantization band. 8: DI DD is measured while no transfer is present on the SPI bus. 9: An external buffer is recommended for external use. 10: Start-up time is the reaction time to the SPI command. 11: Settling time depends on bypass caps on the REFIN+/OUT pin.

DS20006414C-page 6  2020-2021 Microchip Technology Inc.

MCP3465R

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV DD = 2.7V to 3.6V, DV DD = 1.8V to AV DD + 0.1V, MCLK = 4.9152 MHz, V REF = AV DD , ADC_MODE[1:0] = 11. All other register map bits to their default conditions,

Parameters Sym. Min. Typ. Max. Units Conditions

V REF = 2.4V internal, bypass capacitor 0.1 µF and

V REF = 2.4V internal, bypass capacitor 0.1 µF and

and T A = +25°C, includes the first 10 harmonics (Note 2)

V REF = 2.4V internal, bypass capacitor 0.1 µF and T A = +25°C, includes the first 10 harmonics (Note 2)

V REF = 2.4V internal, bypass capacitor 0.1 µF and

AC Performance Signal-to-Noise and Distortion Ratio Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range SNR THD SFDR Input Channel Crosstalk CTALK — -130 — dB V IN = 0V, Perturbation = 0 dB at

50 Hz, applies to all perturbation channels and all input channels AC Power Supply Rejection Ratio AC PSRR — -75 – 20 x

LOG (GAIN)

AC Common-Mode Rejection Ratio AC CMRR — -122 — dB V INCOM = 0 dB at 50 Hz,

V IN = 0V Note 1:

2: 3: 4: 5:

This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. REFIN- must be connected to ground for single-ended measurements. Full-Scale Range (FSR) = 2 x V REF /Gain. This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between the two input pins of the channel selected with the input multiplexer. 6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical

Performance Curves”. 7: INL is the difference between the endpoints’ line and the measured code at the center of the quantization band. 8: DI DD is measured while no transfer is present on the SPI bus. 9: An external buffer is recommended for external use. 10: Start-up time is the reaction time to the SPI command. 11: Settling time depends on bypass caps on the REFIN+/OUT pin.

 2020-2021 Microchip Technology Inc. DS20006414C-page 7

MCP3465R

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply at AV DD = 2.7V to 3.6V, DV DD = 1.8V to AV DD + 0.1V, MCLK = 4.9152 MHz, V REF = AV DD , ADC_MODE[1:0] = 11. All other register map bits to their default conditions,

Parameters Sym. Min. Typ. Max. Units Conditions

ADC Timing Parameters Sampling Frequency DMCLK See Table 5-6 MHz See Figure 4-1 Output Data Rate DRCLK See Table 5-6 ksps See Figure 4-1 ms See Figure 4-1 Data Conversion Time T CONV ADC Start-up Delay T ADC_SETUP See Table 5-6 — 256 — DMCLK

periods ADC_MODE[1:0] bits change from ‘0x’ to ‘1x’ — 0 — DMCLK

periods ADC_MODE[1:0] bits change from ‘10’ to ‘11’ T DLY_SCAN 0 — 512 DMCLK

periods Time delay between sampling channels T TIMER_SCAN 0 — 16777215 DMCLK

periods Time interval between SCAN cycles Data Transfer Time to DR (Data Ready Event)

t DODR — — 50 ns Modulator Output Valid from AMCLK High SCAN Mode Time Delays

External Master Clock Input (CLK_SEL[1] = 0) (MCLK = SCK)

1 — 10 MHz DV DD < 2.7V f MCLK_DUTY 45 — 55 %

Internal Oscillator Start-up Time t OSC_STARTUP — 10 — µs CLK_SEL[1] changes from ‘0’

to ‘1’, time to stabilize the clock frequency to ±1 kHz of the final value (Note 10) Internal Oscillator Current Consumption IDD OSC — 30 — µA Should be added to DI DD when

T Acc — ±5 — °C See Section 5.1.2 “Internal

Temperature Sensor” Master Clock Input Frequency Range f MCLK_EXT Master Clock Input Duty Cycle Internal Clock Oscillator Internal Master Clock Frequency Internal Temperature Sensor Temperature Measurement Accuracy Note 1:

2: 3: 4: 5:

This parameter is ensured by design and not 100% tested. This parameter is ensured by characterization and not 100% tested. REFIN- must be connected to ground for single-ended measurements. Full-Scale Range (FSR) = 2 x V REF /Gain. This input impedance is due to the internal input sampling capacitor and frequency. This impedance is measured between the two input pins of the channel selected with the input multiplexer. 6: Applies to all analog gains. Offset and gain errors depend on analog gain settings. See Section 2.0 “Typical

Performance Curves”. 7: INL is the difference between the endpoints’ line and the measured code at the center of the quantization band. 8: DI DD is measured while no transfer is present on the SPI bus. 9: An external buffer is recommended for external use. 10: Start-up time is the reaction time to the SPI command. 11: Settling time depends on bypass caps on the REFIN+/OUT pin.

DS20006414C-page 8  2020-2021 Microchip Technology Inc.

MCP3465R

TEMPERATURE SPECIFICATIONS

Electrical Specifications: Unless otherwise specified, all parameters apply for T A = -40°C to +125°C, AV DD = 2.7V to 3.6V, DV DD = 1.8V to AV DD + 0.1V, D GND = A GND = 0V.

Output Valid from CS Low  2020-2021 Microchip Technology Inc.

Conditions DS20006414C-page 9

MCP3465R

TABLE 1-2: SPI SERIAL INTERFACE TIMING SPECIFICATIONS FOR DV DD = 1.8V TO 2.7V (10 MHz MAXIMUM SCK FREQUENCY)

Parameters Sym. Min. Typ. Max. Units Schmitt Trigger High-Level Input Voltage V IH 0.7 x DV DD — — V Schmitt Trigger Low-Level Input Voltage V IL — — 0.3 x DV DD V Hysteresis of Schmitt Trigger Inputs V HYS — 200 — mV Conditions Low-Level Output Voltage V OL — — 0.2 x DV DD V I OL = +1.5 mA High-Level Output Voltage V OH 0.8 x DV DD — — V I OH = -1.5 mA Input Leakage Current I LI_D — — 1 µA Pins configured as inputs

or high-impedance outputs DS20006414C-page 10  2020-2021 Microchip Technology Inc.

MCP3465R

t CSD

CS

t SC K t CLE t H I t CSS t L O t C SH t C LD

SPI mode 1,1 SPI mode 1,1

SCK

SPI mode 0,0 SPI mode 0,0

Device Latches SDI on SCK Rising Edge

t SU SDI SDO

t H D t DO t HO t C SSD O High-Z t D IS High-Z 0 (for first two bits on SDO)

FIGURE 1-1:

Device Latches SDO on SCK Falling Edge High-Z 0

Serial Output Timing Diagram.

 2020-2021 Microchip Technology Inc. DS20006414C-page 11

MCP3465R

NOTES:

DS20006414C-page 12  2020-2021 Microchip Technology Inc.

MCP3465R

2.0 TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) therefore outside the warranted range. Note: Unless otherwise indicated, AV DD = 3.3V; DV DD = 3.3V; T A = +25°C; MCLK = 4.9152 MHz; V IN = -0.5 dBFS at 50 Hz; V REF = AV DD ; ADC_MODE = 11. All other registers are set to the default value. Histogram ticks are centered at their bin center.

-40 -60 -80 -100 -120 -140 -160 0 -40 -60 -80 -100 -120 -140 -160 -180 -180

0 500 1000 1500

Frequency (Hz)

2000 0 2500 1500 2000 2500 70000 V IN = -0.5 dBFS @ 1 kHz FFT 16384 samples Occurrence (Counts) -40 -60 -80 -100 -120 -140 -160

64000 samples Bin size = 1 LSE 60000

50000

Histograms may show up to 2 bins equally distributed if offset is close to a round LSE value (Intrinsic noise << 16-bit quantization noise)

40000

30000

20000

10000

0 -180

0 500 1000 1500 2000 -10 2500 -9 -8

Frequency (Hz)

FIGURE 2-5: (External V REF ).

Occurrence (Counts)

-20 -7 -6 -5 -4 -3 -2 -1 0 ADC Output Code (LSE)

FIGURE 2-2: FFT Output Spectrum, f in = 1 kHz (External V REF ).

Output Amplitude (dBFS)

1000

FIGURE 2-4: FFT Output Spectrum, f in = 1 kHz (Internal V REF ).

0 -20 500

Frequency (Hz)

FIGURE 2-1: FFT Output Spectrum,

Output Amplitude (dBFS)

V IN = -0.5 dBFS @ 1 kHz FFT 16384 samples -20 Output Amplitude (dBFS)

Output Amplitude (dBFS)

0 -20 -40 -60 -80 -100 -120 -140 -160 60000

50000

40000

30000

20000

Output Noise Histogram

Bin size = 1 LSB Histograms may show up to 2 bins equally distributed if offset is close to a round LSB value (Intrinsic noise << 16-bit quantization noise) 10000

0 -180

0 500 1000 1500

Frequency (Hz)

2000 2500

FIGURE 2-3: FFT Output Spectrum,

 2020-2021 Microchip Technology Inc.

-12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2

ADC Output Code (LSB)

FIGURE 2-6: (Internal V REF ). Output Noise Histogram

DS20006414C-page 13

MCP3465R

Unless otherwise indicated, AV DD = 3.3V; DV DD = 3.3V; T A = +25°C; MCLK = 4.9152 MHz; V IN = -0.5 dBFS at 50 Hz; V REF = AV DD ; ADC_MODE = 11. All other registers are set to the default value. Histogram ticks are centered at their bin center.

100

FIGURE 2-10:

V REF .

INL vs. Input Voltage. FIGURE 2-11:

V REF .

Output Noise vs. Input

6 4 2 0 0.25 0.5

FIGURE 2-9:

DS20006414C-page 14 1 2

Analog Gain 4 8

Maximum INL vs. Gain.

65536 131072 32768 8192 16384 4096 2048 65536 -80

-100

-120

-140 16

Oversampling Ratio (OSR)

FIGURE 2-12:

131072 8 -60 65536 10 -40 32768 AVDD = VREF = 3.6V, +125°C 16384 12 AVDD = VREF = 3.6V, -40°C

-20 8192 14 AVDD = VREF = 2.7V, +125°C 4096 16 0 AVDD = VREF = 2.7V, -40°C 2048 18 Total Harmonic Distortion (dBc)

Maximum INL (ppm of 2*V REF )

20

SNR vs. OSR External

1024

FIGURE 2-8: Voltage.

1024 Oversampling Ratio (OSR) 131072 100 32768 50 16384 0 Differential Input Voltage (% of V REF )

512 -50 0 256 0 -100 8192 0.5 20 4096 1 2048 1.5

40 1024 2 60 512 2.5 80 256

100 128 4 3.5

SINAD vs. OSR External

120 AVDD = VREF = 2.7V, -40°C AVDD = VREF = 2.7V, +125°C AVDD = VREF = 3.6V, -40°C AVDD = VREF = 3.6V, +125°C Signal-to-Noise Ratio (dB)

RMS Noise (ppm of 2*V REF )

5 4.5 512

Oversampling Ratio (OSR)

128

FIGURE 2-7:

100 64 -50 0 50 Differential Input Voltage (% of V REF )

0 64 -6 -100 20 256 -4

40 64 -2 60 128 0 80 32 Gain = 1x 32 4 2 120 AVDD = VREF = 2.7V, -40°C AVDD = VREF = 2.7V, +125°C AVDD = VREF = 3.6V, -40°C AVDD = VREF = 3.6V, +125°C 32 Integral Non-Linearity (ppm of 2*V REF )

6 Signal-to-Noise and Distortion Ratio (dB)

Note: THD vs. OSR External V REF .

 2020-2021 Microchip Technology Inc.

MCP3465R

Note: Unless otherwise indicated, AV DD = 3.3V; DV DD = 3.3V; T A = +25°C; MCLK = 4.9152 MHz; V IN = -0.5 dBFS at 50 Hz; V REF = AV DD ; ADC_MODE = 11. All other registers are set to the default value. Histogram ticks are centered at their bin center.

0

FIGURE 2-13:

V REF .

-100

-120 Oversampling Ratio (OSR) 131072

65536 32768 16384 8192 2048 4096 1024 512 -140

FIGURE 2-16: SFDR vs. OSR External THD vs. OSR Internal V REF .

Oversampling Ratio (OSR)

FIGURE 2-14:

V REF .

80

FIGURE 2-15:

131072 65536 16384 8192 4096 2048 1024 512 256 128 64 32 Oversampling Ratio (OSR) 32768

0

SNR vs. OSR Internal V REF .

 2020-2021 Microchip Technology Inc.

50 45 40 35 30 25 20 15 10 5 0 131072 65536 32768 8192 16384 4096 2048 1024 512 0

SFDR vs. OSR Internal

33 devices x 3 lots Bin Size: 0.05 dB 97.00 97.05 97.10 97.15 97.20 97.25 97.30 97.35 97.40 97.45 97.50 97.55 97.60 97.65 97.70 97.75 97.80 97.85 97.90 97.95 98.00 Occurrence (Counts) 100 20 20 Oversampling Ratio (OSR)

120 40 40

FIGURE 2-17:

V REF .

SINAD vs. OSR Internal

60

60 256 16384 8192 4096 2048 1024 512 256 128 64 32 0 131072 20 65536 40 32768

80 128 60 100 64 80 120 32 100 Spurious-Free Dynamic Range (dBc)

140 120 Signal-to-Noise Ratio (dB)

-80 256 8192 16384 4096 2048 1024 512 256 64 128 0 -60 64 20 131072 40 65536 60 32768

-40 128 80

-20 32 100 Oversampling Ratio (OSR)

Signal-to-Noise and Distortion Ratio (dB)

Total Harmonic Distortion (dBc) 120 32 Spurious-Free Dynamic Range (dBc)

140 Signal-to-Noise Ratio (dB)

FIGURE 2-18: External V REF . SNR Distribution Histogram

DS20006414C-page 15

MCP3465R

Note: Unless otherwise indicated, AV DD = 3.3V; DV DD = 3.3V; T A = +25°C; MCLK = 4.9152 MHz;

V IN = -0.5 dBFS at 50 Hz; V REF = AV DD ; ADC_MODE = 11. All other registers are set to the default value. Histogram ticks are centered at their bin center.

45 35 30 25 20 15 10 5 33 devices x 3 lots Bin Size: 0.05 dB 35 Occurrence (Counts)

Occurrence (Counts)

40 33 devices x 3 lots Bin Size: 0.05 dB 40

30 25 20 15 10 5 0 97.00 97.05 97.10 97.15 97.20 97.25 97.30 97.35 97.40 97.45 97.50 97.55 97.60 97.65 97.70 97.75 97.80 97.85 97.90 97.95 98.00 95.55 95.60 95.65 95.70 95.75 95.80 95.85 95.90 95.95 96.00 96.05 96.10 96.15 96.20 96.25 96.30 96.35 96.40 96.45 96.50 96.55 0 Signal-to-Noise Ratio (dB) Signal-to-Noise-and-Distortion Ratio (dB)

20 18 16 14 12 10 8 6 4 2 0

FIGURE 2-22: Internal V REF .

33 devices x 3 lots Bin Size: 0.05 dB Occurrence (Counts)

35 30 25 20 15 10 5 95.35 95.40 95.45 95.50 95.55 95.60 95.65 95.70 95.75 95.80 95.85 95.90 95.95 96.00 96.05 96.10 96.15 96.20 96.25 96.30 96.35 0 Signal-to-Noise-and-Distortion Ratio (dB) Total Harmonic Distortion (dBc)

25

THD Distribution Histogram

33 devices x 3 lots Bin Size: 1.0 dB 20 15 10 5

FIGURE 2-23: SINAD Distribution Histogram Internal V REF .

35 Occurrence (Counts)

FIGURE 2-20: External V REF .

Occurrence (Counts)

SNR Distribution Histogram

40 33 devices x 3 lots Bin Size: 0.5 dB -120.0 -119.5 -119.0 -118.5 -118.0 -117.5 -117.0 -116.5 -116.0 -115.5 -115.0 -114.5 -114.0 -113.5 -113.0 -112.5 -112.0 Occurrence (Counts)

FIGURE 2-19: SINAD Distribution Histogram External V REF .

33 devices x 3 lots Bin Size: 0.5 dB 30

25

20

15

10

5

0 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 -114.0 -113.5 -113.0 -112.5 -112.0 -111.5 -111.0 -110.5 -110.0 -109.5 -109.0 -108.5 -108.0 -107.5 -107.0 -106.5 -106.0 0 Spurious-Free Dynamic Range (dBc) Total Harmonic Distortion (dBc)

FIGURE 2-21: SFDR Distribution Histogram External V REF .

DS20006414C-page 16

FIGURE 2-24: Internal V REF . THD Distribution Histogram

 2020-2021 Microchip Technology Inc.

MCP3465R

50 45 40 35 30 25 20 15 10 5 0 33 devices x 3 lots Bin Size: 1.0 dB Total Harmonic Distortion (dBc)

Unless otherwise indicated, AV DD = 3.3V; DV DD = 3.3V; T A = +25°C; MCLK = 4.9152 MHz; V IN = -0.5 dBFS at 50 Hz; V REF = AV DD ; ADC_MODE = 11. All other registers are set to the default value. Histogram ticks are centered at their bin center.

0

GAIN=0.33 GAIN=1 GAIN=2 GAIN=4 GAIN=8 GAIN=16 -20 -40 -60 -80 -100

104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 Occurrence (Counts)

Note:

-120 -50 Spurious-Free Dynamic Range (dBc)

FIGURE 2-25: SFDR Distribution Histogram Internal V REF .

-25 0

FIGURE 2-28: External V REF .

25 50 75 Temperature (°C)

100 125

THD vs. Temperature,

80 60

GAIN=0.33 GAIN=1 GAIN=2 GAIN=4 GAIN=8 GAIN=16 40 20 0 -50 -25 0 25 50

Temperature (°C)

FIGURE 2-26: External V REF .

75 100 140

120

100

80

SINAD vs. Temperature,

GAIN=0.33 GAIN=1 GAIN=2 GAIN=4 GAIN=8 GAIN=16 60

40

20

0 125 120 Signal-to-Noise Ratio (dB)

Spurious-Free Dynamic Range (dBc) 100 -50 -25

FIGURE 2-29: External V REF .

0 25 50 75

Temperature (°C)

100 125

SFDR vs. Temperature,

120 100 Signal-to-Noise and Distortion Ratio (dB)

Signal-to-Noise and Distortion Ratio (dB)

120 100 80 60

GAIN=0.33 GAIN=1 GAIN=2 GAIN=4 GAIN=8 GAIN=16 40 20 0 -50 -25

FIGURE 2-27: External V REF .

0 25 50 75

Temperature (°C)

100

SNR vs. Temperature,

 2020-2021 Microchip Technology Inc.

125 80 60

40 20 0 -50 -25

FIGURE 2-30: Internal V REF .

0 25 50 Temperature (°C)

75 100 125

SINAD vs. Temperature,

DS20006414C-page 17

MCP3465R

Note: Unless otherwise indicated, AV DD = 3.3V; DV DD = 3.3V; T A = +25°C; MCLK = 4.9152 MHz;

V IN = -0.5 dBFS at 50 Hz; V REF = AV DD ; ADC_MODE = 11. All other registers are set to the default value. Histogram ticks are centered at their bin center.

140

FIGURE 2-31: Internal V REF . SNR vs. Temperature,

Internal V REF .

2

FIGURE 2-34: Dynamic Performance vs. Input Signal Amplitude.

20 120

100

80

60

40

20

0 -50 -25 0

FIGURE 2-33: Internal V REF .

DS20006414C-page 18 25 50 75 Temperature (°C)

100 125

SFDR vs. Temperature,

Signal-to-Noise and Distortion Ratio (dB) Spurious-Free Dynamic Range (dBc)

100

GAIN=2 GAIN=4 GAIN=8 GAIN=16 BOOST = 0.66x 95 90 85 80 75 70

0 15 5 10

$MCLK Frequency (MHz)

20

FIGURE 2-36: SINAD vs. AMCLK

 2020-2021 Microchip Technology Inc.

MCP3465R

Unless otherwise indicated, AV DD = 3.3V; DV DD = 3.3V; T A = +25°C; MCLK = 4.9152 MHz; V IN = -0.5 dBFS at 50 Hz; V REF = AV DD ; ADC_MODE = 11. All other registers are set to the default value. Histogram ticks are centered at their bin center.

Signal-to-Noise and Distortion Ratio (dB)

Signal-to-Noise and Distortion Ratio (dB)

100 95 90 85

GAIN=0.33 GAIN=1 GAIN=2 GAIN=4 GAIN=8 GAIN=16 BOOST = 1x 80 75 70

0 15 5 10

$MCLK Frequency (MHz)

FIGURE 2-37:

105 100 95 90 85 80 75 70

0 15 5 10

$MCLK Frequency (MHz)

FIGURE 2-38:

Signal-to-Noise and Distortion Ratio (dB)

90 85 20 95 90 85

80 75 70

0

5 10 15 AMCLK Frequency (MHz)

20

105 100 70  2020-2021 Microchip Technology Inc.

5 10 15 AMCLK Frequency (MHz)

100 110 75

FIGURE 2-39: SINAD vs. AMCLK (BOOST = 0.5x, Internal V REF ).

0 115 80 5 10 15 AMCLK Frequency (MHz)

70 120 0 75

FIGURE 2-41: SINAD vs. AMCLK (BOOST = 1x, Internal V REF ).

95 80 20

SINAD vs. AMCLK

100 85 Signal-to-Noise and Distortion Ratio (dB)

Signal-to-Noise and Distortion Ratio (dB)

110 90

FIGURE 2-40: SINAD vs. AMCLK (BOOST = 0.66x, Internal V REF ).

GAIN=0.33 GAIN=1 GAIN=2 GAIN=4 GAIN=8 GAIN=16 BOOST = 2x 115

95 20

SINAD vs. AMCLK

120 100 Signal-to-Noise and Distortion Ratio (dB)

Note:

20 95 90 85 80 75 70

0 5 10 15

AMCLK Frequency (MHz)

20

FIGURE 2-42: SINAD vs. AMCLK (BOOST = 2x, Internal V REF ).

DS20006414C-page 19

MCP3465R

Note: Unless otherwise indicated, AV DD = 3.3V; DV DD = 3.3V; T A = +25°C; MCLK = 4.9152 MHz;

V IN = -0.5 dBFS at 50 Hz; V REF = AV DD ; ADC_MODE = 11. All other registers are set to the default value. Histogram ticks are centered at their bin center.

Signal-to-Noise and Distortion Ratio

AV DD .

1,200 80 60 20 5,000 500 50 5 0 Analog Input Signal Frequency (Hz)

FIGURE 2-44: Frequency.

50,000

1,000 800 T A = 25°C, AZ_MUX = 1 600 400 200 0 2.7 3 3.3

AV DD Supply Voltage (V)

FIGURE 2-47:

SINAD vs. Input Signal

0 3.6

Offset Error vs. AV DD

Voltage 1,000 Input-Referred Offset Error (nV) 100 40

120 Signal-to-Noise and Distortion Ratio (dB)

Error (μV)

800

AV DD Supply Voltage (V)

FIGURE 2-45:

DS20006414C-page 20

Offset Error vs. AV DD FIGURE 2-48:

0 25 50 Temperature (°C)

75 100 125

Offset Error vs. Temperature

 2020-2021 Microchip Technology Inc.

MCP3465R

Note: Unless otherwise indicated, AV DD = 3.3V; DV DD = 3.3V; T A = +25°C; MCLK = 4.9152 MHz;

V IN = -0.5 dBFS at 50 Hz; V REF = AV DD ; ADC_MODE = 11. All other registers are set to the default value. Histogram ticks are centered at their bin center.

AV DD Supply Voltage (V) FIGURE 2-49:

MCLK Frequency (MHz) FIGURE 2-52: vs. MCLK.

Gain Error vs. AV DD .

2 25

Differential Input Impedance 10M Error (%)

1.6 1.4 1.2

1

Output (LSB)

1.8 100K

-50 -25 0 25 50

Temperature (°C) FIGURE 2-50:

Gain Error vs. Temperature.

-4 0.2 DI -5 0

-25 0 25 50

Temperature (°C)

75 100 125 FIGURE 2-51: Temperature Sensor Accuracy vs. Temperature (First Order Best Fit).

 2020-2021 Microchip Technology Inc.

100M FIGURE 2-53: ADC Output Code vs. Differential Input Impedance, Burnout Current Sources Enabled.

-50 Differential Input Impedance (:)

TACC (°C)

1M 0 FIGURE 2-54:

5 10 15 MCLK Frequency (MHz)

20 DI DD and AI DD vs. MCLK.

DS20006414C-page 21

MCP3465R

Note: Unless otherwise indicated, AV DD = 3.3V; DV DD = 3.3V; T A = +25°C; MCLK = 4.9152 MHz;

V IN = -0.5 dBFS at 50 Hz; V REF = AV DD ; ADC_MODE = 11. All other registers are set to the default value. Histogram ticks are centered at their bin center.

2.5

2.41186

Internal V REF Output

DI DD 1.8 2.1 2.4 2.7 3

AV DD /DV DD (V) FIGURE 2-55: and AV DD .

3.3 2.41182

2.41181

2.4118

2.41179 Output Noise = 14.3 ȝV

RMS 100 Samples (100 ms per sample)

0 3.6 2 4

Time (s)

6 8 10 FIGURE 2-58: V REF Output vs. Time

DI DD and AI DD vs. DV DD 2.5 2.415

11 Devices x 3 Lots

Internal V REF output (V)

2 2.41183 2.41178 0

0 2.405

2.4

2.395

2.39

2.385

2.38 0 5 10 15

MCLK Frequency (MHz)

20 AI DD vs. MCLK (Internal FIGURE 2-56: V REF ).

-50

0 -50 -25 0 FIGURE 2-57: Temperature.

DS20006414C-page 22 25 50 75 Temperature ( ƕ C) DI DD and AI DD vs.

100 125 Internal V REF Output (V)

2 -25 0 25 50

Temperature (°C)

75 100 125 FIGURE 2-59: V REF Output Voltage vs.

2.5 2.41184 2.3988 2.3987 2.3986 2.3985 2.3984 2.3983 2.3982 2.3981 2.398 2.3979 2.3978

2.7 2.8 2.9 FIGURE 2-60: Voltage vs. AV DD .

3 3.1 3.2 AV DD (V)

3.3 3.4 3.5 3.6 Internal V REF Output  2020-2021 Microchip Technology Inc.

MCP3465R

2.1 Noise Specifications

Table 2-1 and Table 2-2 summarize the noise performance of the MCP3465R device. The noise performance is an analog gain function of the ADC (digital gain does not change the noise performance significantly) and the OSR, chosen through the user interface. With a higher gain, the input referred noise is reduced. With a higher OSR setting, the noise is also reduced, as the oversampling diminishes both thermal noise and the quantization noise induced by the Delta-Sigma modulator loop. The noise value generally increases when temperature is higher as thermal noise is dominant for all OSR larger than 32. For high OSR settings (> 512), the thermal noise is largely dominant and increases proportionally to the square root of the absolute temperature. The performance in Table 2-1 to Table 2-4 has been measured with the device placed in Continuous Conversion mode, with the differential input voltage equal to V IN = 0V, default conditions for the register map and MCLK = 4.9152 MHz. The noise performance is also a function of the measurement duration. For short duration measurements (low number of consecutive samples), the peak-to-peak noise is usually reduced, because the crest factor (ratio between the RMS noise and peak-to-peak noise) is reduced. This is a consequence of the noise distribution being Gaussian by nature (see Figure 2-5 for noise histogram example and fitting with an ideal Gaussian distribution). The noise specifications have been measured with a sample size of 16384 samples for low OSR values and have been capped to approximately 80 seconds for the 16384 samples, leading to a larger duration. The noise specifications are expressed in two different values, which lead to the same quantity. It is more practical to choose one of these representations depending on the desired application. In Table 2-1, the RMS (Root Mean Square) noise is the variance of the ADC output code, expressed in µV RMS and the input referred to with Equation 5-5. The peak-to-peak noise values are in parentheses. The peak-to-peak noise is the difference between the maximum and minimum code observed during the complete time of the measurement (see Equation 5-5). In Table 2-2, the noise is expressed in Effective Resolution (ER). The Effective Resolution is a ratio of the full-scale range of the ADC (that depends on V REF and gain) and the noise performance of the device. The Effective Resolution can be determined from the RMS or peak-to-peak noise with Equation 2-1 and Equation 2-2.

 2020-2021 Microchip Technology Inc.

EQUATION 2-1:

EQUATION 2-2:

Due to the nature of the noise, the performance detailed in the noise tables can vary significantly from one measurement to another. They present an averaging of the performance over a large distribution of parts over multiple lots. They give the typical expectation of the noise performance, but performance can be better or worse if a limited number of measurements is performed. For large gain and OSR combinations, if the noise performance is comparable to the quantization step (1 LSb), the performance is limited to 0.5 LSb for the RMS noise and 1 LSb for the peak-to-peak noise (same limits for Effective Resolution values). These figures correspond to the resolution limit of the device, as peak-to-peak noise cannot be better than 1 LSb. Similarly, if the intrinsic RMS noise of the device is much smaller than 0.5 LSb, it can lead to histogram with either one or two bins, depending on the relative position of the input voltage versus the possible quantized outputs of the ADC. If the position is exactly in between two quantization steps, the histogram of output noise will have two bins with exactly 50% occurrence on each. This case gives an RMS noise of a 0.5 LSb value, which is therefore, used as a cap of the performance for the sake of clarity and a better representation on the noise tables. The noise specifications are improved by a ratio of approximately √2 (or 0.5-bit Effective Resolution) when the AZ_MUX setting is enabled. However, the output data rate is significantly reduced (see Figure 5-5 and Table 5-6). The digital gain added for Gain = 32x and 64x settings is not significant for the noise performance, therefore the noise values can be extracted from the Gain = 16x columns. Effective Resolution performance is degraded by 1 bit for Gain = 32x and 2 bits for Gain = 64x, compared to Gain = 16x performance.

Note: All Output Noise performance-related

tables and figures are with reference to the input (i.e., Input Referred).

DS20006414C-page 23

MCP3465R

TABLE 2-1: OUTPUT NOISE VS. GAIN VS. OSR (AV DD = DV DD = V REF = 3.3V, T A = +25°C)

RMS (Peak-to-Peak) Noise (µV) Total OSR Gain = 0.33 Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 32 388.9 (2829.9) 130.2 (950) 65.7 (481.7) 33.2 (240.9) 17 (125.5) 8.9 (66.9) 64 151.1 (564) 50.4 (184.6) 25.2 (102.4) 12.6 (56.2) 6.3 (34.8) 3.4 (22.5) 128 151.1 (302.1) 50.4 (107.4) 25.2 (57.1) 12.6 (33.6) 6.3 (21.4) 3.2 (14.3) 256 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (15.9) 3.2 (10.5) 512 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.9) 1024 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 2048 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 4096 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 8192 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 16384 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 20480 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 24576 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 40960 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 49152 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 81920 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3) 98304 151.1 (302.1) 50.4 (100.7) 25.2 (50.4) 12.6 (25.2) 6.3 (12.6) 3.2 (6.3)

TABLE 2-2: EFFECTIVE RESOLUTION VS. GAIN VS. OSR (AV DD = DV DD = V REF = 3.3V,

Effective Resolution RMS (Peak-to-Peak) (bits) Total OSR Gain = 0.33 Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16 32 15.6 (12.8) 15.6 (12.8) 15.6 (12.7) 15.6 (12.7) 15.6 (12.7) 15.5 (12.6) 64 17 (15.2) 17 (15.2) 17 (15) 17 (14.9) 17 (14.5) 16.9 (14.2) 128 17 (16) 17 (15.9) 17 (15.9) 17 (15.6) 17 (15.3) 17 (14.9) 256 17 (16) 17 (16) 17 (16) 17 (16) 17 (15.7) 17 (15.4) 512 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (15.9) 1024 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 2048 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 4096 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 8192 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 16384 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 20480 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 24576 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 40960 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 49152 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 81920 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 98304 17 (16) 17 (16) 17 (16) 17 (16) 17 (16) 17 (16)

Note: To calculate noise RMS level, and Effective Resolution (Bits) for a given GAIN and data rate, refer to the

OSR setting and associated data rate relationship shown in Table 5-6.

DS20006414C-page 24  2020-2021 Microchip Technology Inc.

MCP3465R

TABLE 2-3: OUTPUT NOISE VS. GAIN VS. OSR (AV DD = DV DD = 3.3V, V REF = 2.4V INTERNAL,

RMS (Peak-to-Peak) Noise (µV) Total OSR Gain = 0.33 Gain = 1 Gain = 2 Gain = 4 Gain = 8 Gain = 16

TABLE 2-4: EFFECTIVE RESOLUTION VS. GAIN VS. OSR (AV DD = DV DD = 3.3V, V REF = 2.4V

Effective Resolution RMS (Peak-to-Peak) (bits) Total OSR Gain = 0.33 Gain = 1 Gain = 2 Gain = 4

Note: To calculate noise RMS level, and Effective Resolution (Bits) for a given GAIN and data rate, refer to the

OSR setting and associated data rate relationship shown in Table 5-6.

 2020-2021 Microchip Technology Inc.

Gain = 8 Gain = 16 DS20006414C-page 25

MCP3465R

NOTES:

DS20006414C-page 26  2020-2021 Microchip Technology Inc.

MCP3465R

3.0 PIN DESCRIPTIONS

TABLE 3-1: PIN FUNCTION TABLE

3.1 Differential Reference Voltage Inputs: REFIN+/OUT, REFIN-

The REFIN+/OUT pin is the noninverting differential reference input (V REF +) when VREF_SEL = 0. When VREF_SEL = 1, it is the internal voltage reference output voltage as well as the ADC voltage noninverting reference pin. The REFIN- pin is the inverting differential reference input (V REF -). For single-ended reference applications, the REFINpin should be directly connected to A GND . The differential reference voltage pins must respect this condition at all times: 0.6V ≤ V REF ≤ AV DD . The differential reference voltage input is given by Equation 3-1.

EQUATION 3-1:

For optimal ADC accuracy, appropriate bypass capacitors should be placed between REFIN+/OUT and A GND at all times. Using a 0.1 µF and a 10 µF ceramic capacitor can help to decouple the reference voltage around the sampling frequency (which would lead to aliasing noise in the base band). These bypass capacitors are not mandatory for correct ADC operation, but removing these capacitors may degrade the accuracy of the ADC.

3.2 Analog Inputs (CHn): Differential or Single-Ended

The CHn pins are the analog input signal pins for the ADC. Two analog multiplexers are used to connect the CHn pins to the V IN +/V IN - analog inputs of the ADC. Each multiplexer independently selects one input to be connected to an ADC input (V IN + or V IN -). Each CHn pin can either be connected to the V IN + or V IN - inputs of the ADC. This multiplexer selection is controlled by either the MUX register in MUX mode or the SCAN register in Scan mode. See Figure 5-1 for more details on the multiplexer structure. When the input is selected by the multiplexer, the Differential (V IN ) and Common-Mode Voltage (V INCOM ) at the ADC inputs is defined by Equation 3-2.

EQUATION 3-2:

DS20006414C-page 28 The input signal level is multiplied by the internal programmable analog gain at the front end of the Delta-Sigma modulator. For single-ended input measurements, the user can select V IN - to be internally connected to A GND . The differential input voltage should not exceed an absolute of ±V REF /Gain for accurate measurement. If the input is out of range, the converter output code is saturated or overloaded, depending on how the output data format (DATA_FORMAT[1:0]) is selected. See Section 5.6 “ADC Output Data Format” for further information on the ADC output coding. The absolute voltage on each of the analog signal input pins can range from A GND – 0.1V to V DD + 0.1V. Any voltage above or below this range causes leakage currents through the Electrostatic Discharge (ESD) diodes at the input pins. This ESD current can cause unexpected performance of the device. The Common-mode of the analog inputs should be chosen such that both the differential analog input range and the absolute voltage range on each pin are within the specified operating range defined in the Electrical Characteristics table.

3.3 SPI Serial Interface Communication Pins

The SPI interface is compatible with both SPI Mode 0,0 and 1,1.

3.3.1 CHIP SELECT (CS) This is the SPI Chip Select pin that enables/disables the SPI serial communication. The CS falling edge initiates the serial communication and the rising edge terminates the communication. No communication can take place when this pin is in a Logic High state. This input is Schmitt Triggered.

3.3.2 SERIAL DATA CLOCK (SCK) This is the serial clock input pin for SPI communication. This input has a Schmitt Trigger structure. The maximum SPI clock speed is 20 MHz. Data are clocked into the device on the rising edge of SCK. Data are clocked out of the device on the falling edge of SCK. The device interface is compatible with both SPI Mode 0,0 and 1,1. SPI modes can be changed when CS is in a Logic High state. This pin is also used to input or output the MCLK clock, depending on the CLK_SEL[1:0] bits setting. When CLK_SEL[1:0] = 0x, the SCK pin is defined as the MCLK input pin, while still working as the SCK input pin for SPI communications.

 2020-2021 Microchip Technology Inc.

MCP3465R

When running conversions, SCK has to be continuously clocking at a constant frequency to ensure proper ADC accuracy. In this case, communications using the SPI interface should be synchronized on the free-running clock and can be framed with a proper usage of the CS pin. When CLK_SEL[1:0] = 10, the MCLK is running based on the internal oscillator and is not attached to the SCK pin. In this case, SCK and MCLK are asynchronous and the SCK pin is used only for the SPI interface communications. When CLK_SEL[1:0] = 11, the SCK pin becomes an output for the internal oscillator and sends a free-running clock at the AMCLK frequency. In this case, the SCK pin is still working as the SCK input for SPI communications. The MCP3465R becomes the host device for the SCK clock. The SPI communications have to be framed using this free-running clock as the time base in order to be correctly interpreted by the device.

3.3.3 SERIAL DATA OUTPUT PIN (SDO) This pin is used for the SPI Data Output (SDO). The SDO data are clocked out on the falling edge of SCK. This pin stays high-impedance under the following conditions: • When CS pin is logic high. • During the entire SPI write or Fast command

communication period after the SPI COMMAND byte has been transmitted. • After the two device address bits in the command

are transmitted, if the device address in the command does not match the internal chip device address.

3.3.4 SERIAL DATA INPUT PIN (SDI) This is the SPI Data Input (SDI) pin and it uses a Schmitt Trigger structure. When CS is logic low, this pin is used to send a COMMAND byte just after the CS falling edge, which can be followed by data words of various lengths. Data are clocked into the device on the rising edge of SCK. Toggling SDI while reading a register has no effect.

3.4 Digital Ground (D GND )

D GND is the ground connection to internal digital circuitry. To ensure accuracy and noise cancellation, D GND must be connected to the same ground as A GND , preferably with a star connection. If a digital ground plane is available, it is recommended to tie this pin to the plane of the Printed Circuit Board (PCB). This plane should also reference all other digital circuitry in the system. D GND is not internally connected to A GND and must be connected externally.

3.5 Digital Power Supply (DV DD )

DV DD is the power supply pin for the digital circuitry within the device. The voltage on this pin must be maintained in the range specified by the Electrical Characteristics table. For optimal performance, it is recommended to connect appropriate bypass capacitors (typically, a 10 µF ceramic in parallel with a 0.1 µF ceramic). DV DD is monitored by the DV DD POR monitoring circuit for the digital section.

3.6 Analog Power Supply (AV DD )

AV DD is the power supply pin for the analog circuitry within the device. The voltage on this pin must be maintained in the range specified by the Electrical Characteristics table. For optimal performance, it is recommended to connect appropriate bypass capacitors (typically, a 10 µF ceramic in parallel with a 0.1 µF ceramic). AV DD is monitored by the AV DD POR monitoring circuit for the analog section.

3.7 Analog Ground (A GND )

A GND is the ground connection to internal analog circuitry. To ensure accuracy and noise cancellation, this pin must be connected to the same ground as D GND , preferably with a star connection. If an analog ground plane is available, it is recommended to tie this pin to the plane of the PCB. This plane should also reference all other analog circuitry in the system. A GND is the biasing voltage for the substrate of the die and is not internally connected to D GND .

3.8 Exposed Pad (EP)

The pad is internally connected to A GND . It must be connected to the analog ground of the PCB for optimal accuracy and thermal performance. This pad can also be left floating if necessary.

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4.0 TERMINOLOGY AND FORMULAS

This section defines the terms and formulas used throughout this document. The following terms are defined: • MCLK – Master Clock • AMCLK – Analog Master Clock • DMCLK – Digital Master Clock • DRCLK – Data Rate Clock • OSR – Oversampling Ratio • Offset Error • Gain Error • Integral Nonlinearity Error (INL) • Signal-to-Noise Ratio (SNR) • Signal-to-Noise and Distortion Ratio (SINAD) • Total Harmonic Distortion (THD) • Spurious-Free Dynamic Range (SFDR) • MCP3465R Delta-Sigma Architecture • Power Supply Rejection Ratio (PSRR) • Common-Mode Rejection Ratio (CMRR) • Digital Pins Output Current Consumption PRE[1:0] CLK_SEL[1] OSR[3:0]

SCK Pad 0

OUT MCLK

1/PRESCALE AMCLK

1/4 DMCLK

1/OSR DRCLK 1

Internal Oscillator Multiplexer Clock Divider Clock Divider Clock Divider

AMCLKOUT

FIGURE 4-1: 4.1

System Clock Details.

MCLK – Master Clock

This is the master clock frequency used for clocking the Delta-Sigma ADC and the timer for the Scan mode. It can be externally generated (in which case, SCK is the input pin for this clock) or internally generated by the internal oscillator (in which case, it can also be clocked out on the SCK pin).

4.2 AMCLK – Analog Master Clock

This is the clock frequency that is present on the analog portion of the device after prescaling has occurred via the PRE[1:0] bits.

EQUATION 4-1: ANALOG MASTER CLOCK

MCLK AMCLK = ----------------------

Prescale

4.3 DMCLK – Digital Master Clock EQUATION 4-2: DIGITAL MASTER CLOCK

MCLK DMCLK = AMCLK -------------------- = --------------------------------

4 4  Prescale

4.4 DRCLK – Data Rate Clock

This is the output data rate in Continuous mode or the rate at which the ADC outputs new data. This data rate depends on the OSR and the prescaler as shown in Equation 4-3.

EQUATION 4-3: DATA RATE

AMCLK = -------------------------------------------------- MCLK DRCLK = DMCLK --------------------- = --------------------- -

OSR 4  OSR 4  OSR  Prescale Since this is the output data rate and since the decimation filter is a sinc (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate.

This is the clock frequency that is present on the digital portion of the device. This is also the sampling frequency or the rate at which the modulator outputs are refreshed. Each period of this clock corresponds to one sample and one modulator output. See Equation 4-2.

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4.5 OSR – Oversampling Ratio

The ratio of the sampling frequency to the output data rate. OSR = DMCLK/DRCLK in Continuous mode. See Table 5-6 for the OSR setting effect on sinc filter parameters.

4.6 Offset Error EQUATION 4-5:

SignalPower SINAD  dB  = 10 log 

 --------------------------------------------------------------------   Noise + HarmonicsPower The calculated combination of SNR and THD per the following formula also yields SINAD:

EQUATION 4-6:

This is the error induced by the ADC when the inputs are shorted together (V IN = 0V). This error varies based on gain settings, OSR settings and from chip-to-chip. It can easily be calibrated out by an MCU with a subtraction.

4.7 Gain Error

This is the error induced by the ADC on the slope of the transfer function. It is the deviation expressed in percentage compared to the ideal transfer function defined by Equation 5-5. The specification incorporates ADC gain error contributions, but not the V REF contribution. This error varies with gain and OSR settings. The gain error of this device has a low-temperature coefficient.

4.8 Integral Nonlinearity Error (INL)

Integral nonlinearity error is the maximum deviation of an ADC transition point from the corresponding point of an ideal transfer function, with the offset and gain errors removed, or with the end points equal to zero. It is the maximum remaining static error after offset and gain errors calibration for a DC input signal.

4.9 EQUATION 4-4: SIGNAL-TO-NOISE RATIO

SignalPower SNR  dB  = 10 log  --------------------------------- 

 NoisePower 

4.10 Signal-to-Noise and Distortion Ratio (SINAD) SINAD, THD AND SNR RELATIONSHIP

SINAD  dB  = 10 log 10

4.11

 SNR -----------   10  + 10  THD ------------  

10 

Total Harmonic Distortion (THD)

The THD is the ratio of the output harmonics power to the fundamental signal power for a sine wave input and is defined by Equation 4-7.

EQUATION 4-7:

HarmonicsPower THD  dB  = 10 log  ---------------------------------------------------- 

 FundamentalPower  The THD is usually measured only with respect to the first ten harmonics. THD is sometimes expressed in percentage (%). This formula converts the THD from dB to percentage:

EQUATION 4-8: THD  %  = 100  10 Signal-to-Noise Ratio (SNR)

For this device family, the Signal-to-Noise Ratio is a ratio of the output fundamental signal power to the noise power (not including the harmonics of the signal) when the input is a sine wave at a predetermined frequency; it is measured in dB. Usually, only the maximum Signal-to-Noise Ratio is specified. The SNR figure depends mainly on the OSR and gain settings of the device, as well as the temperature (due to thermal noise being dominant for high OSR).

SINAD EQUATION 4.12

THD  dB  ------------------------

20

Spurious-Free Dynamic Range (SFDR)

SFDR is the ratio between the output power of the fundamental and the highest spur in the frequency spectrum. The spur frequency is not necessarily a harmonic of the fundamental, even though that is usually the case. This figure represents the dynamic range of the ADC when a full-scale signal is used at the input. This specification depends mainly on the OSR and gain settings.

EQUATION 4-9:

FundamentalPower SFDR  dB  = 10 log 

 ----------------------------------------------------   HighestSpurPower Signal-to-Noise and Distortion Ratio is similar to Signal-to-Noise Ratio, with the exception that the user must include the harmonics power in the noise power calculation. The SINAD specification depends mainly on the OSR and gain settings.

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4.13 MCP3465R Delta-Sigma Architecture

A Delta-Sigma ADC is an oversampling converter that incorporates a built-in modulator, which digitizes the quantity of charge integrated by the modulator loop. The quantizer is the block that performs the Analog-to-Digital conversion. The quantizer is typically one bit or a simple comparator, which helps to maintain the linearity performance of the ADC (the DAC structure is in this case, inherently linear). Multibit quantizers help to lower the quantization error (the error fed back in the loop can be very large with 1-bit quantizers) without changing the order of the modulator or the OSR, which leads to better SNR figures. However, typically the linearity of such architectures is more difficult to achieve since the DAC is no more simple to realize and its linearity limits the THD of such ADC. The modulator five-level quantizer is a Flash ADC, composed of four comparators, arranged with equally spaced thresholds and a thermometer coding. The device also includes proprietary five-level DAC architecture that is inherently linear for improved THD figures.

4.14 Power Supply Rejection Ratio (PSRR)

This is the ratio between a change in the power supply voltage and the change in the ADC output codes. It measures the influence of the power supply voltage on the ADC outputs. PSRR is defined in Equation 4-10. The PSRR specification can be DC (the power supply is taking multiple DC values) or AC (the power supply is a sine wave at a certain frequency with a certain Common-mode). In AC, the amplitude of the sine wave represents the change in the power supply.

EQUATION 4-10:

 V OUT PSRR  dB  = 20 log 

 ------------------    AV DD

Where V OUT is the equivalent input voltage that the output code translates to with the ADC transfer function.

4.15 Common-Mode Rejection Ratio (CMRR)

This is the ratio between a change in the Common-mode input voltage and the change in the ADC output codes. It measures the influence of the Common-mode input voltage on the ADC outputs. The CMRR specification can be DC (the Common-mode input voltage takes multiple DC values) or AC (the Common-mode input voltage is a sine wave at a certain frequency with a certain Common-mode). In AC, the amplitude of the sine wave represents the change in the Common-mode input voltage. CMRR is defined in Equation 4-11.

EQUATION 4-11:

 V OUT CMRR  dB  = 20 log 

 -----------------------    V INCOM Where V INCOM = (V IN + + V IN -)/2 is the Common-mode input voltage and V OUT is the equivalent input voltage that the output code translates to with the ADC transfer function.

4.16 Digital Pins Output Current Consumption

The digital current consumption shown in the Electrical Characteristics table does not take into account the current consumption generated by the digital output pins and the charge of their capacitive loading. The specification is intended with all output pins left floating and no communication. In order to estimate the additional current consumption due to the output pins, see Equation 4-12. This equation specifies the amount of additional current due to each pin when its output is connected to a C load capacitance, with respect to D GND and submitted to an output signal toggling at an f out frequency. If a typical 10 MHz SPI frequency is used, with a 30 pF load and DV DD = 3.3V, the SDO output generates an additional maximum current consumption of 500 µA (the maximum toggling frequency of SDO is 5 MHz, since f SCK = 10 MHz and this is reached when the ADC output code is a succession of ‘1’s and ‘0’s). The C load value includes internal digital output driver capacitance, but this can generally be neglected with respect to the external loading capacitance.

EQUATION 4-12:

DIDD SPI = C load  DV DD  f Where:

out C load = Capacitance on the Output Pin DV DD = Digital Supply Voltage

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5.0 DEVICE OVERVIEW

5.1 Analog Input Multiplexer

Each of these multiplexers includes the same possibilities for the input selection, so that any required combination of input voltages can be converted by the ADC. The analog multiplexer is composed of parallel low-resistance input switches, turned on or off, depending on the input channel selection. Their resistance is negligible compared to the input impedance of the ADC (caused by the charge and discharge of the input sampling capacitors on the V IN +/V IN - ADC inputs). The block diagram of the analog multiplexer is shown in Figure 5-1.

The MCP3465R device includes a fully configurable analog input dual multiplexer that can select which input is connected to each of the two differential input pins (V IN +/V IN -) of the Delta-Sigma ADC. The dual multiplexer is divided into two single-ended multiplexers that are totally independent.

MUX[7:4] CH0 CH1 A GND AV DD AV DD REFIN+/OUT

REFIN- CS_SEL[1:0]

TEMP Diode P AV DD

I SOURCE AV DD

I TEMP+ I TEMPTEMP Diode M

V CM MUX[7:4]

= 1101 MUX[3:0] = 1101 MUX7:4] = 1110 MUX[3:0] = 1110 V IN + Analog Multiplexer V IN + A GND

MUX[3:0] V

IN - CH0 CS_SEL[1:0] CH1 A GND I SINK Sigma-Delta ADC AV DD

REFIN+/OUT A

GND REFIN-

TEMP Diode P TEMP Diode M

V CM V IN - Analog Multiplexer A GND

Analog Input Dual Multiplexer FIGURE 5-1: Simplified Analog Input Multiplexer Schematic.

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5.1.1 BURNOUT CURRENT SOURCES

FOR SENSOR OPEN/SHORT DETECTION The ADC inputs, V IN -/V IN +, feature a selectable burnout current source, which enables open or short-circuit detection, as well as biasing very low-current external sensors. The bias current is sourced on the V IN + pin of the ADC (noninverting output of the analog multiplexer) and sunk on the V IN - pin of the ADC (inverting output of the analog multiplexer). Since the same current flows at the V IN -/V IN + pins of the ADC, it can sense the impedance of an externally connected sensor that would be connected between the selected inputs of the multiplexer. When the sensor is in short circuit, the ADC converts signals that are close to 0V. When the sensor is an open circuit, the ADC converts signals that are close to the AV DD voltage. The current source is an independent peripheral of the ADC. It does not need the ADC to be in Conversion mode to be present. Once enabled, the source provides current even when the ADC is in Reset or ADC Shutdown mode. The current source can be configured at any time through programming the CS_SEL[1:0] bits in the CONFIG0 register (see Table 5-2). Since the amount of current selected can be very small, it may be necessary to diminish the MCLK master clock frequency to be able to reach the full desired accuracy during conversions (the settling time of the input structure, including the sensor, can be large if the sensor is very resistive, which will limit the bandwidth of the Sample-and-Hold input circuit).

TABLE 5-2: BURNOUT CURRENT SOURCE SETTINGS

SENSOR The device includes an on-board temperature sensor, which is made of two typical P-N junction diodes biased by fixed current sources (TEMP Diodes P and M). The TEMP Diode P has a current density of 4x of the TEMP Diode M. The difference in the current densities of the diodes yields a voltage that is a function of the absolute temperature. Once the ADC inputs (V IN -/V IN +) are connected to the temperature sensor diodes (MUX[7:0] = 0xDE), the ADC will see a V IN differential input that is the function of the temperature. The transfer function of the temperature sensor can be approximated by a linear equation or a third-order equation for more accuracy. When the internal temperature sensor is selected for the MUX or Scan input, the input sink/source current source, controlled by the CS_SEL[1:0] bits (see Section 5.1, Analog Input Multiplexer), is disabled internally (even though the CS_SEL[1:0] bits are not modified by the temperature sensor selection). In this case, the input current source is replaced by a specific internal current source that will only be sourced to the diode temperature sensor (see Figure 5-1). The bias current of the diodes is not calibrated internally, and can lead to a relatively large gain and offset error in the transfer function of the temperature sensor. Typical graphs showing the typical error in the temperature measurement are provided in Section 2.0, Typical Performance Curves (see Figure 2-51 for first-order and Figure 2-51 for third-order fitting). The accuracy can also be optimized by using proper digital gain and offset error calibration schemes.

The accuracy of the current sources is on the order of magnitude of ±20% and not very well controlled internally. However, the mismatch between sink and source is typically around ±1%. This relatively low accuracy on the current is generally sufficient for open/short-detection applications. Figure 2-53 shows how the ADC output code varies when the burnout current sources are enabled (with Gain = 1x) and the input sensor impedance is swept with a large dynamic range. This allows the use of the ADC as an open/short-detection circuit, which is practical when manufacturing complex remote sensor systems.

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EQUATION 5-1: TEMPERATURE SENSOR TRANSFER FUNCTION

First-order (linear) fitting: Gain = 1, MCLK = 4.9152 MHz, DATA_FORMAT[1:0] = 00

TEMP   C  = 4.0096  10  – 4   ADCDATA  LSb   V REF  V  – 269.13 Where V REF = V REF + – V REF -

5.1.3 ADC OFFSET CANCELLATION

ALGORITHM The input multiplexer and the ADC include an offset cancellation algorithm that cancels the offset contribution of the ADC. This offset cancellation algorithm is controlled by the AZ_MUX bit in the CONFIG2 register. When AZ_MUX = 0 (default), the offset cancellation algorithm is disabled and the conversions are not affected by this

EQUATION 5-2:

setting. When AZ_MUX = 1, the algorithm is enabled. When the offset cancellation algorithm is enabled, ADC takes two conversions, one with the differential input as V IN +/V IN -, one with V IN +/V IN - inverted. Equation 5-2 calculates the ADC output code. When AZ_MUX = 1, the Conversion Time, T CONV , is multiplied by two, compared to the default case where AZ_MUX = 0.

AZ_MUX CONVERSION RESULT

 ADC Output at + V IN  –  ADC Output at -V IN  - ADC Output Code (AZ_MUX = 1) = ------------------------------------------------------------------------------------------------------------------------ 2

This technique allows the cancellation of the ADC offset error and the achievement of ultra-low offset without any digital calibration. The resulting offset is the residue of the difference between the two conversions, which is on the order of magnitude of the noise floor. This offset is effectively canceled at every conversion, so the residual offset error temperature drift is extremely low.

DS20006414C-page 38 For One-Shot mode, the conversion time is simply multiplied by two. Enabling the AZ_MUX bit is not compatible with the Continuous Conversion mode (because it effectively multiplexes the inputs in between each conversion). If AZ_MUX = 1 and

mode), the device will reset the digital filter in between each conversion, and will therefore, have an output data rate of 1/(2 * T CONV ). The Continuous mode is replaced by a series of One-Shot mode conversions with no delay in between each conversion (see Section 5.14 “Conversion Modes” and Figure 5-5 for more details about the Conversion modes).

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5.2 Input Impedance for more details). The RC network usually uses small R

and large C to avoid additional offset due to IR drop in the signal path. This anti-aliasing filter will induce a small systematic gain error on the AC input signals that can be compensated in the digital section with the Digital Gain Error Calibration register (GAINCAL).

The ADC inputs (V IN +/V IN -) are directly tied to the analog multiplexer outputs and are not routed to external pins. The multiplexer input stage contribution to the input impedance is negligible. The conversion accuracy can be affected by the input signal source impedance when any external circuit is connected to the input pins. The source impedance adds to the internal impedance and directly affects the time required to charge the internal sampling capacitor. Therefore, a large input source impedance connected to the input pins can increase the system performance errors, such as offset, gain and Integral Nonlinearity (INL). Ideally, the input source impedance should be near zero. This can be achieved by using an operational amplifier with a closed-loop output impedance of tens of ohms.

5.3 ADC Programmable Gain

The gain of the converter is programmable and controlled by the GAIN[2:0] bits in the CONFIG2 register. The ADC programmable gain is divided into two gain stages: one in the analog domain, one in the digital domain, as per Table 5-3. After the multiplexer, the analog input signals are routed to the Delta-Sigma ADC inputs and are amplified by the analog gain stage (see Section 5.3.1 “Analog Gain” for more details). The digital gain stage is placed inside the digital decimation filter (see Section 5.3.2 “Digital Gain” for more details).

A proper anti-aliasing filter must be placed at the ADC inputs. This will attenuate the frequency contents around DMCLK and keep the desired accuracy over the baseband (DRCLK) of the converter. This anti-aliasing filter can be a simple first-order RC network with low time constant, which will provide a high rejection at the DMCLK frequency (see Figure 5-6

TABLE 5-3: DELTA-SIGMA ADC GAIN SETTINGS

GAIN[2:0] Total Gain (V/V) Analog Gain (V/V) Digital Gain (V/V) Total Gain (dB) V IN Range (V)

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5.3.1 ANALOG GAIN The gain settings, from 0.33x to 16x, are done in the analog domain. This analog gain is placed on each ADC differential input. Each doubling of the gain improves the thermal noise due to sampling by approximately 3 dB, which means the lowest noise configuration is obtained when using the highest analog gain. The SNR, however, is degraded, since doubling the gain factor reduces the maximum allowable input signal amplitude by approximately 6 dB. If the gain is set to 0.33x, the differential input range theoretically becomes ±3 * V REF . However, the device does not support input voltages outside of the power supply voltage range. If large reference voltages are used with this gain, the input voltage range will be clipped between A GND and AV DD ; therefore, the output code span will be limited. This gain is useful when the reference voltage is small and when the input signal voltage is large. The analog gain stage can be used to amplify very low signals, but the differential input range of the Delta-Sigma modulator must not be exceeded.

5.3.2 DIGITAL GAIN When the gain setting is chosen from 16x to 64x, the analog gain stays constant at 16x, and the additional gain is done in the digital domain by a simple shift and round of the output code. The digital gain range is between 1x and 4x. The output noise is approximately unchanged (except for the quantization noise, which is slightly decreased). The SNR is thus degraded by 6 dB per octave from 16x to 64x settings. This digital gain is useful for scaling up the signals without using the host device (MCU) operations, but they degrade the SNR and resolution (one bit per octave) and do not significantly improve the noise performance, except for very large OSR settings.

5.4

5.4.1

Delta-Sigma Modulator

ARCHITECTURE The Delta-Sigma ADC includes a second-order modulator with a multibit DAC architecture. Its 5-level quantizer is a Flash ADC composed of four comparators with equally spaced thresholds and a thermometer output coding. The proprietary 5-level architecture ensures minimum quantization noise at the outputs of the modulators without disturbing the linearity or inducing additional distortion.

Output Code ADCDATA V REF Code

Voltage (Decimal) Value 1111 +2 1111 +V REF 0111 +1 0111 +V REF /2 0011 0 0011 0 0001 -1 0001 -V REF /2 0000 -2 0000 -V REF Unlike most multibit DAC architectures, the 5-level DAC used in this architecture is inherently linear; therefore, it does not degrade the ADC linearity and THD performance. The sampling frequency is DMCLK; therefore, the modulator outputs are refreshed at a DMCLK rate. Figure 5-2 represents a simplified block diagram of the Delta-Sigma modulator.

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t D OMD AT t D OMD AT t D OMD AT t D OMD AT t D OMD AT AMCLK MDAT

A typical dependency of the bandwidth depending on the gain for each BOOST setting combination is shown from Figure 2-35 to Figure 2-38. Typically, a larger gain setting requires a higher BOOST setting in order to achieve the same bandwidth performance.

MDAT

MDAT (code = 0) Figure 2-43 shows the behavior of the achievable band-

width at BOOST[1:0] = 1x with AV DD corner cases. Since the BOOST settings vary, the internal slew rate of the modulator components, using a lower V REF value, will improve the bandwidth if low BOOST settings are used and show a bandwidth behavior that is too limited.

MDAT

5.5 MDAT

C OMP[3] C OMP[2] C OMP[1] C OMP[0] FIGURE 5-3: MDAT Serial Outputs Depending on the Modulator Output Code.

5.4.3 BOOST MODES The Delta-Sigma modulator includes a programmable biasing circuit in order to further adjust the power consumption to the sampling speed applied through the MCLK. This can be programmed through the BOOST[1:0] bits in the CONFIG2 register. The different BOOST settings are applied to the entire modulator circuit, including the voltage reference buffers. The settings of the BOOST[1:0] bits are described in Table 5-5.

TABLE 5-5:

The maximum achievable Analog Master Clock (AMCLK) speed, the maximum sampling frequency (DMCLK) and the maximum achievable data rate (DRCLK) are highly dependent on the BOOST[1:0] and GAIN[2:0] bits setting. A higher BOOST setting allows the circuit’s bandwidth to be increased and allows a higher analog master clock rate, which will then increase the baseband of the input signals to be converted. The digital gain (which is enabled at 32x and 64x gains) has no influence on the achievable bandwidth.

BOOST SETTINGS DESCRIPTION BOOST[1:0] Bias Current

00 x0.5 01 x0.66 10 x1 (default) 11 x2  2020-2021 Microchip Technology Inc.

Digital Decimation Filter

The decimation filter decimates the output bit stream of the modulator to produce 16-bit ADC output data. The decimation filter present in the device is a cascade of two filters: a third-order sinc filter with a decimation ratio of OSR 3 (third order moving an average of 3 x OSR 3 values), followed by a first-order sinc filter with a decimation ratio of OSR 1 , moving an average of OSR values (third order moving average of 3 x OSR 3 values). Figure 5-4 represents the decimation filter architecture.

OSR 1 = 1 Modulator Output (Thermometer

Coding)

SINC 3 SINC 1 OSR 3 OSR 1 4 Decimation

Filter Output

ADC Resolution Decimation Filter

FIGURE 5-4: Diagram.

Decimation Filter Block Equation 5-3 is the transfer function of the decimation filter:

EQUATION 5-3: FILTER TRANSFER

FUNCTION

DS20006414C-page 41

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The resolution (number of possible output codes expressed in powers of two or in bits) of the digital filter is a 16-bit maximum for any OSR = OSR 3 x OSR 1 and data format choice. The resolution only depends on the OSR through the OSR[3:0] bits setting in the CONFIG1 register per Table 5-6. Once the OSR is chosen, the resolution is fixed and the output code of the ADC is encoded with the data format defined by the DATA_FORMAT[1:0] bits setting in the CONFIG3 register.

In One-Shot mode, each conversion is launched individually, so the maximum data rate is effectively 1/T CONV if each conversion is launched with no delay. The digital filter is reset in between each conversion. However, due to the nature of the digital filter (which memorizes the sum of the incoming bit stream), the data rate at the filter output can be maximized if the filter is never reset. Because of the internal resampling of the digital filter, the output data rate can be equal to DMCLK/OSR = DRCLK; this is the case in Continuous mode. In this case, the first conversion still happens in the T CONV time, as this is the settling time of the filter. The subsequent conversions are pipelined and give their output at a data rate of DRCLK. The Continuous Conversion mode can optimize the data rate, while consuming the same power as One-Shot mode, which is advantageous in applications that require a continuous sampling of the analog inputs. The Continuous mode is not compatible with multiplexing the inputs (see Section 5.15 “Scan Mode” for more details about the Conversion mode settings in MUX and Scan modes).

The transfer function of this filter has a unity gain at each multiple of DMCLK. A proper anti-aliasing filter must be placed at the ADC inputs. This will attenuate the frequency contents around each multiple of DMCLK and keep the desired accuracy over the baseband of the converter. This anti-aliasing filter can be a simple first-order RC network with low time constant to provide a high rejection at DMCLK frequency. The conversion time is a function of the OSR settings and the DMCLK frequency.

EQUATION 5-4: CONVERSION TIME FOR

OSR = OSR 3 x OSR 1 Figure 5-5 shows the fundamental difference between One-Shot mode and Continuous mode in a simplified diagram. T CONV =   3  OSR 3  +  OSR 1 – 1   OSR 3   DMCLK Analog Input

Signal One-Shot mode Conversions are Serialized, Filter is Reset after Each Conversion

Group Delay: T CONV Data Rate: 1/(T CONV )

Conversion1 Conversion2 Conversion3 T CONV T CONV T CONV Conversion1 T CONV = Settling Time

Continuous mode Conversions are Pipelined,

Filter is Never Reset Group Delay: T CONV Data Rate: DRCLK 1/DRCLK 1/DRCLK Conversion2 T CONV Conversion3 T CONV

FIGURE 5-5:

DS20006414C-page 42 One-Shot Mode vs. Continuous Mode.

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Since the converter is effectively doing two conversions when the AZ_MUX bit is enabled, the conversion time is equal to 2 * T CONV in this mode. As described in Section 5.1.3 “ADC Offset Cancellation Algorithm”, this selection is not compatible with the Continuous Conversion mode; therefore, the output data rate is equal to 1/(2 * T CONV ) in this mode. Table 5-6 summarizes the possible filter settings and their associated Conversion Time, T CONV , as well as their output data rate (DRCLK) in Continuous mode.

filter notches with a multiple of 50/60 Hz depending on the OSR setting. The rejection band strongly depends on the master clock accuracy and corresponds to a first-order decimation filter rejection rate. The high OSR settings can be used for applications requiring very low noise and slow data rates. Figure 5-6 shows the frequency response of the decimation filter with default settings. Figure 5-7 represents the frequency response of the filter with the highest OSR settings and a line rejection at 60 Hz. When OSR is larger than 20480 for typical master clock frequency, MCLK = 4.9152 MHz, the device includes an additional 50/60 Hz rejection by aligning decimation

TABLE 5-6: OVERSAMPLING RATIO AND SINC FILTER RELATIONSHIP ADC Resolution

in Bits (No Missing

Codes)

Conversion

Time (T CONV )

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5.6 ADC Output Data Format

The ADC Output Data (ADCDATA) register is located at address: 0x0. The default length of the register is 16-bit (15-bit + sign). Output data are calculated in the digital decimation filter with a much larger resolution and rounded to the closest LSb value.

EQUATION 5-5:

The rounding ensures a maximum 1/2 LSb error instead of a simple truncation that ensures a 1 LSb maximum error. Equation 5-5 calculates the ADC output code as a function of the input and reference signals for DC inputs.

ADC OUTPUT CODE FOR DC INPUT (DATA_FORMAT[1:0] = 00)

For AC sine wave inputs, the decimation filter transfer function (see Equation 5-3) induces an additional gain on the ADC output code, which depends on the input frequency (roll-off of the decimation filter). For any inputs, the V IN +/V IN - voltages are averaged out during the whole conversion time as the ADC is an oversampling converter.

ADC output format is set by the DATA_FORMAT[1:0] bits in the CONFIG3 register. These bits define four different possible formats for the ADC Data Output register: three 32-bit formats and one 16-bit format for the MCP3465R. Figure 5-8 describes all possible data formats.

DATA_FORMAT[1:0] 00 SGN + DATA[14:0] 01 SGN + DATA[14:0] 0x0000 10 SGN ext (16-bit) DATA[15:0] 11 FIGURE 5-8:

CH_ID[3:0] SGN ext (12-bit) DATA[15:0] ADC Output Format Selection.

When DATA_FORMAT[1:0] = 0x, the ADC data are represented on 16 bits (15-bit plus sign). The ADC output code is represented with MSb first signed two’s complement coding. With these two data formats, the coding does not allow overrange; the equivalent analog input range is [-V REF ; +V REF – 1 LSb]. When V IN * Gain > V REF – 1 LSb, the 16-bit ADC code (SGN + DATA[22:0]) will saturate and be locked at 0x7FFF. When V IN * Gain < -V REF , the 16-bit ADC code will saturate and be locked at 0x8000. Using these data formats does not permit correctly evaluating full-scale errors in case of a positive full-scale error.

 2020-2021 Microchip Technology Inc.

When DATA_FORMAT[1:0] = 00, the output register shows only the 16-bit value. When DATA_FORMAT[1:0] = 01, the output register is 32 bits long and the output code is padded with additional zeros on the last byte. The output code is left justified in this case. This format is useful for 32-bit MCU applications.

DS20006414C-page 45

MCP3465R

When DATA_FORMAT[1:0] = 1x, the ADC data are represented on 17 bits. For these two data formats, the output register is 32 bits long. With these two data formats, the coding allows overrange; the equivalent analog input range is [-2 x V REF , +2 x V REF – 1 LSb]. When V IN * Gain > 2V REF – 1 LSb, the 17-bit ADC code (SGN + DATA[15:0]) will saturate and be locked at 0x0FFFF. When V IN * Gain < -2V REF , the 16-bit ADC code will saturate and be locked at 0x10000. Using these data formats allows a correct evaluation of the full-scale errors in case of a positive full-scale error, since they allow inputs that can be greater than V REF or less than -V REF . The ADC accuracy is not maintained on the full extended [-2 x V REF , +2 x V REF – 1 LSb] range, but only on a smaller range, which is approximately equal to ±1.05 x V REF . This overrange can be useful in high-side measurements and gain error cancellation algorithms. The overrange-capable formatting on 17 bits is fully compatible with the standard code locked formatting on 16 bits; both coding formats will produce the same TABLE 5-7:

16-bit codes for the [-V REF ; +V REF – 1 LSb] range and the MSb on the 17-bit coding can be considered as a simple Sign bit extension. When DATA_FORMAT[1:0] = 10, the 17-bit (16-bit + SGN) value is right justified. The first byte of the 32-bit ADC output code will repeat the Sign bit (SGN). In DATA_FORMAT[1:0] = 11, the output code is similar to the one in DATA_FORMAT[1:0] = 10. The only difference resides in the four MSbs of the first byte, which are no longer repeats of the Sign bit (SGN). They are the Channel ID data (CH_ID[3:0]) that are defined in Table 5-15. This CH_ID[3:0] word can be used to verify that the right channel has been converted to Scan mode and can serve easy data retrieval and logging (see Section 5.15 “Scan Mode” for more details about the Scan mode). In MUX mode, this 4-bit word is defaulted to ‘0000’ and does not vary with the MUX[7:0] selection. This format is useful for 32-bit MCU applications.

Equivalent Input Voltage ADC Output Code (SGN + DATA[14:0]) Hexadecimal Decimal

V REF – 1 LSb 0111111111111111 0x7FFF +32767 V REF – 2 LSb 0111111111111110 0x7FFE +32766

1 LSb 0000000000000001 0x0001 +1

0 0000000000000000 0x0000 0 -1 LSb 1111111111111111 0xFFFF -1 -V REF + 1 LSb 1000000000000001 0xFFFF -32767

< -V REF 1000000000000000 0x8000 -32768 Hexadecimal Decimal

Equivalent Input Voltage ADC Output Code (SGN + DATA[15:0])

2 V REF – 1 LSb 01111111111111111 0x0FFFF +65535 2 V REF – 2 LSb 01111111111111110 0x0FFFE +65534 V REF + 1 LSb 01000000000000001 0x08001 +32769

V REF 01000000000000000 0x08000 +32768 V REF – 1 LSb 00111111111111111 0x07FFF +32767 V REF – 2 LSb 00111111111111110 0x07FFE +32766

1 LSb 00000000000000001 0x00001 +1

0 00000000000000000 0x00000 0 -1 LSb 11111111111111111 0x1FFFF -1 -V REF + 1 LSb 11000000000000001 0x18001 -32767

-V REF 11000000000000000 0x18000 -32768 -V REF – 1 LSb 10111111111111111 0x17FFF -32769 -2 V REF + 1 LSb 10000000000000001 0x10001 -65535

< -2 V REF 10000000000000000 0x10000 -65536 DS20006414C-page 46  2020-2021 Microchip Technology Inc.

MCP3465R

5.7 Internal/External Voltage Reference

5.7.1 VOLTAGE REFERENCE

SELECTION The voltage reference selection for the ADC is controlled by the VREF_SEL bit in the CONFIG0 register, as shown in Table 5-9.

TABLE 5-9:

The REFIN- pin is set as an input, directly connected to the V REF - input of the ADC. For a better noise immunity, it is recommended to connect this pin to A GND externally when a single-ended voltage reference is used. Figure 6-10 shows more details of the reference selection and reference pins connections.

ADC VOLTAGE REFERENCE SELECTION VREF_SEL Description 0 1 Reference Input/Output Pins

REFIN- Pin REFIN+/OUT Pin External reference selected. Internal reference buffer is shut down. Internal reference is only generating the internal 1.2V Common-mode voltage for the ADC.

V REF - Input V REF + Input Internal reference selected with 2.4V buffered output.

V REF - Input (should be tied to A GND )

Internal reference with 2.4V

buffered output REFINPAD ADC V REF -

Input REFIN+/OUT

PAD ADC V REF +

Input

–

2x

• V REF Buffer –

1x ADC Internal V

CM Voltage +

Internal + Band Gap Voltage – FIGURE 5-9:

1.2V V CM Buffer Voltage Reference Selection Schematic.

 2020-2021 Microchip Technology Inc. DS20006414C-page 47

MCP3465R

When VREF_SEL = 0, the reference voltage is set to External mode. The REFIN+/OUT pin becomes an input. In this case, the REFIN+/OUT pad is directly tied to the V REF + input of the ADC. There is no input buffer in the differential input voltage reference path in this mode, so the external voltage reference should include a buffer to be able to charge the internal voltage reference sampling capacitors. When VREF_SEL = 1, the REFIN+/OUT is internally buffered to produce a 2.4V buffered reference voltage at the V REF + input of the ADC. Section 5.7.2 “Internal Voltage Reference Buffer” details the architecture of the voltage reference buffer. In this mode, the REFIN+/OUT pin becomes an output and the reference voltage is generated internally. The structure of the internal voltage reference is based on a band gap voltage reference source, giving a 1.2V output directly connected to a low noise chopper buffer, configured with a gain of 2x, to give a 2.4V output on the REFIN+/OUT pad. The internal reference has a very low typical temperature coefficient of 15 ppm/°C for extended temperature range and 9 ppm/°C for industrial temperature range, allowing the ADC output codes to have the least variation corresponding to the temperature ranges, since they are proportional to (1/V REF ).

5.7.2 INTERNAL VOLTAGE REFERENCE

BUFFER When VREF_SEL = 1, the voltage reference buffer is enabled. It is only powered on when the ADC state is in Reset or in Conversion mode and is powered off in Shutdown mode. The buffer is designed to be able to drive the ADC reference input that is sampling the reference voltage. The REFIN- pin is not buffered and is connected directly to the ADC inverting voltage reference input (V REF -). The offset induced by the buffer may slightly vary between the two possible gain selections, as well as its temperature dependency and bandwidth; therefore, it has to be characterized separately. The buffer injects a certain quantity of 1/f noise into the system that can be modulated with the incoming input signals and can limit the SNR performance at higher OSR values (OSR > 256). To overcome this limitation, the buffer includes an auto-zeroing algorithm that greatly reduces (cancels out) the 1/f noise and cancels the offset value of the reference buffer. As a result, the SNR of the system is not affected by this 1/f noise component of the reference buffer, even at maximum OSR values. This autozeroing algorithm is performed synchronously with the DMCLK and can be enabled or disabled with the AZ_VREF bit setting in the CONFIG2 register. When AZ_VREF = 1 (default), the auto-zeroing is enabled, which cancels out the 1/f noise and improves the SNR, while not impacting the THD performance. This mode is recommended for higher OSR values (OSR > 256). When AZ_VREF = 0, the reference auto-zeroing algorithm is disabled. This setting should be reserved for lower OSR values, where higher ADC speed is more important than accuracy. If the application is susceptible to high-frequency noise, using AZ_VREF = 0 or a proper low-pass filter at the V REF output pin (to filter out the chopper frequency components from the buffered output) is recommended.

DS20006414C-page 48  2020-2021 Microchip Technology Inc.

MCP3465R

5.8 Power-on Reset the two POR monitoring circuits are crossed.

Figure 5-10 illustrates the power-up and power-down sequences. The analog and digital power supplies are monitored separately by two Power-on Reset (POR) monitoring circuits at all times, except during Full Shutdown mode (see Section 5.10 “Low-Power Shutdown Modes”).

If the CS pin is kept logic low during a POR state, a logic high pulse is necessary to start the first communication sequence after power-up. The CS rising edge will reset the SPI interface properly. Each POR circuit has two separate thresholds, one for the rising voltage supply and one for the falling voltage supply. They both include hysteresis (the rising threshold is superior), so that the device is tolerant to a certain degree of transient noise on each power supply.

The DV DD and AV DD monitoring thresholds are different since their respective voltage ranges are different. The AV DD rising threshold is approximately 1.75V, ±10% and the DV DD is 1.2V, ±10%. The hysteresis is approximately 150 mV (typical). If any of the two power supply voltages is below its respective threshold, the POR state is forced internally. In this state, the SPI interface is disabled, no command can be executed by the chip; all registers are cleared and set to their default values.

Proper decoupling ceramic capacitors (0.1 µF and 10 µF ceramic) should be placed as close as possible to the power supply pins (AV DD , DV DD ) to provide additional transient immunity. At power-up, when both power supply voltages are above the rising thresholds, the device powers up, and the SPI interface is enabled and can handle communications. Since both thresholds need to be crossed for the power-up, the power-up sequence is not important and any power supply voltage can ramp up first. The detection time for the monitoring circuits (t POR ) is about 1 µs for relatively fast power-up ramp rates. The normal operation stops when any of the falling thresholds of During Full Shutdown mode, the power supply voltages are not monitored to be able to reach ultra-low power consumption. The device cannot generate a POR event interrupt in this mode, except for cases of extremely low-power supply voltages. See Section 5.10.1 “Full Shutdown Mode”. In order to ensure a proper power-up sequence, the ramp rate of DV DD must not exceed 3 V/µs when coming out of the POR state.

Voltage (AV DD , DV DD )

POR Threshold Up POR Threshold Down t POR

Time POR State FIGURE 5-10:

Normal Operation POR State Power-on Reset Timing Diagram.

 2020-2021 Microchip Technology Inc. DS20006414C-page 49

MCP3465R

5.9 ADC Operating Modes

The ADC can be placed into three different operating modes: ADC Shutdown, Standby and Conversion. The ADC operating mode is controlled by the user through the ADC_MODE[1:0] bits in the CONFIG0 register. The user can directly launch conversions or place the ADC into ADC Shutdown or Standby mode by writing these bits. Additional Fast commands are available for each of the three possible states of these bits to allow faster programming in case of time-sensitive applications (see Section 6.2.4 “Command-Type Bits (CMD[1:0])”). Table 5-10 describes the available ADC_MODE[1:0] bits setting. The ADC_MODE[1:0] bits do not give an instantaneous representation of the ADC state. Writing the ADC_MODE[1:0] bits sets the desired state of the ADC, but this state is only attained after a start-up time depending on the current state of the ADC (see Section 5.11 “ADC Start-up Timer” for details about the start-up timer). Typically, the device starts in ADC Shutdown mode after a POR (ADC_MODE[1:0] = 00 by default). To launch conversions in the desired configuration, the user should program the part in the desired configuration and then set the ADC_MODE[1:0] bits to ‘11’. In this case, the first conversion will start after T ADC_SETUP = 256 DMCLK periods. This time is necessary for the part to adjust to the new programmed settings and settle in to its operating point to accurately convert the input signals. Internally, the device tracks the current state of the ADC, as well as the start-up timer counter, to be able to optimize the start-up time depending on the desired transitions and internal configurations required, and set by the user.

TABLE 5-10:

In MUX mode, overwriting the ADC_MODE[1:0] bits to ‘11’ when the ADC is already in conversion resets and restarts the current conversion immediately. In Scan mode (see Section 5.15 “Scan Mode”), writing the ADC_MODE[1:0] bits to ‘11’ starts the conversion Scan cycle. During the complete cycle, even when the Scan timer is enabled, reading the ADC_MODE[1:0] bits gives a ‘11’ code output, meaning that the Scan cycle is ongoing. Rewriting ADC_MODE[1:0] = 11 during Scan mode will immediately reset and restart the entire Scan sequence from the beginning of the sequence. The restart of the Scan sequence may induce a T ADC_SETUP additional delay if the ADC is in ADC Shutdown mode when the ADC_MODE bits are overwritten (this can happen if the ADC_MODE bits are overwritten during the timer delay period, where the ADC is placed into ADC Shutdown mode in between two Scan cycles). The ADCDATA register is always updated with the last conversion results. The ADCDATA register cannot provide incomplete conversion results. The A/D conversion must be completed to be able to provide a result in the ADCDATA register. Each end of conversion generates a data ready interrupt on both IRQ mechanisms (see Section 6.8.1 “Conversion Data Ready (DR) Interrupt”). The ADCDATA register is never cleared when the device transitions from one mode to another. The only way to clear the ADCDATA register is a POR event or a Full Reset Fast command (see Section 6.2.5 “Fast Commands Description”).

Note: Since there is no IRQ pin, the IRQ

mechanisms are the STATUS byte and IRQ register bits.

ADC OPERATING MODES DESCRIPTION ADC_MODE[1:0] ADC Mode Description

11 Conversion The ADC is placed into Conversion mode and consumes the specified

current. A/D conversions can be reset and restarted immediately once this mode is effectively reached. This mode may be reached after a maximum of T ADC_SETUP time, depending on the current state of the ADC. 10 Standby Conversions are stopped. ADC is placed into Reset but consumes almost

as much current as in Conversion mode. A/D conversions can start immediately once this mode is effectively reached. This mode may be reached after a maximum of T ADC_SETUP time, depending on the current state of the ADC. 0x ADC Shutdown Conversions are stopped. ADC is placed into ADC Shutdown mode and

does not consume any current. A/D conversions can only start after T ADC_SETUP start-up time. This mode is effective immediately after being programmed.

DS20006414C-page 50  2020-2021 Microchip Technology Inc.

MCP3465R

5.10 Low-Power Shutdown Modes

The device incorporates two low-power modes that can be activated in order to limit power consumption of the device when ADC is not used. These two modes are called Partial Shutdown and Full Shutdown modes.

5.10.1 FULL SHUTDOWN MODE The Full Shutdown mode can only be enabled by sending a Fast Command Full Shutdown (Fast Command code: ‘1101’). Note that the execution of this Fast command forces the CONFIG0 to be set to 0x00 (no active block is enabled). Full Shutdown mode is the lowest power mode of the device. None of the circuits consuming static power are active in this mode. As stated in Section 5.8 “Power-on Reset”, the AV DD /DV DD POR monitoring circuits are not active while in Full Shutdown mode.

Note: If the digital power supply resides for a long

time period below the POR threshold and to a sufficiently low voltage (typically below 0.6V), some bits previously set to ‘1’ can toggle to ‘0’ and not be set properly. In order to ensure a safe operation after the Full Shutdown mode, follow the sequence of commands: - Write LOCK register to 0xA5 - Write IRQ register to 0x07 - Send a Fast CMD Full Reset (‘1110’) - Reconfigure the chip as desired This sequence ensures a recovery with the desired settings in any loss of power scenario.

TABLE 5-11:

The part can still be accessed through the SPI interface during this mode and will accept incoming SPI commands. The ADCDATA register is not cleared during Full Shutdown mode and still holds previous conversion results. The other register settings are not modified or reset due to entering Full Shutdown mode. The Full Shutdown mode stops all internal timers and resets them. Sending a Fast CMD to change the operating mode exits the Full Shutdown mode. The user should place all digital inputs to a static value (logic low or high) in order to optimize power consumption during Full Shutdown mode. The current consumption specifications during Full Shutdown mode are intended without any digital pin toggling during the measurement. In this case, only leakage current is consumed throughout the device and this current varies exponentially with respect to absolute temperature.

5.10.2 PARTIAL SHUTDOWN MODE Partial Shutdown mode is achieved when CONFIG0 is set to ‘0000000x’. In this mode, most of the internal circuits are shut down, with the exception of the POR monitoring and internal biasing circuits. During the Partial Shutdown mode, the power supply is continuously monitored, whereas in Full Shutdown mode, the POR monitoring circuits are powered down. The power consumption is also much higher in Partial Shutdown mode due to the POR monitoring circuits being active. Partial Shutdown mode allows the device to be restarted and put back in Conversion mode faster than Full Shutdown mode. Table 5-11 describes the differences between Partial and Full Shutdown modes. If the current consumption of Partial Shutdown mode is acceptable for the application, it is recommended that it is used as an alternative to Full Shutdown mode, where the POR monitoring circuits are shut down and no longer monitoring the AV DD and DV DD power supplies. LOW-POWER MODES (1) Device VREF_SEL CONFIG0[6] CLK_SEL[1:0] CS_SEL[1:0] ADC_MODE[1:0] Low-Power Mode Description

Partial Shutdown 0 0 00 00 0x All peripherals, except the POR

monitoring circuits and clock biasing circuits, are shut down and consume no static current. The SPI interface remains active in this mode and consumes no current while the bus is Idle. Full Shutdown 0 0 00 00 00 All analog and digital circuits are

shut down and consume no static current. The SPI interface remains active in this mode and consumes no current while the bus is Idle. Note 1: x = Do not care  2020-2021 Microchip Technology Inc. DS20006414C-page 51

MCP3465R

5.11 ADC Start-up Timer

The device includes an intelligent start-up timer circuit for the ADC, which ensures that the ADC is properly biased and that internal nodes are properly settled before each conversion. This timer ensures the proper conditions for the ADC to convert with its full accuracy for each conversion. The ADC can operate in three different modes: ADC Shutdown, Standby and Conversion, as described in Section 5.9 “ADC Operating Modes”. The ADC start-up timer manages the time for the transitions between each mode. These transitions can be instantaneous or can take a maximum of 256 DMCLK periods, depending on the type of transition and the current status of the ADC and of the internal start-up timer. The timer will always try to reduce the transition time, from one state to another, but will also allow enough time for the internal circuitry to settle to the proper internal operating points. The transitions from Standby or Conversion mode to ADC Shutdown mode are always immediate. They reset the internal start-up timer to 256 DMCLK periods (T ADC_SETUP ). The transitions from ADC Shutdown to Standby or Conversion mode start the internal start-up timer that decrements from 256 to 0. The timer only decrements after a small delay of two MCLK periods in case of a transition caused by an SPI command. This small delay is necessary to overcome any possible synchronization issue between the two asynchronous clocks: MCLK and SCK. The timer will immediately decrement (without the synchronization delay) if the transitions are generated by the internal state machine (for example, when the transitions are generated by the Scan sequence). Once the timer reaches 0 (when the user has clocked 256 DMCLK periods), the device reaches its internal proper operating points and will either stay in Standby mode (if ADC_MODE[1:0] = 10) or start the Conversion mode (if ADC_MODE[1:0] = 11). The transition from Standby to Conversion mode and vice versa is immediate once the timer has reached 0 (if ADC_MODE[1:0] = 11). If the transition from Standby to TABLE 5-12:

Conversion mode occurs, and if the timer has not yet reached 0, the timer will continue to decrement to 0 before effectively starting the conversion. The timer cannot decrement faster than 256 DMCLK periods when the ADC transitions from ADC Shutdown mode to Conversion mode (from ADC Shutdown mode, the ADC is allowed 256 DMCLK periods to power-up and settle to its desired operating point before starting conversions). The start-up time has been sized at 256 DMCLK clock periods for the part to be able to settle in all conditions and with all possible clock frequencies as specified. Table 5-12 summarizes the behavior of the internal start-up timer as a function of the ADC_MODE[1:0] bits setting. Rewriting the ADC_MODE[1:0] bits without changing the bit settings does not modify the internal timer and cannot shorten the start-up delay necessary to start accurate conversions. A synchronization delay of two MCLK periods occurs after each rewrite if

In Scan mode, when CONV_MODE[1:0] = 11 (Continuous mode), the ADC may be placed in ADC Shutdown mode and restarted in between each Scan cycle depending on the TIMER[15:0] bits setting (see Section 5.15.5 “Delay Between Scan Cycles (TIMER[15:0])”). If the TIMER register is programmed with a decimal code greater than T ADC_SETUP = 256, the internal timer will automatically place the part in ADC Shutdown mode at the end of the cycle and will start to transition to the next cycle 256 DMCLK periods before the end of the timer delay. This lowers the power consumed during the timer delay as much as possible. If the value of the timer delay is less than 256 DMCLK periods, the part will not enter ADC Shutdown mode and will stay in Standby during the timer delay (in this case, the power consumed is equivalent to the Conversion mode power consumption). Figure 5-11 shows different cases of transitions between modes and shows the internal state of the start-up timer for each step.

 2020-2021 Microchip Technology Inc.

MCP3465R

DMCLK Continuous Clocking SPI Wri te Wri te Wri te AD C _M ODE =

1x AD C _M ODE = 0x AD C _M ODE = 1x 0x 1x 0x 1x Timer Reset Timer

Countdown Timer Reset Switching Between ADC_MODE = 10 and 11

has no Effect on the Timer ADC_MODE ADC Start-up Timer Decimal

Code Wri te

1X AD C _M ODE = 1x 256 ADC Ready to Convert 0

FIGURE 5-11:

5.12

ADC Start-up Timer Timing Diagram.

Master Clock Selection/Internal Oscillator

The device includes three possible clock modes for the master clock generation. The Master Clock (MCLK) is used by the ADC to perform conversions and is also used by the digital portion to generate the different digital timers. The clock mode selection is made through the CLK_SEL[1:0] bits located in the CONFIG0 register. The possible selections are described in Table 5-13. The master clock is not propagated in the chip when the chip enters the Full Shutdown mode (see Section 5.10 “Low-Power Shutdown Modes”). MCP3465R is a low pin count device, targeted to applications requiring a smaller PCB footprint, so there is no dedicated pin for the MCLK input/output on this device. The SCK pin is used for this function, on top of being used as the clock input for the digital interface. SCK is always the clock input for the digital interface at all times. Any change to the CLK_SEL bits is following a specific sequence described in Section 6.9 “Master Clock Input/Output Modes”. Each Reset and restart resets all internal phases to their default values and can lead to a possible temporary duty cycle change at the clock output pin.

TABLE 5-13: CLOCK SELECTION BITS CLK_SEL[1:0] Clock Mode SCK Pin

00 or 01 External clock MCLK digital input

10 Internal RC

Oscillator, no clock output High-Z MCLK and SCK are asynchronous 11 AMCLK is present as Internal RC

Oscillator with clock an output on the SCK pin output  2020-2021 Microchip Technology Inc.

5.12.1 EXTERNAL MASTER CLOCK MODE

The External Clock mode is used to input the MCLK clock necessary for the ADC conversions and can accept duty cycles with a large range, since the clock is redivided internally to generate the different internal phases. The external clock can be provided on the SCK pin. Therefore, the SCK pin in this mode has a dual functionality, as it is also the clock input pin for the digital interface. In this mode, SCK = MCLK at all times and the digital interface is synchronous with the master clock. When running conversions, SCK has to be continuously clocking at a constant frequency as it is defined for the MCLK input to ensure proper ADC accuracy. In this case, communications using the SPI interface should be synchronized on this free-running clock and can be framed with a proper usage of the CS pin.

5.12.2 INTERNAL OSCILLATOR The device includes an internal RC-type oscillator powered by the digital power supply (DV DD /D GND ). The frequency of this internal oscillator ranges from 3.3 MHz to 6.6 MHz. The oscillator is not trimmed in production; therefore, the precision of the center frequency is approximately ±30% from chip to chip. The duty cycle of the internal oscillator is centered around 50% and varies very slightly from chip to chip. The internal oscillator has no Reset feature and keeps running once selected.

DS20006414C-page 53

MCP3465R

5.12.3 INTERNAL MASTER CLOCK

When CLK_SEL[1] = 1, the internal oscillator is selected and the master clock is generated internally. The master clock generation is independent of the ADC as the clock can still be generated, even if the ADC is in ADC Shutdown mode. The internal oscillator is only disabled when CLK_SEL[1:0] = 0x. The clock can be distributed to the SCK pin depending on the CLK_SEL[0] bit. When the clock output is selected (CLK_SEL[0] = 1), the AMCLK clock derived from the MCLK (AMCLK = MCLK/PRESCALE) is available on the SCK pin. The AMCLK output can serve as the clock pin to synchronize other MCP3465R devices that are configured with CLK_SEL[1:0] = 00 or 01. The AMCLK output is available on the SCK pin as soon as the Write command (CLK_SEL[1:0] = 11) is finished. Section 6.9 “Master Clock Input/Output Modes” describes in detail the transitions from one clock mode to another.

5.13 Digital System Offset and Gain Calibrations

The MCP3465R device includes a digital calibration feature for offset and gain errors. The calibration scheme for offset error consists of the addition of a fixed offset value to the ADC output code (ADCDATA at address: 0x0). The offset value added (OFFSETCAL) is determined in the OFFSETCAL register (address: 0x9). The calibration scheme for gain error consists of the multiplication of a fixed gain value to the ADCDATA code. The gain value (GAINCAL) multiplied is determined in the GAINCAL register (address: 0xA). The digital offset and gain calibration schemes are enabled or disabled via the EN_OFFCAL and EN_GAINCAL control bits of the CONFIG3 register. When both calibration control bits are enabled (EN_OFFCAL = EN_GAINCAL = 1), the ADCDATA register is modified with the digital offset and gain calibration schemes, as described in Equation 5-6. When a calibration enable bit is off, its corresponding register becomes a Don’t Care register and the corresponding calibration is not performed.

EQUATION 5-6: ADCDATA OUTPUT

AFTER DIGITAL GAIN AND OFFSET ERROR CALIBRATION

[ADCDATA (pre-calibration) + OFFSETCAL] x GAINCAL DS20006414C-page 54 The calculations are performed internally with proper management of overloading, so that the overload detection is done on the output result only and not on the intermediate results. A sufficient number of additional overload bits is maintained and propagated internally to overcome all possible overload and/or overload recovery situations. For example, if ADCDATA (pre-calibration) + OFFSETCAL is out of bounds, but (ADCDATA (pre-calibration) + OFFSETCAL) x GAINCAL is still in the right range (possible with 0 < GAINCAL < 1), the result is not saturated.

5.13.1 DIGITAL OFFSET ERROR

CALIBRATION The Offset Calibration register (OFFSETCAL, address: 0x9) is a signed MSb first, two’s complement coding, 16-bit register that holds the digital offset calibration value, OFFSETCAL. The OFFSETCAL equivalent input voltage value is calculated with Equation 5-7.

EQUATION 5-7: OFFSETCAL

CALIBRATION VALUE (EQUIVALENT INPUT VOLTAGE) OFFSETCAL (V) = V REF x (OFFSETCAL[23:8] signed decimal code)/(32768 x GAIN)

For the MCP3465R device, the offset calibration is done by adding the OFFSETCAL[23:8] calibration value to the ADCDATA output code, bit by bit. The last byte of the OFFSETCAL register (OFFSETCAL[7:0]) is ignored and internally reset to 0x00 during the calibration; therefore, the addition just takes into account the OFFSETCAL[23:8] bits and is done bit by bit with the ADC output code. The offset calibration value range in equivalent voltage is [-V REF /Gain; (+V REF – 1 LSb)/Gain], which can cancel any possible offset in the ADC but also in the system. The offset calibration is realized with a simple 16-bit signed adder and is instantaneous (no pipeline delay). Enabling the offset calibration will affect the next conversion result; the conversion result already held in the ADCDATA register (0x0) is not modified when the EN_OFFCAL is set to ‘1’, but the next one will take the offset calibration into account. Changing the OFFSETCAL register to a new value will not affect the current ADCDATA value, but the next one (after a data ready interrupt) will take the new OFFSETCAL value into account. Figure 5-12 presents the different cases and their impact on the ADCDATA register and the Data Ready Event.

 2020-2021 Microchip Technology Inc.

MCP3465R

SPI ADC STATUS

Write EN_OFFCAL = 1

Data 1 Conversion Data 2 Conversion Data 3 Conversion Data 4 Conversion DATA0 DATA1 DATA2 + OFFSETCAL1 DATA3 + OFFSETCAL2 Data Ready Event ADCDATA REGISTER VALUE FIGURE 5-12:

5.13.2 ADC Output and Data Ready Event Behavior with Digital Offset Calibration Enabled.

DIGITAL GAIN ERROR CALIBRATION The Gain Error Calibration register (GAINCAL, address: 0xA) is an unsigned 16-bit register that holds the digital gain error calibration value, GAINCAL. Equation 5-8 calculates the GAINCAL multiplier.

EQUATION 5-8: GAINCAL CALIBRATION

VALUE (MULTIPLIER VALUE) GAINCAL (V/V) = (GAINCAL[23:8] unsigned decimal code)/32768 For the MCP3465R device, the gain error calibration is done by multiplying the GAINCAL value to the ADC output code. The last byte of the GAINCAL register (GAINCAL[7:0]) is ignored and internally reset to 0x00 during the calibration; therefore, the multiplication just takes into account the GAINCAL[23:8] bits. The gain error calibration value range in equivalent voltage is [0; 2-2 -15 ], which can cancel any possible gain error in the ADC and in the system. The gain SPI ADC STATUS

Data 1 Conversion Write EN_GAINCAL = 1 error calibration is made with a simple 16-bit add-and-shift circuit clocked on DMCLK, and induces a pipeline delay of T GCAL = 15 DMCLK periods. This pipeline delay acts as a delay on the data ready interrupt position that is shifted by T GCAL = 15 DMCLK periods. During this delay, the converter can process the next conversion, the delay does not shift the next conversion and does not change the Conversion Time, T CONV . Enabling the gain error calibration will affect the next conversion result; the conversion result already held in the ADCDATA register (0x0) is not modified when the EN_GAINCAL is set to ‘1’, but the next one will take the offset calibration into account. Changing the GAINCAL register to a new value will not affect the current ADCDATA value, but the next one (after a data ready interrupt) will take the new GAINCAL value into account. Figure 5-13 shows the different cases, and their associated effects on the ADCDATA register and the Data Ready Event.

Data 2 Conversion Data 3 Conversion Data 4 Conversion Data Ready Event ADCDATA DATA0 DATA1 DATA2 x GAINCAL2 T GCAL

FIGURE 5-13:

DATA3 x GAINCAL2 T GCAL

ADC Output and Data Ready Event Behavior with Digital Gain Error Calibration Enabled.

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5.14 Conversion Modes

The ADC includes several conversion modes that can be selected through the CONV_MODE[1:0] bits located in the CONFIG3 register. The ADC behavior, with respect to these bits, depends on whether the ADC is in MUX or Scan mode. Table 5-14 summarizes the possible configurations.

TABLE 5-14: ADC CONVERSION MODES IN MUX OR SCAN MODES

CONVERSION MODES IN MUX MODE In MUX mode, the user can choose between one-shot and continuous conversions. A one-shot conversion is a single conversion and takes a certain Conversion Time, T CONV (or 2 x T CONV when AZ_MUX = 1; see Section 5.1.3 “ADC Offset Cancellation Algorithm”). Once this conversion is performed, the part automatically returns to a Standby or ADC Shutdown state, depending on the CONV_MODE[1:0] bits setting. The Conversion mode determined by the CONV_MODE[1:0] bits setting will also affect the state of the ADC_MODE[1:0] bits, as described in Table 5-14. The conversion can be preceded by a start-up time that depends on the ADC state (see Section 5.11 “ADC Start-up Timer”). One-Shot mode is recommended for low-power, low bandwidth applications, requiring a once in a while A/D conversion.

Returns to ‘10’ after one conversion (MUX mode) or one Scan cycle (Scan mode).

Performs continuous Scan Stays at ‘11’. cycles with TIMER[15:0] bits delay between each cycle.

In Continuous Conversion mode, the ADC is never placed in Standby or ADC Shutdown mode and converts continuously without any internal Reset. In this mode, the output data rate of the ADC is defined by DRCLK (see Figure 5-5). The digital decimation filter induces a pipeline or group delay of T CONV for the first data ready and is structured to give a continuous stream of data at the DRCLK rate after this first data (the internal registers of the filter are never reset in this mode, thus the decimation filter acts as a moving average). Each data ready interrupt corresponds to a valid and complete conversion that was processed through the digital filter (the digital filter has no latency in this respect). This mode allows a faster data rate than the One-Shot mode, and is therefore, recommended for higher bandwidth applications. The pipeline delay should be carefully determined and adapted to the user needs, especially in closed-loop, low-latency applications. This mode is recommended for applications requiring continuous sampling/averaging of the input signals. If AZ_MUX = 1, the Continuous Conversion mode is replaced by a series of subsequent One-Shot mode conversions, with a Reset in between each conversion. This makes the group delay equal to 2 x T CONV and the data rate equal to 1/(2 x T CONV ). Figure 5-14 and Figure 5-15 detail One-Shot and Continuous Conversion modes for MUX mode.

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MCP3465R

T ADC_SETUP T CONV Shutdown or Reset Depending on CONV_MODE[1:0] MUX One-Shot Conversion Mode Timing Diagram.

Write Read ADC

Data 1

Don’t Care Continuous Clocking ADC_MODE 00 11 ADC STATUS Shutdown MCLK FIGURE 5-15:

Start-up Data 1 Conversion T ADC_SETUP T CONV Read ADC

Data 2 Data 2 Conversion Data 3 Conversion 1/DRCLK 1/DRCLK MUX Continuous Conversion Mode Timing Diagram.

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5.14.2 CONVERSION MODES IN SCAN

MODE If CONV_MODE[1:0] = 11, the ADC runs in a Scan Cycle mode with a TIMER[15:0] delay between cycles. Writing the CONV_MODE[1:0] bits with the SPI interface within a conversion does not create an internal Reset. It is recommended not to wait for the end of a conversion to change the CONV_MODE[1:0] bits to the desired value, but to change to the desired value just after the data are ready to avoid possible glitches. Figure 5-16 and Figure 5-17, respectively, detail the ADC timing behavior in One-Shot and Continuous Conversion modes when configured for Scan mode, with N channels chosen among 16 Scan possibilities.

In Scan mode, the device takes one conversion per channel and multiplexes the input to the next channel in the Scan sequence. Therefore, all conversions are One-Shot mode conversions, no matter how the CONV_MODE[1:0] bits are set. Each conversion takes the same time, T CONV (or 2 x T CONV when AZ_MUX = 1; see Section 5.1.3 “ADC Offset Cancellation Algo-

01 or 10, the Scan cycle is executed once and then the ADC is placed into Standby or ADC Shutdown mode.

SPI Write Write CONV_MODE = 0x/10 ADC_MODE = 11 MCLK Read ADC Data 1 Don’t Care ADC_MODE 00 ADC STATUS Shutdown FIGURE 5-16:

Read ADC Data N Continuous Clocking ‘0x’ or ‘10’ Depending on CONV_MODE 11 Start-up Channel 1 Conversion Reset Channel 2 Conversion Reset Channel N Conversion (Last in Cycle)

T DLY_SCAN T CONV T ADC_SETUP T CONV T DLY_SCAN T CONV Shutdown or Reset Depending on CONV_MODE Scan One-Shot Conversion Mode Timing Diagram.

T ADC_SETUP Start-up Channel 1 Conversion Reset Channel 2 Conversion Reset Channel N Conversion (Last in Cycle)

T DLY_SCAN T CONV T ADC_SETUP T CONV T CONV T DLY_SCAN Shutdown or Reset Depending on TIMER[23:0] Settings

T TIMER_SCAN Start-up Channel 1 Conversion Channel 2 Conversion Reset (New Cycle) (New Cycle)

T CONV T DLY_SCAN T CONV Start-up Time is Reduced to 0 if T TIMER_SCAN < 256 DMCLK Periods

FIGURE 5-17:

DS20006414C-page 58 Scan Continuous Conversion Mode Timing Diagram.

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MCP3465R

5.15 Scan Mode

5.15.1 5.15.2

SCAN MODE PRINCIPLE The ADC is, by default, in MUX mode at power-up. The

ADC enters Scan mode as soon as one of the SCAN[15:0] bits in the SCAN register is set to ‘1’. MUX mode and Scan mode cannot be enabled at the same time. When SCAN[15:0] = 0x0000, Scan mode is disabled and the part returns to MUX mode, where the input channel selection is defined by the MUX[7:0] bits.

In Scan mode, the device sequentially and automatically converts a list of predefined differential inputs (also referred to as input channels) in a defined order. After this series of conversions, the ADC can be placed in Standby or ADC Shutdown mode, or it can wait a certain time in order to perform the same sequence of conversions periodically. The Scan cycle conversions are effectively started as

soon as the ADC_MODE[1:0] bits are programmed through the SPI interface to ‘11’ (Direct Write or Fast command, ADC Reset and restart). After the ADC_MODE[1:0] bits are set to ‘11’, they keep the same value until the Scan mode is completed or aborted.

This mode is useful for applications that require constant monitoring of defined channels or internal resources (like AV DD or VCM), and allows a minimal and simplified communication. When in Scan mode, the MUX register (address: 0x6) becomes a Don’t Care register. Each SCAN[n] bit defines a possible input channel for the

Scan cycle, which corresponds to a certain selection of the analog multiplexer input channel and possibly a certain predefined gain of the ADC. The Scan cycle will process and convert each channel that has been enabled (SCAN[n] = 1) with a defined order of priority, from MSb to LSb (SCAN[15] to SCAN[0]). The list of channels with their corresponding inputs is defined in Table 5-15.

Scan mode includes a configurable delay between each Scan cycle, as well as a configurable delay between each conversion within a Scan cycle. Each conversion within the Scan cycle leads to a data ready interrupt and to an update of the ADCDATA register as soon as the current conversion is finished. The device does not include additional memory to retain all Scan cycle A/D conversion results. Therefore, each result has to be read when it is available and before it is overwritten by the next conversion result.

TABLE 5-15:

SCAN MODE ENABLE AND SCAN CHANNEL SELECTION When using DATA_FORMAT[1:0] = 11, each channel conversion result in the Scan sequence can be identified with a Channel ID (CH_ID[3:0]) code that will appear in the four MSbs of the ADCDATA register output value (Section 5.6 “ADC Output Data Format”). The Channel ID indicates the channel that sends the output data. Table 5-15 shows each possible Channel ID value and its associated channel.

ADC CHANNEL SELECTION SCAN[n]

Bit (1) Channel Name Channel ID MUX[7:0] Corresponding Setting Specific ADC Gain 15 OFFSET 1111 0x88 None 14 V CM 1110 0xF8 1x 13 AV DD 1101 0x98 0.33x 12 TEMP 1100 0xDE 1x 8 Differential Channel A (CH0-CH1) 1000 0x01 None 1 Single-Ended Channel CH1 0001 0x18 None Single-Ended Channel CH0 0000 0x08 None 0 Note 1: SCAN[11:9] and SCAN[7:2] are not available for the MCP3465R, as it is a 2-channel device. These bits

must remain set to ‘0’.

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5.15.3 5.15.3.1 SCAN MODE INTERNAL RESOURCE CHANNELS

Analog Supply Voltage Reading (AV DD ) During the conversion that reads AV DD in Scan mode, the multiplexer selection becomes 0x98 (AV DD – A GND ), which is equal to the analog power supply voltage. Since AV DD is the highest voltage available in the chip, when reading AV DD in Scan mode, the gain of the ADC is automatically set to 1/3x, which maximizes the input full-scale range regardless of the GAIN[2:0] bits setting. This temporary internal configuration does not change the register settings; it only impacts the gain of the device during this conversion. With this fixed 1/3x gain, the ADC can measure the maximum specified analog supply voltage (AV DD = 3.6V) with a reference voltage as low as 1.2V.

5.15.3.2 The V CM reading is susceptible to the gain and offset errors of the ADC, which should be calibrated to obtain a precise internal Common-mode measurement.

5.15.4 DELAY BETWEEN CONVERSIONS

WITHIN A SCAN CYCLE (DLY[2:0]) While the ADC and multiplexer are optimized to switch from one channel to another instantaneously, it may not be the case of an application that requires additional settling time to overcome the transition. The device can insert an additional delay between each conversion of the Scan cycle. The delay value is controlled by the DLY[2:0] bits located in the SCAN register (SCAN[23:20]). See Table 5-16.

TABLE 5-16:

Temperature Reading (TEMP)

DELAY BETWEEN CONVERSIONS WITHIN A SCAN CYCLE DLY[2:0] Delay Value (DMCLK Periods)

111 512 110 256 101 128 100 64 011 32 Offset Reading (OFFSET) 010 16 During the conversion that reads OFFSET in Scan mode, the differential MUX output is shorted to A GND (internally). The offset reading varies from part to part, and over AV DD and temperature. The reading of this offset value can be used for the device offset calibration or tracking of the offset value in applications.

001 8 000 0 During the conversion that reads TEMP in Scan mode, the multiplexer selection becomes 0xDE, which enables the two temperature diode sensors at each input of the ADC. During the temperature reading, the ADC gain is automatically set to 1x, regardless of the GAIN[2:0] bits setting. This temporary internal configuration does not change the register setting; it only impacts the gain of the device during this conversion.

5.15.3.3 There is no automatic offset calibration in the device, so the user has to manually write the opposite (signed value) of the offset measured into the OFFSETCAL register to effectively cancel the offset on the subsequent outputs.

5.15.3.4 V CM Reading (V CM ) During the conversion that reads V CM , the device monitors the internal Common-mode voltage of the device in order to ensure proper operation.

The delay is only added in between two conversions of the same Scan cycle. There is no delay added at the end or the beginning of each Scan cycle due to the DLY[2:0] bits setting. During this delay, the ADC is internally kept in Standby mode (ADC_MODE[1:0] = 10 internally, but the ADC_MODE[1:0] bits are always read as ‘11’ through the SPI interface). The analog multiplexer switches to the next selected input at the end of each conversion (i.e., at the beginning of the added delay, so that the application has additional time to settle properly).

The V CM voltage of the device should be located at 1.2V, ±2% to ensure proper accuracy. With this setting, the internal multiplexer setting becomes 0xF8 (V CM – A GND ). In order to properly measure V CM , the reference voltage must be larger than 1.2V. During the V CM reading, the gain of the ADC is set to 1x, regardless of the GAIN[2:0] bits setting. This temporary internal configuration does not change the register setting; it impacts the gain of the device during this conversion.

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5.15.5 DELAY BETWEEN SCAN CYCLES

(TIMER[15:0]) During Continuous mode, Scan cycles are processed continuously, one after another, separated by a time delay (T TIMER_SCAN ), which is defined by the TIMER register (address: 0x8) value. During this delay, the ADC is automatically placed into a power-saving mode (Standby or ADC Shutdown). The T TIMER_SCAN delay offers better power efficiency for applications which run a Scan sequence periodically. Since the delay can be very long, it allows synchronous applications with very slow update rates without having to use an external timer. The TIMER register defines the time, T TIMER_SCAN , between cycles with a 16-bit unsigned value going from 0 to 16777215 DMCLK periods. Table 5-17 details the TIMER values with respect to the TIMER[15:0] code.

TABLE 5-17: TIMER DELAY VALUE

The internal TIMER counter will decrement from the T TIMER_SCAN value to 0 and launch the new Scan cycle. If the T TIMER_SCAN value is greater than T ADC_SETUP (256 DMCLK periods), the device will enter ADC Shutdown mode (ADC_MODE is set to ‘00’ internally) at each end of a Scan cycle. When the internal TIMER counter reaches 256, the device will start the ADC during a T ADC_SETUP time to be ready to convert when the internal counter reaches 0. If the T TIMER_SCAN value is less than T ADC_SETUP , the part will be placed in Standby mode between Scan cycles (ADC_MODE is set to ‘10’ internally). ADC_MODE[1:0] bits in the CONFIG0 register can only be read as ‘11’ by the SPI interface during the entire Scan cycle and between Scan cycles.

5.16 A/D Conversion Automatic Reset and Restart Feature

When the A/D conversions are running, the user can change the device configuration through the SPI interface by writing any register. Some register settings directly impact the conversion results and lead to invalid ADC data if they are changed within a conversion. The device incorporates an automatic reset and restart feature for the A/D conversions to avoid these  2020-2021 Microchip Technology Inc.

invalid data. Some register writes with the SPI interface during a conversion will automatically reset and restart the A/D conversion with the new settings. The automatic reset and restart feature behavior depends on the register bits that are written by the SPI interface.

5.16.1 REGISTER BIT MODIFICATIONS

NOT CAUSING RESET/RESTART The first group of bits will not generate any reset and restart. This group is composed of all the unused bits, all the read-only bits and some digital settings, such as CONV_MODE[1:0], DATA_FORMAT[1:0], CRC_FORMAT, EN_CRCCOM, EN_FASTCMD and LOCK[7:0] bits.

5.16.2 REGISTER BIT MODIFICATIONS

CAUSING IMMEDIATE RESET/RESTART The second group of bits generates a reset and a restart. The reset is immediate, the restart is only valid after a period of two MCLK periods (necessary to handle the reset and ensures that the restart is synchronous with the master clock). This group is composed of settings that do not induce an analog operating point change. This group includes: ADC_MODE[1:0], PRE[1:0], OSR[3:0], GAIN[2:0], AZ_MUX, EN_OFFCAL, EN_GAINCAL, MUX[7:0] and DLY[2:0] bits. The EN_OFFCAL and EN_GAINCAL bits generate the reset and restart only if they are changed to a new value. An overwrite of the same value has no effect. In Scan mode, the reset and restart feature will just restart the current conversion for this group of bits; the Scan cycle is not modified and not restarted. The MUX[7:0] bits can be changed within Scan mode without generating a reset and a restart, since this register is a Don’t Care during Scan mode. The DLY[2:0] bits can be changed during the MUX mode without generating a reset and restart since these bits are Don’t Care during the MUX mode. The OFFSETCAL[23:8] and GAINCAL[23:8] bits only generate a reset and a restart when written if their corresponding enable bit (EN_OFFCAL, EN_GAINCAL) is enabled. The ADC_MODE[1:0] bits generate an immediate reset and restart, but only if they are overwritten with ‘11’ (in any other case, the conversions are stopped). Depending on the part being in MUX or Scan mode, the reset and restart feature will reset the conversion or the complete Scan cycle.

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5.16.3 REGISTER BIT MODIFICATIONS

CAUSING DELAYED RESET/RESTART A third group of bits will generate a reset and a restart that induce a new start-up delay (T ADC_SETUP ), so that the internal analog operating points can be settled with the new settings before the new conversion is started. The reset is immediate; the start-up timer is only restarted after a period of two MCLK periods (necessary to handle the reset and to ensure that the restart is synchronous with the master clock). Overall, the delay from the reset to the actual restart of the conversion with the new settings is then 2 MCLK + T ADC_SETUP . This group includes the CONFIG0 and RESERVED registers at addresses, 0xB and 0xC. The CONFIG0 bits induce a start-up timer delay only if they are changed to a new value. If they are overwritten with the same value, they will generate an immediate reset and restart. In Scan mode, the reset and restart feature will just restart the current conversion for this group of bits; the Scan cycle is not modified and not restarted. This third group of bits will induce a start-up timer delay, even when ADC_MODE[1:0] = 10 or if the ADC is in Standby mode.

Depending on the phase between the AMCLK and the SPI commands, the 2-MCLK delay can turn into a 4-MCLK delay to ensure the proper synchronization of the device. If very precise synchronization is required, it is recommended to not change the register configurations (i.e., not during conversions). In MUX mode, the TIMER and SCAN registers do not generate a reset and restart when written, except if the SCAN register is modified to effectively enter in Scan mode. In this case, the MUX mode is superseded by the Scan mode immediately. In Scan mode, a write access of the SCAN register, during or between conversions within the Scan cycle, will create a reset and restart of the whole Scan sequence. Within the same conditions, a write access on the TIMER register will not create a reset and restart of the entire Scan sequence. However, during the T TIMER_SCAN delay between Scan cycles, a write on the SCAN register does not generate a reset and a restart of the entire sequence. Within the same conditions, a write on the TIMER register generates a reset and a restart of the entire sequence.

During the reset and restart sequence, the reset is immediate and resets the internal phases to the original state, which can lead to a discontinuity in the clock output frequency if the AMCLK clock output is enabled. The restart is synchronous with the AMCLK generation and is effective only after two MCLK periods.

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MCP3465R

6.0 SPI SERIAL INTERFACE AND DEVICE OPERATION

6.1 Overview

The MCP3465R device uses an SPI interface to read and write the internal registers. The device includes a four-wire (CS, SCK, SDI, SDO) serial SPI interface that is compatible with SPI Modes 0,0 and 1,1. Data are clocked out of the device on the falling edge of SCK and data are clocked into the device on the rising edge of SCK. In these modes, the SCK clock can Idle either high (1,1) or low (0,0). The digital interface is asynchronous with the ADC conversion clock (i.e., the MLCK clock controls the ADC sampling and digital filtering when the internal oscillator is selected as the conversion clock source). However, when an external clock is selected as the conversion clock source, SCK becomes MCLK; therefore, it makes the interface and conversion clock synchronous signals. All digital input pins are Schmitt Triggered to avoid system noise perturbations on the communications. The SPI interface is maintained in a Reset state during POR. Each SPI communication starts with a CS falling edge and stops with the CS rising edge. Each SPI communication is independent. When CS is logic high, SDO is in high-impedance, the transitions on SCK and SDI have no effect. Changing from SPI Mode 1,1 to an SPI Mode 0,0 and vice versa is possible, and must be done while the CS pin is logic high. Any CS rising edge clears the communication and resets the SPI digital interface. See Figure 1-1 for the SPI timing details. The MCP3465R digital interface is capable of handling various Continuous Read and Write modes, which allows for ADC data streaming or full register map writing within only one communication (and with only one unique COMMAND byte). It also includes single byte Fast commands. The device does not include a Master Reset pin, but it includes an SPI Fast command to be able to fully reset the part at any time and place it back in a default configuration. The device family also includes advanced security features to secure communication and alert users of unwanted Write commands that change the desired configuration. To secure the entire configuration, the device includes an 8-bit lock code (LOCK[7:0]), which blocks all Write commands to the full register map if the value of the lock code is not equal to a defined password (0xA5). The user can protect its configuration by changing the LOCK[7:0] value to 0x00 after full programming, so that any unwanted Write command will not result in a change in the configuration. Each SPI read communication can be secured through a selectable CRC-16 checksum provided on the SDO pin at the end of every communication sequence. This checksum computation is compatible with the DMA CRC hardware of the PIC24 and PIC32 MCUs, as well as many other MCU references, resulting in no additional overhead for the added security.

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Once the part is locked (write-protected), an additional checksum calculation also runs continuously in the background to ensure the integrity of the full register map. All writable registers of the register map are processed through a CRC-16 calculation engine and give a CRC-16 checksum that depends on the configuration. This checksum is readable from the CRC register and updated when MCLK is running. If there is a change in the checksum, a CRC interrupt generates a flag to warn the user that the configuration has been corrupted. The MCP3465R device does not incorporate a dedicated IRQ pin, but two IRQ mechanisms are available for users to synchronize with Data Ready Events, and retrieve POR and CRC errors that could happen during operations. MCP3465R does not incorporate a dedicated MCLK I/O pin, as the rest of the family of MCP3465R devices, due to its low pin count. However, the SCK pin can be used as an input to retrieve MCLK from an external clock source, or as an output to gather AMCLK generated by the internal oscillator to synchronize with the MCU.

6.2 SPI Communication Structure

The MCP3465R interface has a simple communication structure. Every communication starts with a CS falling edge and stops with a CS rising edge. The communication is always started by the COMMAND byte (8 bits) clocking on the SDI input. The COMMAND byte defines the command that will be executed by the digital interface. It includes the device address, the register address bits and the command-type bits. The COMMAND byte is typically followed by data bytes clocked on SDI if the command type is a write and on SDO if the command type is a read. The COMMAND byte can also define a Fast command, and in this case, it is not followed by any other byte. The following subsections detail the COMMAND byte structure and all possible commands. During the COMMAND byte clocking on SDI, a STATUS byte is also propagated on the SDO output to enable easy polling of the device status. During this time, the interface is full-duplex, but the part can still be used by MCUs handling only half-duplex communications if the STATUS byte is ignored.

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6.2.1 COMMAND BYTE STRUCTURE The COMMAND byte fully defines the command that will be executed by the part. This byte is divided into three parts: the device address bits (CMD[7:6]), the command address bits (CMD[5:2]) and the command-type bits (CMD[1:0]). See Table 6-1.

TABLE 6-1:

6.2.2 Register Address/Fast Command

Bits Command Type

Bits DEVICE ADDRESS BITS (CMD[7:6]) The SPI interface of the MCP3465R device is addressable, which means that multiple devices can communicate on the same SPI bus with only one Chip Select line for all devices. Each device communication starts by a CS falling edge, followed by the clocking of the device address (CMD[7:6]). Each device contains an internal device address which the device can respond to. This address is coded on two bits, so four possible addresses are available. The device address is hard-coded within the device and should be determined when ordering the device. The device address is part of the device markings to avoid potential confusion (see Section 9.1 “Package Marking Information (*) ”). When the CMD[7:6] bits match the device address, the communication will proceed and the part will execute the commands defined in the control byte and its subsequent data bytes. When the CMD[7:6] bits do not correspond to the address hard-coded in the device, the command is ignored. In this case, the SDO output will become

TABLE 6-2:

6.2.3 COMMAND BYTE CMD[7] CMD[6] CMD[5] CMD[4] CMD[3] CMD[2] CMD[1] CMD[0] Device Address

Bits high-impedance, which prevents bus contention errors when multiple devices are connected on the same SPI bus (see Figure 6-2). The user has to exit from this communication through a CS rising edge to be able to launch another command.

6.2.5 FAST COMMANDS DESCRIPTION There are five possible Fast commands available for the MCP3465R. For each command, only the COMMAND byte has to be provided on the SPI port and the command is executed right after the COMMAND byte has been clocked. The Fast command codes are detailed in Table 6-2. All undefined command address codes for Fast commands will be ignored and will have no effect. SDO will stay in high-impedance after the COMMAND byte for a Fast command until a CS rising edge is provided. The Fast commands can be enabled or disabled by setting the EN_FASTCMD bit in the IRQ register to ‘1’ (default). Disabling Fast commands can increase the security of the device because it can avoid the execution of unwanted Fast commands, which can be useful in harsh environments.

The STATUS byte structure is described in Figure 6-1.

STAT[7] STAT[6] STAT[5] STAT[4] STAT[3] STAT[2] STAT[1] STAT[0] 0 0 DEV_ADDR [1] DEV_ADDR [0] DEV_ADDR [0] DR_ST ATUS CRCCFG_ ST ATUS POR_ST ATUS Device Address Acknowledge bits FIGURE 6-1:

Interrupt Status bits

STATUS Byte.

The first two bits are always equal to ‘0’ and SDO toggles to ‘0’ as soon as a CS pin falling edge is performed. This allows having an application with multiple devices, with different device addresses, sharing one common SPI bus and avoiding bus contention during STATUS byte clocking.

The ADC Start/Restart command (command address: ‘1010’) overwrites the ADC_MODE[1:0] bits to ‘11’, creating a conversion start (or a restart if the conversion was already running).

The next three bits of the STATUS byte give a confirmation (Acknowledge) of the hard-coded device address. If the device address of the COMMAND byte and the internal device address of the chip match, these three bits will be transmitted and they are equal to: The ADC Standby mode command (command address: ‘1011’) overwrites the ADC_MODE[1:0] bits to ‘10’ and places the ADC in Standby mode.

The ADC Shutdown mode command (command address: ‘1100’) overwrites the ADC_MODE[1:0] bits to ‘00’ and places the ADC in ADC Shutdown mode. The Full Shutdown mode command (command address: ‘1101’) overwrites the CONFIG0 register to 0x00 and places the device in Full Shutdown mode (see Section 5.10 “Low-Power Shutdown Modes” for a full description of this mode). The Full Reset command (command address: ‘1110’) resets the device and places the entire register map into its default state condition, including the non-writable registers. The only difference with a POR event is that the POR_STATUS bit in the IRQ register is set to ‘1’ after a Full Reset and is reset to ‘0’ after a POR event. The user can only clear the ADC Data Output register to its default value by using the Full Reset command.

6.2.6 DEVICE ADDRESS AND STATUS

BYTE DURING CONTROL BYTE During the COMMAND byte clocking on the SDI pin, the SDO pin displays a STATUS byte to help the user retrieve quick interrupt status information. The STATUS byte allows fast polling of the different interrupts without having to read the IRQ register. However, it requires an MCU that can communicate in Full-Duplex mode (SDI and SDO are clocked at the same time). For MCUs that are only half-duplex, the polling of the IRQ status can still be done by reading the IRQ register continuously.

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The STAT[3] bit allows the user to distinguish the SDO output from a High-Impedance state (device address is not matched), as the bits, STAT[4] and STAT[3], are complementary and will induce a deterministic toggle on the SDO output. If the two device address bits are not matched with the internally hard-coded device address bits, SDO is maintained in a High-Impedance state during the rest of the communication and the command is ignored. This behavior avoids potential bus contention errors if multiple devices with different device addresses share the same SPI bus. After the transmission of the first two bits, only one device responds to the command (all other devices with non-matching device addresses keep the SDO in high-impedance). In this case, the user needs to abort the communication (CS rising edge) in order to perform another command. The three LSbs of the STATUS byte are the three Interrupt Status bits: • STAT[2] = DR_STATUS (ADC data ready interrupt

status)

error on the register map interrupt status)

DS20006414C-page 65

MCP3465R

These three Interrupt Status bits are independent of the IRQ register and are cleared each time the STATUS byte is fully clocked. This enables the polling on the STATUS byte as a possible interrupt management solution. All Status bit values are latched together, just after the device address has been correctly recognized by the chip. Any interrupt happening after the two first Status bits have been clocked out will appear in the STATUS byte of the subsequent communication sequence.

Figure 6-2 represents the beginning of each communication with both COMMAND and STATUS bytes depicted. After the STATUS byte is propagated, the SDO pin will be placed in high-impedance for Fast commands or Write commands and will transfer data bytes for Read commands as long as the CS pin stays logic low.

Device Latches SDI on Rising Edge CS

Device Latches SDO on Falling Edge SPI Mode 1,1

SCK SDO High-Z Device Address does not Match

CMD[7:6] CMD[0] CMD[1] CMD[2] CMD[3] Device Address ACK DR_ STATUS 0 CMD[6] Device Address Matches CMD[7:6] CMD[6] High-Z CMD[7] SDO Command

Type Register Address CRCREG_ STATUS POR_ STATUS Device Address CMD[4] CMD[5] Don’t Care CMD[6] SDI CMD[7] SPI Mode 0,0 Interrupts Status High-Z

0 FIGURE 6-2: SPI Communication Start (COMMAND Byte on SDI and STATUS Byte on SDO) when the Device Address Matches/Does Not Match CMD[7:6].

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6.3 Writing to the Device

When the command type is Incremental Write (CMD[1:0] = 10), the device enters Write mode and starts writing the first data byte to the address given in the CMD[5:2] bits.

CONFIG0 (0x1)

CONFIG1 (0x2)

CONFIG2 (0x3) After the STATUS byte has been transferred, SDO stays in a High-Impedance state during an Incremental Write communication. Writing to a read-only address (such as addresses, 0x0 or 0xF) has no effect and does not increment the Address Pointer. The user must stop the communication and restart a communication with a COMMAND byte pointing to a writable address (0x1 to 0xD).

CONFIG3 (0x4)

IRQ (0x5)

MUX (0x6)

SCAN (0x7)

TIMER (0x8) Each register is effectively written after receiving the last bit for the register (SCK last rising edge). Any CS rising edge during a write communication aborts the current writing. In this case, the register being written will not be updated and will keep its old value.

OFFSETCAL (0x9)

GAINCAL (0xA)

Reserved (0xB) The registers may need 8, 16 bits to be effectively written, depending on their address (see Table 8-1). After each register is written, the Address Pointer is automatically incremented as long as CS stays logic low. When the Address Pointer reaches 0xD, the next register to be written is the 0x1 register (see Figure 6-3 for a graphical representation of the address looping). Internal registers located at addresses, 0xB, 0xC and 0xE, should be kept to their default state at all times for proper operation. These are reserved registers and should not be modified.

Reserved (0xC)

LOCK (0xD)

Reserved (0xE)

FIGURE 6-3: Incremental Write Loop.

The Incremental Write feature can be used in order to fully configure the part using a unique communication, which can save time in the application. This unique communication can end at address 0xD, so that the user can also lock the configuration when written, providing additional security in the application (see Section 6.6 “Locking/Unlocking Register Map Write Access”). Figure 6-4 shows an example of a write communication in detail with a single register write. Figure 6-5 shows an example of an Incremental Write communication.

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CS Device latches SDI on rising edge DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13] DATA[14] DATA[15] DATA[16] DATA[17] 0 POR_ STATUS DATA[18] 1 CRCREG_ STATUS DATA[19] CMD[2] DR_ STATUS DATA[20] CMD[3] CMD[6] DATA[23] DATA[21] CMD[4] 0 0 0 DATA[22] CMD[5] Hi-Z CMD[6] SDO CMD[6] Don’t care CMD[7] SDI CMD[7] SCK Don’t care Hi-Z SPI mode 0,0; example with a 24-bit wide register located at address CMD[5:2] CS Device latches SDI on rising edge DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13] DATA[14] DATA[15] DATA[16] DATA[17] DATA[18] DATA[19] DATA[20] DATA[21] 1 CRCREG_ STATUS DATA[22] CMD[2] DR_ STATUS DATA[23] CMD[3] CMD[6] 0 0 POR_ STATUS CMD[4] 0 0 CMD[6] Hi-Z CMD[5] SDO CMD[7] Don’t care CMD[6] SDI CMD[7] SCK DATA[0] Don’t care Hi-Z A<6> SPI mode 1,1; example with a 24-bit wide register located at address CMD[5:2]

FIGURE 6-4: Single Register Write Communication (CMD[1:0] = 10) Timing Diagram.

CS ADDRESS SET 0x1 Depends on ADDR SCK 8x SDI COMMAND BYTE Depends on ADDR+1 ... 8x 8x 8x ... 8x ...

Don’t care CMD[7:6] + ADDR +10 ADDR ADDR + 1 ... ADDR = 0xD ADDR = 0x1 Complete WRITE sequence

Complete WRITE sequence

Complete WRITE sequence Roll-over SDO Hi-Z 0 00XXXXXX Hi-Z Depends on IRQ status

and device address

FIGURE 6-5:

DS20006414C-page 68 Multiple Register Write within One Communication Using Incremental Write Feature.

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MCP3465R

6.4 Reading from the Device

When the Command bit, CMD[0], is equal to ‘1’, the command is a read communication. After the STATUS byte has been transferred, the first register to be read on the SDO pin is the one with the address defined by the Command Address bits (CMD[5:2]). Any CS rising edge during a read communication aborts the current reading. The registers may need 4, 8, 16, 24 or 32 bits to be fully read depending on their address (see Table 8-1). If the CMD[1:0] bits are equal to ‘11’, the command type is Incremental Read. In this case, after each register is read, the Address Pointer is automatically incremented as long as CS stays logic low. The following data bytes are read from the next address sequentially defined in the register map. When the Address Pointer reaches 0xF (last register in the register map for reading), the next register to read is register 0x0 (see Figure 6-6 for a graphical representation of the address looping).

If the CMD[1:0] bits are equal to ‘01’, the command type is Static Read. In this case, the register address defined in the COMMAND byte is read continuously. The Address Pointer is automatically incremented. Continuously clocking SCK while CS stays logic low will continuously read the same register. Reading another register is only possible by aborting the current communication sequence by raising CS and issuing another command. In both Static and Incremental modes, the registers are updated after each register read is fully performed. If the value of the register changes internally during the read, it will only be updated after the end of the read. The value of each register is latched in the SDO Output Shift register at the first rising edge of SCK of each individual register reading. Figure 6-7 shows the bit by bit details of a single register Read communication. Figure 6-8 shows the examples of Static and Incremental Read communications.

ADCDATA (0x0)

CONFIG0 (0x1)

CONFIG1 (0x2)

CONFIG2 (0x3)

CONFIG3 (0x4)

IRQ (0x5)

MUX (0x6)

SCAN (0x7)

TIMER (0x8)

OFFSETCAL (0x9)

GAINCAL (0xA)

Reserved (0xB)

Reserved (0xC)

LOCK (0xD)

Reserved (0xE)

CRCREG (0xF)

FIGURE 6-6: Incremental Read Loop.

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CS Device latches SDI on rising edge Device latches SDO on falling edge DATA[0] DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13] DATA[14] DATA[15] DATA[16] DATA[17] DATA[18] CMD[1] POR_ STATUS DATA[19] CMD[2] DR_ STATUS CRCREG_ STATUS DATA[20] CMD[3] CMD[6] DATA[23] DATA[21] CMD[4] 0 0 0 Don’t care DATA[22] CMD[5] 1 CMD[6] Hi-Z CMD[6] SDO Don’t care CMD[7] SDI CMD[7] SCK Don’t care Hi-Z SPI mode 0,0 ; example with a 24-bit wide register located at address CMD[5:2] CS Device latches SDI on rising edge Device latches SDO on falling edge 1 DATA[1] DATA[2] DATA[3] DATA[4] DATA[5] DATA[6] DATA[7] DATA[8] DATA[9] DATA[10] DATA[11] DATA[12] DATA[13] DATA[14] DATA[15] DATA[16] DATA[17] DATA[18] DATA[19] DATA[20] DATA[21] DATA[22] A<6> Don’t care DATA[23] POR_ STATUS CMD[1] CMD[2] CMD[3] CMD[6] DR_ STATUS CRCREG_ STATUS CMD[4] 0 0 CMD[6] 0 CMD[5] Hi-Z CMD[7] SDO Don’t care CMD[6] SDI CMD[7] SCK DATA[0] Hi-Z SPI mode 1,1; example with a 24-bit wide register located at address CMD[5:2]

FIGURE 6-7:

DS20006414C-page 70 Single Read SPI Communication (Static or Incremental Read).

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MCP3465R

CS SCK SDI Depends on ADDR 8x Don’t Care Depends on

ADDR COMMAND

BYTE ... Depends on ADDR ... ADDR Don’t Care CMD[7:6] + ADDR + 01 SDO High-Z 00XXXXXX ADDR Depends on IRQ status

and device address Complete READ

sequence ADDR 0 Static Read Sequence CS

ADDRESS SET 0x0 SCK Depends on ADDR 8x Depends on ADDR+1 ... Depends on Data Format 16x 8x ... 16x ...

ADDR SDI Don’t Care COMMAND BYTE Don’t Care ...

CMD[7:6] + ADDR + 11 Complete READ sequence 0xF

Roll-over SDO High-Z 00XXXXXX ADDR ADDR + 1 ... ADDR = 0xF ADDR = 0x0 ADDR = 0x1 ... ADDR = 0xF

0 Depends on IRQ status

and device address Complete READ sequence Complete READ sequence

Incremental Read Sequence

FIGURE 6-8: Static and Incremental Read SPI Communications.

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MCP3465R

If the COMMAND byte defines a static read of the ADCDATA register (address: 0x0), the ADC data will be present on SDO and will be updated continuously at each read. In this case, when a data ready interrupt occurs within a read, the data are not corrupted and will be updated to a new value after the old value has been completely read. The ADC register contains a double buffer that prevents data from being corrupted while reading them. The part is able to stream output data continuously with no additional command if the communication is not stopped with a CS rising edge. Figure 6-9 represents the continuous streaming of incoming ADCDATA through the SPI port with both SPI Modes 0,0 and 1,1.

MSb of the data. This mechanism allows the device to continuously read ADC data outputs seamlessly, even in SPI Mode 0,0. In SPI Mode 1,1, the SDO pin stays in the last state (LSb of previous data) after a complete reading, which also allows seamless Continuous Read mode. The ADC output data can only be properly read after a t DODR time, after the data ready interrupt comes in the IRQ register. The t DODR timing is shorter than the time necessary to input a command on the SDI pin, which ensures proper reading when a new Read command is triggered by the data ready interrupt. In case of continuous reading (with CS pin kept logic low), the t DODR timing must be carefully handled by the MCU, but the interrupt service time is generally much longer than the t DODR timing. Retrieving a Data Ready Event by reading the STATUS byte or reading the IRQ register automatically ensures that the t DODR timing is respected.

For continuous reading of ADCDATA in SPI Mode 0,0, once the data have been completely read after a Data Ready Event, the SDO pin takes the MSb value of the previous data at the end of the reading (falling edge of the last SCK clock). If SCK stays Idle at logic low (by definition of Mode 0,0), the SDO pin is updated at the falling edge of the next Data Ready Event with the new CS Device latches SDI on rising edge Device latches SDO on falling edge Don’t care DATA1[30] DATA1[29] DATA1[28] DATA1[31] DATA1[28] DATA0[31] DATA1[29] DATA0[0] DATA0[1] DATA0[2] DATA0[3] DATA0[4] DATA0[5] DATA0[6] DATA0[7] DATA0[8] DATA0[9] DATA0[10] DATA0[11] DATA0[12] DATA0[13] DATA0[14] DATA0[15] DATA0[16] DATA0[17] DATA0[18] DATA0[19] DATA0[20] DATA0[21] DATA0[22] DATA0[23] DATA0[24] DATA0[25] DATA0[26] DATA0[27] DATA0[28] DATA0[31] DATA0[29] DATA0[30] Read Start 1 1 0 CMD[6] 0 0 Hi-Z CMD[6] SDO CMD[7] Read Start DATA1[30] A<0> 0 A<1> 0 R/W 1 A<2> 0 A<3> 0 A<4> 0 Don’t care CMD[6] A<5> SDI CMD[7] A<6> SCK SDO c hanges synchronous ly with the falling

edge (DR interrupt flag) only when MSB is present on SDO Data Ready Event DR Interrupt

(DATA1 is ready)

SPI mode 0,0; ADC Data Format : 32-bit CS Device latches SDI on rising edge Device latches SDO on falling edge R/W 1 Data Ready Event DATA0[1] DATA0[2] DATA0[3] DATA0[4] DATA0[5] DATA0[6] DATA0[7] DATA0[8] DATA0[9] DATA0[10] DATA0[11] DATA0[12] DATA0[13] DATA0[14] DATA0[15] DATA0[16] DATA0[17] DATA0[18] DATA0[19] DATA0[20] DATA0[21] DATA0[22] DATA0[23] DATA0[24] DATA0[25] DATA0[26] DATA0[27] DATA0[28] DATA0[29] DATA0[30] Read Start DATA0[31] 1 1 0 CMD[6] CMD[6] 0 Hi-Z 0 SDO CMD[7] Read Start DATA0[0] DATA1[31] A<0> 0 A<1> 0 A<2> 0 A<3> 0 A<4> 0 Don’t care CMD[6] A<5> SDI CMD[7] A<6> SCK DR Interrupt (DATA1 is ready)

SPI mode 1,1; ADC Data Format : 32-bit

FIGURE 6-9:

DS20006414C-page 72 Continuous ADC Read (Data Streaming) with SPI Mode 0,0 and 1,1.

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MCP3465R

Continuous streaming is possible, but needs extra care from the user to correctly synchronize with the device by using the Data Ready Event.

When enabled, the CRC checksum (CRCCOM[15:0]) is propagated on SDO after each read communication sequence. When MCLK is generated externally, the user can count the number of MCLK clocks sent to the device and read the ADC data after the Data Ready Event that is generated after a defined number of clock periods (see Table 5-6 for more information about the number of clocks required for obtaining Data Ready Events).

In case of a Static Read command, the checksum is propagated after each register read. In case of an Incremental Read command, the checksum is propagated after the last register read in the register map (address: 0xF). Figure 6-11 and Figure 6-12 show typical read communications in Static Read and Incremental Read modes, respectively, when the EN_CRCCOM bit is enabled. Since the STATUS byte is propagated on SDO, it is part of the first message and it is included in the calculation of the first checksum. For subsequent checksum calculations, the message only contains the registers that are effectively read in between two checksums.

If the user desires to perform continuous streaming of ADC output data, it is recommended to poll the STATUS byte and start reading ADC data only when the DR_STATUS bit is effectively set to ‘0’ (see Section 6.8.1 “Conversion Data Ready (DR) Interrupt” for more information about the interrupt mechanisms attached to the Data Ready Event). Retrieving a data ready interrupt, by reading the STATUS byte or reading the IRQ register, automatically ensures that the t DODR timing is respected.

6.5 Securing Read Communications through CRC-16 Checksum

Since some applications can generate or receive large EMI/EMC interferences and large transient spikes, it is helpful to secure SPI communications as much as possible to maintain data integrity and desired configurations during the application’s lifetime. The communication data on the SDO pin can be secured through the insertion of a Cyclic Redundancy Check (CRC) checksum at the end of each read sequence. The CRC checksum on communications can be enabled or disabled through the EN_CRCCOM bit in the CONFIG3 register. The CRC message ensures the integrity of the read sequence bits transmitted on the SDO pin. The CRC checksum in the MCP3465R uses the 16-bit CRC-16 ANSI polynomial, as defined in the IEEE 802.3 Standard: x 16 + x 15 + x 2 + 1. This polynomial can also be noted as 0x8005. CRC-16 detects all single and double-bit errors, all errors with an odd number of bits, all burst errors of 16 bits in length or less and most errors for longer bursts. This allows an excellent coverage of the SPI communication errors that can occur in the system and heavily reduces the risk of a miscommunication, even under noisy environments.

 2020-2021 Microchip Technology Inc.

The CRC-16 format displayed on the SDO pin depends on the CRC_FORMAT bit in the CONFIG3 register (see Figure 6-10). It can have a 16-bit or 32-bit format to be compatible with both 16-bit and 32-bit MCUs. The CRCCOM[15:0] bits calculated by the device do not depend on the format (the device always calculates a 16-bit only CRC checksum).

(Default)

CRCCOM[15:0]

FIGURE 6-10: Communications.

0x0000

CRC Format Table for Read The CRC calculation computed by the device is fully compatible with the CRC hardware contained in the Direct Memory Access (DMA) of the PIC24 and PIC32 MCU product lines. The CRC message that should be considered in the PIC ® device DMA is the concatenation of the read sequence and its associated checksum. When the DMA CRC hardware computes this extended message, the resulting checksum should be 0x0000. Any other result indicates that a miscommunication has occurred, and that the current communication sequence should be stopped and restarted.

DS20006414C-page 73

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CS Depends on ADDR SCK 8x SDI COMMAND BYTE 16x or 32x Depending on CRC format Depends on

ADDR 16x or 32x Depending on CRC format ...

ADDRESS SET ADDR

Roll-over

Don’t Care Don’t Care

CRC Checksum CMD[7:6] + ADDR + 01 SDO High-Z

0 STATUS BYTE ADDR Complete READ sequence including STATUS Byte

= First Message for CRC Calculation

FIGURE 6-11:

CRC Checksum ADDR CRC Checksum First checksum New message New checksum ...

SPI Static Read with Communication CRC Enabled.

CS

ADDRESS SET 0x0 SCK 8x Depends on ADDR Depending on ADDR+1 ... 16x 16x or 32x Depending on CRC format Depends on Data Format 8x ... 24x 16x or 32x Depending on CRC format ...

ADDR SDI Don’t Care COMMAND BYTE Don’t Care ...

CMD[7:6] + ADDR + 11 Complete READ sequence 0xF

Roll-over SDO High-Z

0 STATUS BYTE ADDR ADDR + 1 ...

Complete READ sequence including STATUS Byte

= First Message for CRC Calculation FIGURE 6-12:

DS20006414C-page 74 ADDR = 0xF CRC Checksum ADDR = 0x0 First Checksum ADDR = 0x1 New Message ... ADDR = 0xF CRC Checksum CRC Checksum (not part of register map)

New Checksum

SPI Incremental Read with Communication CRC Enabled.

 2020-2021 Microchip Technology Inc.

MCP3465R

6.6 Locking/Unlocking Register Map Write Access

The MCP3465R digital interface includes an advanced security feature that allows locking or unlocking the register map write access. This feature prevents the miscommunication that can corrupt the desired configuration of the device, especially an SPI read becoming an SPI write because of the noisy environment. The last register address of the incremental write loop (0xD: LOCK) contains the LOCK[7:0] bits. If these bits are equal to the password value (0xA5), the register map write access is not locked. Any write can take place and the communications are not protected. The MCP3465R device is, by default after POR, in an unlocked state (LOCK[7:0] = 0xA5). When the LOCK[7:0] bits are not equal to 0xA5, the register map write access is locked. The register map and the full device configuration are write-protected. Any write to an address other than 0xD will yield no result. All the register addresses, except the address 0xD, become read-only. In this case, if the user wants to change the configuration, the LOCK[7:0] bits have to be reprogrammed back to 0xA5 before sending the desired Write command. The LOCK[7:0] bits are located in the last register of the Incremental Write address loop, so the user can program the entire register map, starting from 0x1 to 0xD, within one continuous write sequence and then lock the configuration at the end of the sequence by writing all zeros (for example) in the 0xD address.

6.7 Detecting a Configuration Change through CRC-16 Checksum on the Register Map and its Associated Interrupt Flag

In order to prevent internal corruption and to provide additional security on the register map configuration, the MCP3465R device includes an automatic and continuous CRC checksum calculation on the full register map Configuration bits. This calculation is not the same as the communication CRC checksum described in Section 6.5 “Securing Read Communications through CRC-16 Checksum”.

Since this feature is intended to protect the configuration of the device, this calculation is run continuously only when the register map is locked (LOCK[7:0]), which is different than 0xA5 (see Section 6.6 “Locking/Unlocking Register Map Write Access”). If the register map is unlocked (for example, after POR), the CRCCFG[15:0] bits are cleared and no CRC is calculated. The DR_STATUS, CRCCFG_STATUS and POR_STATUS bits are set to ‘1’ (default) and the CRCCFG[15:0] bits are set to ‘0’ (default) for this calculation, as they could vary and lead to unwanted CRC errors. After the DR_STATUS, CRCCFG_STATUS and POR_STATUS bits are cleared (with a read on the IRQ register), the CRC checksum on the register map can be verified by reading all registers in an incremental read sequence and by using the CRC communication. At the second incremental read loop, the checksum provided by the CRC communication must be equal to all zeros if the checksum on the register map is correct. The checksum will be calculated for the first time in 11 DMCLK periods. This first value will then be the reference checksum value and will be latched internally until an unlocking of the register map occurs. The checksum will then be calculated continuously every 11 DMCLK periods and checked against the reference checksum. If the checksum is different than the reference, an interrupt flag is generated on the CRCCFG_STATUS bit within the STATUS byte on SDO, and on the CRCCFG_STATUS bit in the IRQ register. The interrupt flag is maintained on both mechanisms until the register map write access is unlocked. When the part write access is unlocked, the interrupt on both interrupt mechanisms is cleared when the interrupt is read (read STATUS byte or read IRQ register). At power-up, the interrupt is not present and the register map is unlocked. As soon as the user finishes writing its configuration, the user needs to lock the register map (for example, by writing 0x00 in the LOCK bits) to be able to use the interrupt flag and to calculate the checksum of the register map.

This calculation takes the contents of the register map, from addresses 0x1 to 0xF, and produces a checksum which is held in the CRCCFG[15:0] bits located in the CRCCFG register (address: 0xF). The CRC checksum for the register map uses the 16-bit CRC-16 ANSI polynomial as defined in the IEEE 802.3 Standard: x 16 + x 15 + x 2 + 1.

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6.8 Interrupts Description

The MCP3465R device incorporates two interrupt mechanisms to be able to synchronize the device with an MCU and to warn against external perturbations. There are three events that can generate interrupt flags: • Data Ready • POR • CRC Error on the Register Map Configuration A summary of the different mechanisms is available in Table 6-3.

TABLE 6-3: INTERRUPT DESCRIPTION SUMMARY TABLE

6.8.1 CONVERSION DATA READY (DR)

INTERRUPT The data ready interrupt happens when a new conversion is ready to be read on the ADCDATA register. This event happens synchronously with DMCLK and at each end of conversion. This interrupt is implemented with two different and independent mechanisms: STATUS byte on SDO and IRQ register Status bit. 1.

STATUS byte on SDO. When the interrupt occurs on the next STATUS byte transmitted on SDO, the DR_STATUS bit will be logic low. Once the STATUS byte has been transmitted, the DR_STATUS bit appears as ‘1’ until a new interrupt is present. If the interrupt occurs between two STATUS byte transmissions, the DR_STATUS bit on SDO will appear as equal to ‘0’ on the second reading. IRQ register Status bit. When the interrupt occurs, the DR_STATUS bit in the IRQ register is set to ‘0’. Once the IRQ register has been fully read, this DR_STATUS bit is reset to ‘1’. If the interrupt occurs between two readings of the IRQ register, the IRQ register Status bit appears as equal to ‘0’ on the second reading.

6.8.2 6.8.2.1 STATUS Byte on SDO When the device has just powered up, on the first STATUS byte transmitted on SDO (first communication), the POR_STATUS bit is logic low. Once the STATUS byte has been transmitted, the POR_STATUS bit appears as ‘1’ until the part is powered down. If a POR event occurs between two STATUS byte transmissions, and if the part is properly repowered up, the POR_STATUS bit on SDO will appear as equal to ‘0’ on the latter reading. This mechanism can only work when the power supplies are back above the POR thresholds on the analog and digital cores, as retrieving data from the SPI port is not possible when the device is in a POR state.

6.8.2.2 IRQ Register Status Bit When the device has just powered up, the POR_STATUS bit in the IRQ register is set to ‘0’. Once the IRQ register has been fully read, this POR_STATUS bit is once again reset to ‘1’. If a POR event occurs between two readings of the IRQ register, the IRQ register Status bit will appear as equal to ‘0’ on the second reading. This mechanism can only work when the power supplies are back above the POR thresholds on the analog and digital cores. POR INTERRUPT The POR interrupt informs the user if a POR event has happened. This interrupt is implemented with two different and independent mechanisms: STATUS byte on SDO and IRQ register Status bit.

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MCP3465R

6.8.3 CRCCFG ERROR INTERRUPT The CRCCFG interrupt happens when an error in the CRC-16 checksum has been detected in the register map CRC calculation. This interrupt is implemented with two different and independent mechanisms: STATUS byte on SDO and IRQ register Status bit.

6.8.3.1 STATUS Byte on SDO In case of a CRCCFG error on the next STATUS byte transmitted on SDO, the CRCCFG_STATUS bit is logic low. Once the STATUS byte has been transmitted, the CRCCFG_STATUS bit appears as ‘1’ until a new interrupt occurs. If the error is detected again between two STATUS byte transmissions, the CRCCFG_STATUS bit on SDO will appear as equal to ‘0’ on the second reading.

6.8.3.2 IRQ Register Status Bit In case of a CRCCFG error, the CRCCFG_STATUS bit in the IRQ register is set to ‘0’. Once the IRQ register is fully read, the CRCCFG_STATUS bit is reset to ‘1’. If the CRCCFG error happens again between two readings of the IRQ register, the IRQ register Status bit will appear as ‘0’ on the second reading.

Note:

6.9

If MCLK starts running before the device is locked, an interrupt can momentarily occur, even if registers have not been corrupted. In such a case, the user must send a start/restart conversion Fast command, which clears the unwanted interrupt and correctly restarts the CRC calculations.

Master Clock Input/Output Modes

The MCP3465R device does not include a dedicated input/output master clock pin. In the MCP3465R, the SCK pin is used to enter the external Master Clock (MCLK) for the ADC or to deliver the Analog Master Clock to the MCU. The SCK pin can be bidirectional and the direction of the SCK I/O is determined by the CLK_SEL[1:0] bits setting. Additionally, the transitions from Input to Output mode and vice-versa, need extra care in order to avoid bus contention errors and induce a specific sequence that allows smooth transitions. These transitions are described in the following sections and in Figure 6-13 to Figure 6-16. The following sections detail precisely each possible mode of operation as defined in Table 5-12.

6.9.1 INTERNAL OSCILLATOR MODE

WITHOUT EXTERNAL CLOCK

The master clock is not propagated on any output. Toggling the CS pin does not reset or impact the internal MCLK clock generation.

6.9.2 EXTERNAL CLOCK MODE

This mode is accessed by writing CLK_SEL[1:0] = 0x. This mode defines the SCK pin as both the Serial Clock input and the Master Clock input. In this mode, the SCK and MCLK are equal, therefore the device becomes a fully synchronous system. If the ADC is not in Conversion mode, the SCK input clock has no restrictions, but if the ADC is running, the SCK input clock should be continuous and its frequency should be kept constant to ensure the optimal performance of the ADC. During this Free-Running Clock mode, the SPI communications should not impact the clock frequency and need to be synchronized on the SCK input. Toggling the CS pin does not reset or impact the MCLK clock input. SCK always remains an MCLK input in this mode, even when CS is logic high, while the SPI commands are not taken into account anymore. Using an MCU that can be set in Framed SPI mode can help to design a fully synchronous system. The MCU can continuously send frames at the same frequency, where some frames are simply clock frames with no communication (CS is kept logic high) and some frames include communications (CS is kept logic low and SDI can toggle to define commands). Therefore, the toggling of the CS input is synchronized with the free-running clock, SCK, so that the communications can happen at any desired time without impacting the SCK continuous clocking. Since the SCK pin remains as an input for both CLK_SEL[1:0] = 0x and 10 modes, the transition from one to another is instantaneous, as soon as the Write command is completed (end of last bit of the CONFIG0 register). The transition from one to another mode resets any current conversion and resets the internal clock phases in order to restart from a unique predefined Reset state. Respecting the SPI timings ensures that the transition from one mode to another is handled properly by the device. When a transition to CLK_SEL[1:0] happens, the internal oscillator is restarted from a Shutdown state and the start-up time of the oscillator is necessary to ensure that the internal clock frequency is settled to a stable final value. Figure 6-13 and Figure 6-14 show in detail the transitions from and to CLK_SEL[1:0] = 0x and 10 modes for the MCP3465R device. In Figure 6-14, the prescaler is set to PRE[1:0] = 00 (1:1) so that AMCLK = MCLK.

This mode is accessed by writing CLK_SEL[1:0] = 10. This mode is the easiest to use, as SCK does not share its functionality. In this mode, SCK is only the Serial Clock input for the SPI digital Interface. The Master Clock (MCLK) is generated by the internal oscillator and runs asynchronously with the Serial Clock (SCK).

 2020-2021 Microchip Technology Inc. DS20006414C-page 77

MCP3465R

CS High Aborts SPI Communication but Doesn’t Stop Internal MCLK CS External MCLK Mode Validated SPI Mode 1,1 SCK Don’t Care 1 8 1 Continuous Clocking 8 1 8

SPI Mode 0,0 SCK PAD Direction SDI SDO Input Don’t Care Write CLK_MODE = 0x (Ext CLK input on pin SCK) COMMAND Byte High-Z Continuous Write Don’t Care COMMAND Byte High-Z STATUS Byte STATUS Byte Reset MCLK SPI mode 1,1 Continuous clocking MCLK

SPI mode 0,0

MCLK Source Internal Only (no output)

FIGURE 6-13:

External = SCK MCP3465R Transition from CLK_SEL[1:0] = 10 to 0x.

CS High Aborts SPI Communication but Doesn’t Stop Internal MCLK CS Internal MCLK Mode (no output) Validated SPI Mode 1,1 SCK Don’t Care 1 8 1 Continuous Clocking 8 1 8

SPI Mode 0,0 SCK PAD Direction SDI SDO Input Don’t Care High-Z Control Byte Write CLK_MODE = 10 (Int RC without output on pin SCK) Continuous Write Don’t Care High-Z STATUS Byte Control Byte STATUS Byte Reset MCLK MCLK Same as SCK MCLK Source

FIGURE 6-14:

DS20006414C-page 78 External = SCK Internal Only (no output)

MCP3465R Transition from CLK_SEL[1:0] = 0x to 10.

 2020-2021 Microchip Technology Inc.

MCP3465R

6.9.3 INTERNAL CLOCK MODE WITH

EXTERNAL AMCLK CLOCK

internally until a new command is launched (CS falling edge). In this case, the SCK is configured as the AMCLK output and always starts with a Logic Low state when it is at the CS falling edge transition. This mode is accessed by writing CLK_SEL[1:0] =

11. This mode defines the SCK pin as both the Serial Clock input and the Analog Master Clock (AMCLK) output. In regard to the MCLK clock domain, the SCK pin is an output pin that shows a continuous clock, AMCLK, generated by the internal oscillator. In regard to the SCK clock domain, the SCK pin is still the input pin for the digital interface. In this mode, the SCK and MCLK are equal and the device becomes a fully synchronous system.

To avoid bus contention errors, it is recommended to keep the SCK state to logic low, before having the first CS falling edge, after the writing of the CLK_SEL[1:0] bits in CONFIG0 (as shown in Figure 6-15). Considering that the internal oscillator starts at the CS falling edge after the SPI write (CLK_SEL[1:0] = 11), a settling time is necessary before being able to reach the internal oscillator nominal frequency. It is recommended not to launch conversions before this nominal clock frequency value has been established.

The MCU connected to the SPI port has to be configured to receive the SCK output and to generate synchronized commands with this output; it needs to be in SPI client mode. When this mode is enabled and running, the transitions on the CS pin do not impact the SCK output; AMCLK is always available on the SCK output even if CS is logic high.

The opposite transition, from CLK_SEL[1:0] = 11 to another clock mode, is described in Figure 6-16. This transition is also not immediate in order to allow a smooth transition from an SCK Output to an SCK Input mode. Considering that the SCK pin becomes an output in this clock mode, the transitions to and from this mode need special care in order to avoid bus contention errors on the SCK pin. The transition to this mode from another clock mode is detailed in Figure 6-15.

Writing the CLK_SEL[1:0] bits to ‘10’ or ‘0x’ resets the internal master clock immediately, but the SCK is still present as an output until CS sees a rising edge. After the CS rising edge, the SCK output is placed in a High-Impedance mode and the SCK becomes an output. The transition is not immediate; it does not occur as soon as the CLK_SEL[1:0] bits = 11 are written in the CONFIG0 register. This writing resets the master clock The master clock stays in Reset until the next CS falling edge is detected. As soon as this happens, the SCK can be used in the new selected mode.

Start the Int OSC CS Internal MCLK mode (output on SCK) Validated CS High Aborts SPI Communication but doesn’t Stop Internal MCLK T CLZ

Free-Running SCK Coming from Internal OSC SPI Mode 1,1 SCK Don’t Care 1 8 1 8 High-Z Continuous Clocking 1 8

SPI Mode 0,0 SCK PAD Direction SDI SDO Input Don’t Care High-Z MCLK FIGURE 6-15:

Control Byte Write CLK_MODE = 11 (Int with RC CLK output on pin

SCK)

Status Byte IF CLK_MODE = 0x • MCLK = SCK IF CLK_MODE = 10 • MCLK = Int RC OSC High-Z Continuous Write Don’t Care High-Z Output Control Byte Status Byte Reset MCLK MCP3465R Transition from CLK_SEL[1:0] = 0x/10 to ‘11’.

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MCP3465R

CS High Aborts SPI Communication but Doesn’t Stop Internal MCLK CS External or Internal Clock (no output) Mode Validated Free-Running SCK Coming from Internal OSC Max T CLZ SPI Mode 1,1 SCK 1 8 1 8 High-Z Cont.

Clocking 1 8

SPI Mode 0,0 SCK PAD Direction SDI SDO Output Don’t Care High-Z Control Byte STATUS Byte High-Z Write CLK_MODE = 0x (Ext CLK input on pin SCK)

or Write CLK_MODE = 10 (Int RC without output on pin SCK)

Continuous Write High-Z IF CLK_MODE = 0x => MCLK = SCK Reset MCLK DS20006414C-page 80 Control Byte STATUS Byte MCLK FIGURE 6-16:

Don’t Care Input IF CLK_MODE = 10 => MCLK = Int RC OSC MCP3465R Transition from CLK_SEL[1:0] = 11 to 0x/10.

 2020-2021 Microchip Technology Inc.

MCP3465R

7.0 BASIC APPLICATION CONFIGURATION

REFIN+/OUT pin for noise filtering and to provide more stability for the internal voltage reference (see Section 3.1 “Differential Reference Voltage Inputs: REFIN+/OUT, REFIN-”). The MCP3465R device can be used for various precision Analog-to-Digital Converter applications. The flexibility of its usage is given by the possibility of configuring the ADC to fit the required application.

7.1

The ADC can be used in Differential or Single-Ended mode due to the internal dual multiplexer (Figure 5-1). The user can select the input connection settings from the MUX register (Section 8.7 “Multiplexer (MUX) Register”) by using the different settings available on the positive and negative inputs of the ADC. The single-ended configuration is achieved by selecting A GND for the V IN - input of the ADC (MUX[3:0] = 1000) or by selecting any CHn input channel for V IN - and connecting the corresponding CHn input channel to A GND .

Typical Application for Absolute Voltage Measurement

The MCP3465R is able to measure the signal provided by sensors with absolute voltage output. For such applications, the MCP3465R typically uses its internal voltage reference. For the best performance, an external capacitor is recommended on the 3.3A 3.3D R1 5% 10 R2 5% 10 0603 0603 C1 0.1 μF R7 1k 0603 GNDA CH1 CH0 1 2 J1

Anti-Aliasing Filters

R8

1k

FIGURE 7-1:

0603 C7 0.1 μF 0603 GNDA GNDA 13 11 10 AV DD

DV DD DGND REFIN+ SCK

CS C6 0.1 μF 0603 SDI 6 10 μF 0603 U1 REFINCH0 C5 0603 C4 0.1 μF SDO CH1 3 AGND 0603 GND 5 2 12 1 GND EP GNDA GNDA 4 C3 0603 0.1 μF 0603 C2 0.1 μF 9 R3 10

8 R4 10

7 R5 10 R6 10 RG7/ADC_MISO

RG8/ADC_MOSI

RG6/ADC_SCK RG9/ADC_CS

MCP3465R

GNDA C8 0.1 μF 0603 MCP3465R Application Example.

 2020-2021 Microchip Technology Inc. DS20006414C-page 81

MCP3465R

7.1.1 HIGH-SIDE AND LOW-SIDE

CURRENT SENSING The ADC has the ability to perform differential measurements with an analog input Common-mode equal to or slightly larger than AV DD , or equal to or slightly lower than A GND (see the Electrical Characteristics table). A differential input structure and a Kelvin connection are required in order to achieve the most accurate measurements. An anti-aliasing filter is required to avoid aliasing of the oversampling frequency (DMCLK) back into the baseband of the input signal and possible corruption of the output data. Figure 7-1 provides an example of an anti-aliasing filter. For the measurement of voltages that can reach AV DD or a few mV higher, a gain setting of 0.33x is useful since it increases the input range to a 3 x V REF value, so a 1.2V V REF will allow a theoretical input range of 3.6V. However, the maximum voltage that can be measured is always bounded by AV DD + 0.1V in order to limit excess leakage current at the input pins created by the ESD structures. Therefore, in order to properly measure 3.6V with a 1.2V voltage reference, it is recommended to use an AV DD supply voltage as close as possible to 3.6V.

7.1.2 THERMOCOUPLE CONNECTION One of the most used temperature transducers in the industry is the thermocouple. Thermocouples provide a voltage dependent on the temperature difference between cold junction and hot junction. This voltage is in the order of magnitude of tens of µV/°C, which requires amplification that can be provided by the internal gain stage of the ADC.

7.2 Typical Application for Ratiometric Voltage Measurement

A wide range of sensors provides an output voltage directly related to the power supply of the sensors. These sensors are known as ratiometric output. These sensors often have a Wheatstone bridge structure, such as pressure sensors or load cells (Figure 7-3).

R 1 RTD V IN + Input Signal REFIN+/OUT MCP3465R

V IN - REFINFIGURE 7-3: Wheatstone Bridge Ratiometric Connection.

Others act as a single resistor with a value dependent on temperature (pure metal resistance thermometer RTD and negative temperature coefficient resistor NTC). To accurately measure the signal from these sensors, REFIN+/OUT is usually connected to the same power supply of the sensor (Figure 7-4), as long as this respects the specified voltage range on the REFIN+/OUT pin (see the Electrical Characteristics table.

R 2 Sensor V IN +

Anti-Aliasing

Filter REFIN+/OUT MCP3465R

V IN - REFIN-

R 1

C 1 FIGURE 7-4:

FIGURE 7-2:

C 2 A GND D GND RTD Ratiometric Connection.

Thermocouple Connection. The connection of the thermocouple to the ADC requires minimal extra components. A differential input structure is recommended. The cold junction can be measured by using a digital temperature sensor, such as MCP9804, connected to the MCU. If high accuracy is not required, the cold junction temperature can be estimated directly with the internal temperature sensor of the ADC (see Figure 7-2).

DS20006414C-page 82  2020-2021 Microchip Technology Inc.

MCP3465R

7.3 Power Supply Design and Bypassing

The split between analog and digital can be done under the device, and AV DD and DV DD can be connected with lines coming under the ground plane. The two separate return paths will eventually share a unique connection point (star connection) in order to minimize coupling between the two power supply domains.

In any system, the analog ICs (such as references or operational amplifiers) are always connected to the analog ground plane. The MCP3465R should also be considered a sensitive analog component and connected to the analog ground plane. The ADC features two pairs of power supply voltage pins: A GND and AV DD , D GND and DV DD . For best performance, it is recommended to keep the two pairs of pins connected to two different networks (see Figure 7-5), so that the design will feature two ground traces and two power supplies (see Figure 7-6).

Another possibility, sometimes easier to implement in terms of PCB layout, is to consider the MCP3465R as an analog component, and connect AV DD to DV DD and A GND to D GND with a star connection. In this scheme, the decoupling capacitors may be larger due to the ripple on the digital power supply (caused by the digital filters and the SPI interface of the MCP3465R), now causing glitches on the analog power supply. The analog circuitry (including MCP3465R) and the digital circuitry (MCU) should have separate power supplies and return paths to the external ground reference, as described in Figure 7-5. An example of a typical power supply circuit, with different paths for analog and digital return currents, is shown in Figure 7-6. A possible split example is shown in Figure 7-7, where the ground star connection can be located underneath the device with the exposed pad.

Figure 7-6 shows an example of a power supply schematic with separate DV DD and AV DD . A high-current LDO (MCP1825) was used for the DV DD line to be able to power the MCU and other peripherals attached to the MCU. A high PSRR LDO (MCP1754) is used for the AV DD that goes to the ADC and a few other components sensitive to noise. The Net Tie is used to separate D GND from A GND .

I D I A 0.1 ȝF C 0.1 ȝF

V D V A AV

DD DV DD MCP365 MCU

D GND A GND

I A I D

“Star” Point D - = A - =

FIGURE 7-5: Separating Digital and Analog Ground by Using a Star Connection.

VIN VOUT 3 C44 10 μF 5V_USB C15 10 μF TANT-B GND VOUT 2

+5V USB +9V IN

VIN VOUT C14 0.1 μF 0603 GND

GND 1 U3 MCP1754-3.3V GND GND 3 3.3A 2 VIN 3 1

4 2 3

GND D1

MRA4005 GND TANT-B J9 1 1 3 2 Power Jack 2.5 mm U4 LM1117-5V GND 9V

J10 C10 0.1 μF TANT-B

0603 GND GND 3.3D

C45 10 μF C11 0.1 μF 0603 2 1 U2 MCP1825S-3.3V

GND 5V Net Tie GND GNDA GNDA C12 0.1 μF 0603

GNDA GNDA C13 10 μF TANT-B GNDA

FIGURE 7-6: Power Supply with Separate Lines for Analog and Digital Sections (the “Net Tie” Object Represents the Star Ground Connection).

 2020-2021 Microchip Technology Inc. DS20006414C-page 83

MCP3465R

DV

DD

DGND A GND 1

AV

DD

7.4

12 11 10 EP 13 5 6 CS 7 SCK

4

CH0 REFIN+ 3 8 SDI CH1 REFIN- 2 9 SDO

FIGURE 7-7: Separation of Analog and Digital Circuits on the Layout (Shown on the UQFN Package). When remote sensors are used to reduce the sensitivity to external influences, such as EMI, the wires that connect the sensor to the ADC should form a twisted pair. Ferrite beads can be used between the digital and analog ground planes to keep high-frequency noise from entering the device. A low-resistance ferrite bead is recommended.

DS20006414C-page 84

SPI Interface Digital Crosstalk

The MCP3465R device incorporates a high-speed 20 MHz SPI digital interface. This interface can induce crosstalk, especially with the outer channels closer to the SPI digital pins (for example, CH7), if it is run at full speed without any precautions. The crosstalk is caused by the switching noise created by the digital SPI signals. This crosstalk would negatively impact the SNR in this case. The noise is attenuated if proper separation between the analog and the digital power supplies is put in place (see Section 7.3 “Power Supply Design and Bypassing”). In order to further remove the influence of the SPI communication on measurement accuracy, it is recommended to add series resistors on the SPI lines to reduce the current spikes caused by the digital switching noise (see Figure 7-1 where these resistors have been implemented). The resistors also help to keep the level of electromagnetic emissions low. The switching noise is also a linear function of the DV DD supply voltage. In order to further reduce the influence of the switching noise caused by SPI transmissions, the DV DD digital power supply voltage should be kept at as a low value as possible. The measurement graphs provided in this MCP3465R data sheet have been performed with 10 series resistors connected on each SPI I/O pin. Measurement accuracy disturbances have not been observed, even at 20 MHz interfacing.

 2020-2021 Microchip Technology Inc.

MCP3465R

8.0 INTERNAL REGISTERS

The MCP3465R has a total of 16 internal registers made of volatile memory. Table 8-1 includes a summary of the registers. These registers are sequentially accessible. 3 TABLE 8-1: INTERNAL REGISTERS SUMMARY Address Register Name No. of Bits R/W Description

MCP3465R

8.1 ADCDATA REGISTER

Name Bits Address Cof ADCDATA 4/16/32 0x0 R

REGISTER 8-1: ADCDATA: ADC CHANNEL DATA OUTPUT REGISTER

R-0 ADCDATA[15:0] bit 23 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-0 x = Bit is unknown ADCDATA[15:0]: ADC Output Code The data are post-calibration if the EN_OFFCAL or EN_GAINCAL bits are enabled. The data can be formatted in 16/32-bit modes depending on the DATA_FORMAT[1:0] settings (see Section 5.6 “ADC Output Data Format”). The ADC Channel Data Output registers always contain the most recent A/D conversion data. The register is updated at each data ready internal signal (it depends on the OSR and CONV_MODE settings). The register is latched at the start of each SPI Read command. The register is double buffered to avoid data loss. There is a small time delay, t DODR , after each data ready, where the user has to wait for the data to be available; otherwise, data corruption can occur (when the internal data are refreshed). When EN_MDAT = 1, this register becomes a 4-bit wide register containing the MDAT output codes, which are the outputs of the modulator that are represented by four comparator outputs (COMP[3:0], see Section 5.4.2 “Modulator Output Block”).

DS20006414C-page 86  2020-2021 Microchip Technology Inc.

MCP3465R

8.2 CONFIG0 REGISTER

Name Bits Address Cof CONFIG0 8 0x1 R/W

REGISTER 8-2: CONFIG0 REGISTER

1 = Internal voltage reference is selected and buffered internally; the REFIN+/OUT pin voltage is set

at 2.4V (default) 0 = External voltage reference is selected and not buffered internally; the internal voltage reference

buffer is shut down bit 6 CONFIG0[6]: If CONFIG0 = 0x0, the device goes into Partial Shutdown mode.

This bit does not have any other function. bit 5-4 CLK_SEL[1:0]: Clock Selection

11 = Internal clock is selected and AMCLK is present on the SCK pin, which becomes an output pin 10 = Internal clock is selected and no clock output is present on the SCK pin, in which case, the SCK

pin becomes the SPI clock input pin only 01 = External digital clock; in this mode, SCK = MCLK and the clock input pin is SCK (MCLK needs to

be sent continuously to ensure proper functioning of A/D conversions) 00 = External digital clock (default); in this mode, SCK = MCLK and the clock input pin is SCK (MCLK

needs to be sent continuously to ensure proper functioning of A/D conversions) bit 3-2 CS_SEL[1:0]: Current Source/Sink Selection for Sensor Bias (source on V IN +/Sink on V IN -)

11 = 15 µA is applied to the ADC inputs 10 = 3.7 µA is applied to the ADC inputs 01 = 0.9 µA is applied to the ADC inputs 00 = No current source is applied to the ADC inputs (default) bit 1-0 ADC_MODE[1:0]: ADC Operating Mode Selection

11 = ADC Conversion mode 10 = ADC Standby mode 01 = ADC Shutdown mode 00 = ADC Shutdown mode (default)

 2020-2021 Microchip Technology Inc. DS20006414C-page 87

MCP3465R

8.3 CONFIG1 REGISTER

Name Bits Address Cof CONFIG1 8 0x2 R/W

REGISTER 8-3:

R/W-0

CONFIG1: CONFIGURATION REGISTER 1

00 = AMCLK = MCLK (default) bit 5-2 OSR[3:0]: Oversampling Ratio for Delta-Sigma A/D Conversion

bit 1-0 RESERVED[1:0]: Must remain set to ‘00’ DS20006414C-page 88 x = Bit is unknown  2020-2021 Microchip Technology Inc.

MCP3465R

8.4 CONFIG2 REGISTER

Name Bits Address Cof CONFIG2 8 0x3 R/W

REGISTER 8-4:

R/W-1

CONFIG2: CONFIGURATION REGISTER 2

11 = ADC channel has current x 2 10 = ADC channel has current x 1 (default) 01 = ADC channel has current x 0.66 00 = ADC channel has current x 0.5 bit 5-3 GAIN[2:0]: ADC Gain Selection

bit 2 AZ_MUX: Auto-Zeroing MUX Setting

1 = ADC auto-zeroing algorithm is enabled; this setting multiplies the conversion time by two and

does not allow Continuous Conversion mode operation (which is then replaced by a series of consecutive One-Shot mode conversions) 0 = Analog input multiplexer auto-zeroing algorithm is disabled (default). bit 1 AZ_REF: Auto-Zeroing Reference Buffer Setting

1 = Internal voltage reference buffer chopping algorithm is enabled; this setting has no effect when

external voltage reference is selected (VREF_SEL = 0) (default) 0 = Internal voltage reference buffer chopping auto-zeroing algorithm is disabled bit 0 RESERVED: Must remain set to ‘1’  2020-2021 Microchip Technology Inc. DS20006414C-page 89

MCP3465R

8.5 CONFIG3 REGISTER

Name Bits Address Cof CONFIG3 8 0x4 R/W

REGISTER 8-5:

R/W-0 R/W-0 CONV_MODE[1:0]

CONFIG3: CONFIGURATION REGISTER 3

11 = Continuous Conversion mode or continuous conversion cycle in Scan mode 10 = One-shot conversion or one-shot cycle in Scan mode; it sets ADC_MODE[1:0] to ‘10’ (standby) at

the end of the conversion or at the end of the conversion cycle in Scan mode 0x = One-shot conversion or one-shot cycle in Scan mode; it sets ADC_MODE[1:0] to ‘0x’ (ADC

shutdown) at the end of the conversion or at the end of the conversion cycle in Scan mode (default) bit 5-4 DATA_FORMAT[1:0]: ADC Output Data Format Selection

11 = 32-bit (17-bit right justified data + Channel ID): CHID[3:0] + SGN extension (12 bits) + 16-bit ADC

data; it allows overrange with the SGN extension 10 = 32-bit (17-bit right justified data): SGN extension (8-bit) + 16-bit ADC data; it allows overrange with

the SGN extension 01 = 32-bit (16-bit left justified data): 16-bit ADC data + 0x0000 (16-bit); it does not allow overrange (ADC

code locked to 0xFFFF or 0x8000) 00 = 16-bit (default ADC coding): 16-bit ADC data; it does not allow overrange (ADC code locked to

0xFFFF or 0x8000) bit 3 CRC_FORMAT: CRC Checksum Format Selection on Read Communications

(it does not affect CRCCFG coding) 1 = 32-bit wide (CRC-16 followed by 16 zeros)

bit 2 EN_CRCCOM: CRC Checksum Selection on Read Communications

(it does not affect CRCCFG calculations) 1 = CRC on communications enabled 0 = CRC on communications disabled (default) bit 1 EN_OFFCAL: Enable Digital Offset Calibration

bit 0 EN_GAINCAL: Enable Digital Gain Calibration

DS20006414C-page 90  2020-2021 Microchip Technology Inc.

MCP3465R

8.6 IRQ REGISTER

Name Bits Address Cof IRQ 8 0x5 R/W

REGISTER 8-6:

U-0 — R-1

IRQ: INTERRUPT REQUEST REGISTER

R-1 R-1 R/W-0 DR_STATUS CRCCFG_STATUS POR_STATUS EN_MDAT U-1 R/W-1 U-1 — EN_FASTCMD — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 Unimplemented: Read as ‘0’ bit 6 DR_STATUS: Data Ready Status Flag

1 = ADCDATA has not been updated since the last reading or last Reset (default) 0 = New ADCDATA ready for reading bit 5 CRCCFG_STATUS: CRC Error Status Flag for Internal Registers

1 = CRC error has not occurred for the Configuration registers (default) 0 = CRC error has occurred for the Configuration registers bit 4 POR_STATUS: POR Status Flag

1 = POR has not occurred since the last reading (default) 0 = POR has occurred since the last reading bit 3 EN_MDAT: Modulator Output Data Enable

1 = Places modulator output on the ADCDATA register, which then becomes a 4-bit register, which reads

COMP[3:0] 0 = Modulator output is not provided; ADCDATA shows the ADC output after decimation filter bit 2 Unimplemented: Read as ‘1’ bit 1 EN_FASTCMD: Enable Fast Commands in the COMMAND Byte

1 = Fast commands are enabled (default) 0 = Fast commands are disabled bit 0 Unimplemented: Read as ‘1’  2020-2021 Microchip Technology Inc. DS20006414C-page 91

MCP3465R

8.7 MULTIPLEXER (MUX) REGISTER

Name Bits Address Cof MUX 8 0x6 R/W

REGISTER 8-7:

R/W-0

MUX: MULTIPLEXER REGISTER

1110 = Internal Temperature Sensor Diode M (Temp Diode M) (1) 1101 = Internal Temperature Sensor Diode P (Temp Diode P) (1)

1010 = Reserved (do not use)

0111 = Reserved (do not use) 0110 = Reserved (do not use) 0101 = Reserved (do not use) 0100 = Reserved (do not use) 0011 = Reserved (do not use) 0010 = Reserved (do not use)

Bit 3-0 MUX_VIN-[3:0]: Input Selection (2)

1110 = Internal Temperature Sensor Diode M (Temp Diode M) (1) 1101 = Internal Temperature Sensor Diode P (Temp Diode P) (1)

1010 = Reserved (do not use)

0111 = Reserved (do not use) 0110 = Reserved (do not use) 0101 = Reserved (do not use) 0100 = Reserved (do not use) 0011 = Reserved (do not use) 0010 = Reserved (do not use)

Note 1:

2:

x = Bit is unknown Selects the internal temperature sensor diode and forces a fixed current through it. For a correct temperature reading, the MUX[7:0] selection should be equal to 0xDE. The codes, ‘1010/0111/0110/0101/0100/0011/0010’, correspond to a floating input and should be avoided.

DS20006414C-page 92  2020-2021 Microchip Technology Inc.

MCP3465R

8.8 SCAN REGISTER

Name Bits Address Cof SCAN 24 0x7 R/W

REGISTER 8-8:

R/W-0

SCAN: SCAN MODE SETTINGS REGISTER

R/W-0 R/W-0 DLY[2:0] R/W-0 U-0 RESERVED — bit 23 bit 16 R/W-0 R/W-0 R/W-0 R/W-0 OFFSET VCM AV DD TEMP R/W-0 R/W-0 R/W-0 R/W-0 RESERVED RESERVED RESERVED SCAN_DIFF_CHA bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED R/W-0 SCAN_SE_CH[1:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Bit 23-21 DLY[2:0]: Delay Time (T DLY_SCAN ) Between Each Conversion During a Scan Cycle

Bit 20 RESERVED: Must remain set to ‘0’ Bit 19-16 Unimplemented: Read as ‘0’ Bit 15-12 SCAN Channel Selection (see Table 5-15 for a complete description) Bit 11-9 RESERVED: Must remain set to ‘000’ Bit 8 SCAN Channel Selection (see Table 5-15 for a complete description) Bit 7-2 RESERVED: Must remain set to ‘000000’ Bit 1-0 SCAN Channel Selection (see Table 5-15 for a complete description)

 2020-2021 Microchip Technology Inc. DS20006414C-page 93

MCP3465R

8.9 TIMER REGISTER

Name Bits Address Cof TIMER 24 0x8 R/W

REGISTER 8-9: TIMER: TIMER DELAY VALUE REGISTER

R/W-0 TIMER[15:0] bit 23 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Bit 23-0 x = Bit is unknown TIMER[15:0]: Selection Bits for the Time Interval (T TIMER_SCAN ) Between Two Consecutive Scan Cycles

0xFFFF: T TIMER_SCAN = 16777215 * DMCLK periods 0xFFFFFE: T TIMER_SCAN = 16777214 * DMCLK periods • • • 0x000002: T TIMER_SCAN = 2 * DMCLK periods 0x000001: T TIMER_SCAN = 1 * DMCLK periods

DS20006414C-page 94  2020-2021 Microchip Technology Inc.

MCP3465R

8.10 OFFSETCAL REGISTER

Name Bits Address Cof OFFSETCAL 24 0x9 R/W

REGISTER 8-10: OFFSETCAL: OFFSET CALIBRATION REGISTER

R/W-0 OFFSETCAL[23:16] bit 23 bit 16 R/W-0 OFFSETCAL[15:8] bit 15 bit 8 RW-0 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Bit 23-8 OFFSETCAL[23:8]: Offset Error Digital Calibration Code (two’s complement, MSb first coding)

See Section 5.13 “Digital System Offset and Gain Calibrations”. Bit 7-0 Unimplemented[7:0]: Don’t care as OFFCAL[23:0] is internally truncated to the 16 MSbs

Default value is 0x00.

 2020-2021 Microchip Technology Inc. DS20006414C-page 95

MCP3465R

8.11 GAINCAL REGISTER

Name Bits Address Cof GAINCAL 24 0xA R/W REGISTER 8-11: GAINCAL: GAIN CALIBRATION REGISTER

R/W-1 R/W-0

GAINCAL[23:16] bit 23 bit 16 R/W-0 GAINCAL[15:8] bit 15 bit 8 RW-0 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Bit 23-8 GAINCAL[23-8]: Gain Error Digital Calibration Code (unsigned, MSb first coding)

The GAINCAL default value is 800000, which provides a gain of 1x. See Section 5.13 “Digital System Offset and Gain Calibrations”. Bit 7-0 Unimplemented[7:0]: Don’t care as GAINCAL[23:0] is internally truncated to the 16 MSbs

Default value is 0x00.

DS20006414C-page 96  2020-2021 Microchip Technology Inc.

MCP3465R

8.12 RESERVED REGISTER

Name Bits Address Cof RESERVED 24 0xB R/W REGISTER 8-12: RESERVED REGISTER

8.13

x = Bit is unknown RESERVED[15:0]: Must remain set to 0x900000

RESERVED REGISTER

Name Bits Address Cof RESERVED 8 0xC R/W REGISTER 8-13: RESERVED REGISTER

R/W-0x30 RESERVED[7:0] bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Bit 7-0 x = Bit is unknown RESERVED[7:0]: Must remain set to 0x30  2020-2021 Microchip Technology Inc. DS20006414C-page 97

MCP3465R

8.14 LOCK REGISTER

Name Bits Address Cof LOCK 8 0xD R/W

REGISTER 8-14:

R/W-1 LOCK: SPI WRITE MODE LOCKING PASSWORD VALUE REGISTER

8.15

x = Bit is unknown LOCK[7:0]: Write Access Password Entry Code 0xA5 = Write access is allowed on the full register map. CRC on register map values is not calculated

Any code, except 0xA5 = Write access is not allowed on the full register map. Only the LOCK register is writable. CRC on register map is calculated continuously only when DMCLK is running.

RESERVED REGISTER

Name Bits Address Cof RESERVED 16 0xE R/W REGISTER 8-15: RESERVED REGISTER

R/W (0x000E) RESERVED[15:0] bit 15 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Bit 15-0 x = Bit is unknown RESERVED[15:0]: Must remain set to 0x000A DS20006414C-page 98  2020-2021 Microchip Technology Inc.

MCP3465R

8.16 CRCCFG REGISTER

Name Bits Address Cof CRCCFG 16 0xF R

REGISTER 8-16: CRCCFG: CRC CONFIGURATION REGISTER

R-0 CRCCFG[15:0] bit 15 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Bit 15-0 x = Bit is unknown CRCCFG[15:0]: CRC-16 Checksum Value CRC-16 checksum is continuously calculated internally based on the register map configuration settings when the device is locked (LOCK[7:0] ≠ 0xA5).

 2020-2021 Microchip Technology Inc. DS20006414C-page 99

MCP3465R

NOTES:

DS20006414C-page 100  2020-2021 Microchip Technology Inc.

MCP3465R

9.0 PACKAGING INFORMATION 9.1 Package Marking Information (*)

12-Lead UQFN (2 mm x 2 mm x 0.55 mm) Example:

465R 0256

Part Number Code SPI Device Address MCP3465RT-E/SFX 46R 01 (1) Note 1: Denotes the device default SPI address option.

The device only responds to SPI commands if CMD[7:6] match the SPI device address for each command (see Section 6.2.2, Device Address Bits (CMD[7:6])). Contact Microchip Sales for other device address option ordering procedures.

Assembled/Packaged Before: 9/15/2020 XXX

NNN (1) Assembled/Packaged After: 9/15/2020 XXXX

YNNN (2) Note 1: NNN is the alphanumeric traceability code.

2: is the last digit of the year (e.g., 0NNN for

2020. and NNN is the alphanumeric traceability code.

Legend: XX...X

YYY WW NNN e 3 * * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e 3 ) can be found on the outer packaging for this package.

In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.

 2020-2021 Microchip Technology Inc. DS20006414C-page 101

MCP3465R

12-Lead Ultra Thin Plastic Quad Flat, No Lead Package (SFX) - 2x2 mm Body [UQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging D NOTE 1 A B N 1 E 2 (DATUM B) (DATUM A) 2X

0.10 C 2X

0.10 C TOP VIEW

0.10 C

A1 C A SEATING

PLANE 12X

(A3) 0.08 C

SIDE VIEW

0.10 C A B D2 0.10 C A B E2 2 1

KNOTE 1

N

BOTTOM VIEW

Microchip Technology Drawing C04-438A Sheet 1 of 2 DS20006414C-page 102  2020-2021 Microchip Technology Inc.

MCP3465R

12-Lead Ultra Thin Plastic Quad Flat, No Lead Package (SFX) - 2x2 mm Body [UQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging Units Dimension Limits Number of Terminals N e Pitch Overall Height A Standoff A1 A3 Terminal Thickness Overall Length D Exposed Pad Length D2 Overall Width E E2 Exposed Pad Width b Terminal Width Terminal Length L K Terminal-to-Exposed-Pad MIN 0.50 0.00 0.82 0.82 0.15 0.24 0.25 MILLIMETERS

NOM 12 0.40 BSC

0.55 0.02 0.152 REF 2.00 BSC

0.92 2.00 BSC

0.92 0.20 0.29

• MAX 0.60 0.05 1.02 1.02 0.25 0.34

• Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-438A Sheet 2 of 2  2020-2021 Microchip Technology Inc. DS20006414C-page 103

MCP3465R

12-Lead Ultra Thin Plastic Quad Flat, No Lead Package (SFX) - 2x2 mm Body [UQFN]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging C1

X2 12 ØV 1

C2 Y2 2 G1 Y1 X1

SILK SCREEN

E

RECOMMENDED LAND PATTERN

Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X12) X1 Contact Pad Length (X12) Y1 Contact Pad to Center Pad (X12) G1 Thermal Via Diameter EV MIN MILLIMETERS

NOM 0.40 BSC MAX 1.00 1.00 2.10 2.10

0.20 0.70 0.20

0.30 Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during

reflow process Microchip Technology Drawing C04-2438A DS20006414C-page 104  2020-2021 Microchip Technology Inc.

MCP3465R

APPENDIX A: REVISION HISTORY Revision C (April 2021)

• Updated references to Effective Resolution

throughout the document. • Minor editorial corrections.

Revision B (March 2021)

The following is the list of modifications: • Corrected Table 5-11 • Corrected Register 8-2

Note: The SPI standard uses the terminology

“Master” and “Slave”. The equivalent Microchip terminology used in this document is “Host” and “Client”, respectively.

Revision A (September 2020)

• Initial release of this document  2020-2021 Microchip Technology Inc. DS20006414C-page 105

MCP3465R

NOTES:

 2020-2021 Microchip Technology Inc. DS20006414C-page 106

MCP3465R

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office .

PART NO. X (1) X /XXX

Device Tape and

Reel Temperature

Range Package Device: MCP3465R:

Examples: a) MCP3465RT-E/SFX: Two-Channel ADC,

Tape and Reel, Extended Temperature, 12-Lead UQFN.

Two-Channel, 153.6 ksps, Low Noise 16-Bit Delta-Sigma ADC with Internal Voltage Reference

Note

Tape and Reel: T = Tape and Reel

Blank = Standard packaging (tube or tray)

Temperature Range:

EPackage: SFX = Ultra Small, No Lead Package (UQFN),

2 mm x 2 mm x 0.55 mm, 12-Lead

 2020-2021 Microchip Technology Inc.

1: Tape and Reel identifier only appears in the

catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2: Device SPI Address ‘01’ is the default

address option. Contact Microchip Sales for other device address option ordering procedure.

DS20006414C-page 107

MCP3465R

NOTES:

DS20006414C-page 108  2020-2021 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specifications contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.

• There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip

devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished without violating Microchip's intellectual property rights.

• Microchip is willing to work with any customer who is concerned about the integrity of its code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not

mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Information regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications.

THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.

IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.

Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, QuietWire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies.

© 2020-2021, Microchip Technology Incorporated, All Rights Reserved. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.

 2020-2021 Microchip Technology Inc.

ISBN: 978-1-5224-8132-4 DS20006414C-page 109

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02/28/20