stm32h7r3a8

⬇ Download Markdown · ⬇ Download LaTeX · ⬇ original · view original · CSV: table 1, table 2, table 3, table 4, table 5, table 6, table 7, table 8, table 9, table 10, table 11, table 12, table 13, table 14, table 15, table 16, table 17, table 18, table 19, table 20, table 21, table 22, table 23, table 24, table 25, table 26, table 27, table 28, table 29, table 30, table 31, table 32, table 33, table 34, table 35, table 36, table 37, table 38, table 39, table 40, table 41, table 42, table 43, table 44, table 45, table 46, table 47, table 48, table 49, table 50, table 51, table 52, table 53, table 54, table 55, table 56, table 57, table 58, table 59, table 60, table 61, table 62, table 63, table 64, table 65, table 66, table 67, table 68, table 69, table 70, table 71, table 72, table 73, table 74, table 75, table 76, table 77, table 78, table 79, table 80, table 81, table 82, table 83, table 84, table 85, table 86, table 87, table 88, table 89, table 90, table 91, table 92, table 93, table 94, table 95, table 96, table 97, table 98, table 99, table 100, table 101, table 102, table 103, table 104, table 105, table 106

Table 1 (pages 34–41)

Table 1 · 7 columns × 215 rows · p.34–41 · CSV

Peripherals	Clock types	Clock sources	Kernel clock MUX		Max Kernel clock freq. [MHz](1)	Type (2)(3)
Peripherals	Clock types	Clock sources	Pos.	Control field	Max Kernel clock freq. [MHz](1)	Type (2)(3)
ADF	Kernel	hclk1	0(4)	ADF1SEL	FMAX / 2	A
ADF	Kernel	pll2_p_ck	1	ADF1SEL	FMAX / 2	A
ADF	Kernel	pll3_p_ck	2	ADF1SEL	FMAX / 2	A
ADF	Kernel	I2S_CKIN	3	ADF1SEL	FMAX / 2	A
ADF	Kernel	csi_ker_ck	4	ADF1SEL	FMAX / 2	A
ADF	Kernel	hsi_ker_ck	5	ADF1SEL	FMAX / 2	A
ADF	Bus	hclk1	-	-	FMAX / 2	-
ADC12	Kernel	pll2_p_ck	0(4)	ADCSEL	125	A
ADC12	Kernel	pll3_r_ck	1	ADCSEL	125	A
ADC12	Kernel	per_ck	2	ADCSEL	125	A
ADC12	Bus	hclk1	-	-	FMAX / 2	-
CORDIC	Bus	hclk2	-	-	FMAX / 2	-
CRC	Bus	hclk4	-	-	FMAX / 2	-
CRS	Bus	pclk1	-	-	FMAX / 4	-
DBG	Bus	sys_bus_ck	-	-	FMAX / 2	-
DBG	kernel	sys_cpu_ck/3	-	-	FMAX / 3	-
DB_OCSPI1. DB_OCSPI2	Bus	hclk5	-	-	FMAX / 2	-
DB_SDMMC1	Bus	hclk5	-	-	FMAX / 2	-
DB_SDMMC2	Bus	hclk2	-	-	FMAX / 2	-
DCMIPP	Bus	aclk	-	-	FMAX / 2	-
DCMIPP	Bus	pclk5			FMAX / 4
GPDMA1	Bus	hclk1	-	-	FMAX / 2	-
HPDMA1	Bus	hclk5	-	-	FMAX / 2	-
HPDMA1	Bus	aclk	-	-	FMAX / 2	-
DMA2D	Bus	hclk5	-	-	FMAX / 2	-
DMA2D	Bus	aclk	-	-	FMAX / 2	-
ETH1	Kernel	ETH_MII_TX_CLK	-	-	25	A
ETH1	Kernel	ETH_MII_TX_CLK/. ETH_RMII_REF_CLK	0(4)	ETH1REFCKSEL	25	A
ETH1	Kernel	hse_ker_ck	1	ETH1REFCKSEL	25	A
ETH1	Kernel	eth_clk_fb	2	ETH1REFCKSEL	25	A
ETH1	Kernel	hse_ker_ck	0(4)	ETH1PHYCKSEL	50	A
ETH1	Kernel	pll3_s_ck	1	ETH1PHYCKSEL	50	A
ETH1	Kernel	clk_ptp_ref_i		-	FMAX / 2	-
ETH1	Bus	hclk1	-	-	FMAX / 2	-
EXTI	Bus	pclk4	-	-	FMAX / 4	-
FLASH	Bus	hclk5	-	-	FMAX / 2	-
FDCAN	Kernel	hse_ker_ck	0(4)	FDCANSEL	125	A
FDCAN	Kernel	pll1_q_ck	1	FDCANSEL	125	A
FDCAN	Kernel	pll2_p_ck	2	FDCANSEL	125	A
FDCAN	Bus	pclk1	-	-	FMAX / 4	-
FMC	Kernel	hclk5	0(4)	FMCSEL	FMAX / 2	A
FMC	Kernel	pll1_q_ck	1	FMCSEL	FMAX / 2	A
FMC	Kernel	pll2_r_ck	2	FMCSEL	FMAX / 2	A
FMC	Kernel	hsi_ker_ck	3	FMCSEL	FMAX / 2	A
FMC	Bus	hclk5	-	-	FMAX / 2	-
FMC	Bus	aclk		-	FMAX / 2	-
GPIOA-H. GPIOM-P	Bus	hclk4	-	-	FMAX / 2	-
GPU2D	Bus	hclk5	-	-	FMAX / 2	-
GPU2D	Bus	aclk	-	-	FMAX / 2	-
GFXMMU	Bus	hclk5	-	-	FMAX / 2	-
GFXMMU	Bus	aclk	-	-	FMAX / 2	-
GFXTIM	Bus	pclk5	-	-	FMAX / 4	-
HASH	Bus	hclk3	-	-	FMAX / 2	-
HDMI-CEC	Kernel	lse_ck	0(4)	CECSEL	1	-
HDMI-CEC	Kernel	lsi_ck	1	CECSEL	1	-
HDMI-CEC	Kernel	csi_ker_ck/122	2	CECSEL	1	-
HDMI-CEC	Bus	pclk1	-	-	FMAX / 4	-
I2C2, I2C3	Kernel	pclk1	0(4)	I2C23SEL	FMAX / 4	A
I2C2, I2C3	Kernel	pll3_r_ck	1	I2C23SEL	FMAX / 4	A
I2C2, I2C3	Kernel	hsi_ker_ck	2	I2C23SEL	FMAX / 4	A
I2C2, I2C3	Kernel	csi_ker_ck	3	I2C23SEL	FMAX / 4	A
I2C2, I2C3	Bus	pclk1	-	-	FMAX / 4	-
I2C1/I3C1	Kernel	pclk1	0(4)	I2C1_I3C1SEL	FMAX / 4	A
I2C1/I3C1	Kernel	pll3_r_ck	1	I2C1_I3C1SEL	FMAX / 4	A
I2C1/I3C1	Kernel	hsi_ker_ck	2	I2C1_I3C1SEL	FMAX / 4	A
I2C1/I3C1	Kernel	csi_ker_ck	3	I2C1_I3C1SEL	FMAX / 4	A
I2C1/I3C1	Bus	pclk1	-	-	FMAX / 4	-
XSPIM	Bus	hclk5	-	-	FMAX / 2	-
IWDG	Kernel	lsi_ck	-	-	1	A
IWDG	Bus	pclk4	-	-	FMAX / 4	-
JPEG	Bus	hclk5	-	-	FMAX / 2	-
LPTIM1	Kernel	pclk1	0(4)	LPTIM1SEL	FMAX / 4	A
LPTIM1	Kernel	pll2_p_ck	1	LPTIM1SEL	FMAX / 4	A
LPTIM1	Kernel	pll3_r_ck	2	LPTIM1SEL	FMAX / 4	A
LPTIM1	Kernel	lse_ck	3	LPTIM1SEL	FMAX / 4	A
LPTIM1	Kernel	lsi_ck	4	LPTIM1SEL	FMAX / 4	A
LPTIM1	Kernel	per_ck	5	LPTIM1SEL	FMAX / 4	A
LPTIM1	Bus	pclk1	-	-	FMAX / 4	-
LPTIM2, LPTIM3	Kernel	pclk4	0(4)	LPTIM23SEL	FMAX / 4	A
LPTIM2, LPTIM3	Kernel	pll2_p_ck	1	LPTIM23SEL	FMAX / 4	A
LPTIM2, LPTIM3	Kernel	pll3_r_ck	2	LPTIM23SEL	FMAX / 4	A
LPTIM2, LPTIM3	Kernel	lse_ck	3	LPTIM23SEL	FMAX / 4	A
LPTIM2, LPTIM3	Kernel	lsi_ck	4	LPTIM23SEL	FMAX / 4	A
LPTIM2, LPTIM3	Kernel	per_ck	5	LPTIM23SEL	FMAX / 4	A
LPTIM2, LPTIM3	Bus	pclk4	-	-	FMAX / 4	-
LPTIM4, LPTIM5	Kernel	pclk4	0(4)	LPTIM45SEL	FMAX / 4	A
LPTIM4, LPTIM5	Kernel	pll2_p_ck	1	LPTIM45SEL	FMAX / 4	A
LPTIM4, LPTIM5	Kernel	pll3_r_ck	2	LPTIM45SEL	FMAX / 4	A
LPTIM4, LPTIM5	Kernel	lse_ck	3	LPTIM45SEL	FMAX / 4	A
LPTIM4, LPTIM5	Kernel	lsi_ck	4	LPTIM45SEL	FMAX / 4	A
LPTIM4, LPTIM5	Kernel	per_ck	5	LPTIM45SEL	FMAX / 4	A
LPTIM4, LPTIM5	Bus	pclk4	-	-	FMAX / 4	-
LPUART1	Kernel	pclk4	0(4)	LPUART1SEL	FMAX / 4	A
LPUART1	Kernel	pll2_q_ck	1	LPUART1SEL	FMAX / 4	A
LPUART1	Kernel	pll3_q_ck	2	LPUART1SEL	FMAX / 4	A
LPUART1	Kernel	hsi_ker_ck	3	LPUART1SEL	FMAX / 4	A
LPUART1	Kernel	csi_ker_ck	4	LPUART1SEL	FMAX / 4	A
LPUART1	Kernel	lse_ck	5	LPUART1SEL	FMAX / 4	A
LPUART1	Bus	pclk4	-	-	FMAX / 4	-
LTDC	Kernel	pll3_r_ck	-	-	90	A
LTDC	Bus	pclk5	-	-	FMAX / 4	-
LTDC	Bus	aclk	-	-	FMAX / 2	-
MDIO	Bus	pclk1	-	-	FMAX / 4	-
PKA	Bus	hclk3	-	-	FMAX / 2	-
PWR	Bus	hclk4	-	-	FMAX / 2	-
PSSI	Kernel	pll3_r_ck	0(4)	PSSISEL	100	-
PSSI	Kernel	per_ck	1	PSSISEL	100	-
PSSI	Bus	hclk2	-	-	FMAX / 2	-
XSPI1	Kernel	hclk5	0(4)	XSPI1SEL	FMAX / 2	A
XSPI1	Kernel	pll2_s_ck	1	XSPI1SEL	FMAX / 2	A
XSPI1	Kernel	pll2_t_ck	2	XSPI1SEL	FMAX / 2	A
XSPI1	Bus	hclk5	-	-	FMAX / 2	-
XSPI1	Bus	aclk	-	-	FMAX / 2	-
XSPI2	Kernel	hclk5	0(4)	XSPI2SEL	FMAX / 2	A
XSPI2	Kernel	pll2_s_ck	1	XSPI2SEL	FMAX / 2	A
XSPI2	Kernel	pll2_t_ck	2	XSPI2SEL	FMAX / 2	A
XSPI2	Bus	hclk5	-	-	FMAX / 2	-
XSPI2	Bus	aclk	-	-	FMAX / 2	-
OTGFS	Kernel	hsi48_ker_ck	0(4)	OTGFSSEL	50	A
OTGFS	Kernel	pll3_q_ck	1	OTGFSSEL	50	A
OTGFS	Kernel	hse_ker_ck	2	OTGFSSEL	50	A
OTGFS	Kernel	clk48mohci	3	OTGFSSEL	50	A
OTGFS	Bus	hclk1	-	-	FMAX / 2	-
OTGHS	Kernel	phy60m_ck	-	-	60	A
OTGHS	Bus	hclk1	-	-	FMAX / 2	-
RCC	Bus	hclk4	-	-	FMAX / 2	-
RNG	Kernel	hsi48_ker_ck	-	-	48	A
RNG	Bus	hclk3	-	-	FMAX / 2	-
RTC/AWU(5)	Kernel	no clock	0(4)	RTCSEL	4	A
RTC/AWU(5)	Kernel	lse_ck	1	RTCSEL	4	A
RTC/AWU(5)	Kernel	lsi_ck	2	RTCSEL	4	A
RTC/AWU(5)	Kernel	hse_ker_ck / (RTCDIV+1)	3	RTCSEL	4	A
RTC/AWU(5)	Bus	pclk4	-	-	FMAX / 4	-
SAI1	Kernel	pll1_q_ck	0(4)	SAI1SEL	133	A
SAI1	Kernel	pll2_p_ck	1	SAI1SEL	133	A
SAI1	Kernel	pll3_p_ck	2	SAI1SEL	133	A
SAI1	Kernel	I2S_CKIN	3	SAI1SEL	133	A
SAI1	Kernel	per_ck	4	SAI1SEL	133	A
SAI1	Bus	pclk2	-	-	FMAX / 4	-
SAI2	Kernel	pll1_q_ck	0(4)	SAI2SEL	133	A
SAI2	Kernel	pll2_p_ck	1	SAI2SEL	133	A
SAI2	Kernel	pll3_p_ck	2	SAI2SEL	133	A
SAI2	Kernel	I2S_CKIN	3	SAI2SEL	133	A
SAI2	Kernel	per_ck	4	SAI2SEL	133	A
SAI2	Kernel	spdif_symb_ck	5	SAI2SEL	133	A
SAI2	Bus	pclk2	-	-	FMAX / 4	-
SBS	Bus	pclk4	-	-	FMAX / 4	-
SDMMC1	Kernel	pll2_s_ck	0(4)	SDMMC12SEL	200	A
SDMMC1	Kernel	pll2_t_ck	1	SDMMC12SEL	200	A
SDMMC1	Bus	hclk5	-	-	FMAX / 2	-
SDMMC2	Kernel	pll2_s_ck	0(4)	SDMMC12SEL	200	A
SDMMC2	Kernel	pll2_t_ck	1	SDMMC12SEL	200	A
SDMMC2	Bus	hclk2	-	-	FMAX / 2	-
SPDIFRX	Kernel	pll1_q_ck	0(4)	SPDIFRXSEL	200	A
SPDIFRX	Kernel	pll2_r_ck	1	SPDIFRXSEL	200	A
SPDIFRX	Kernel	pll3_r_ck	2	SPDIFRXSEL	200	A
SPDIFRX	Kernel	hsi_ker_ck	3	SPDIFRXSEL	200	A
SPDIFRX	Bus	pclk1	-	-	FMAX / 4	-
SPI/I2S6	Kernel	pclk4	0(4)	SPI6SEL	200	A
SPI/I2S6	Kernel	pll2_q_ck	1	SPI6SEL	200	A
SPI/I2S6	Kernel	pll3_q_ck	2	SPI6SEL	200	A
SPI/I2S6	Kernel	hsi_ker_ck	3	SPI6SEL	200	A
SPI/I2S6	Kernel	csi_ker_ck	4	SPI6SEL	200	A
SPI/I2S6	Kernel	hse_ker_ck	5	SPI6SEL	200	A
SPI/I2S6	Bus	pclk4	-	-	FMAX / 4	-
SPI/I2S1	Kernel	pll1_q_ck	0(4)	SPI1SEL	130	A
SPI/I2S1	Kernel	pll2_p_ck	1	SPI1SEL	130	A
SPI/I2S1	Kernel	pll3_p_ck	2	SPI1SEL	130	A
SPI/I2S1	Kernel	I2S_CKIN	3	SPI1SEL	130	A
SPI/I2S1	Kernel	per_ck	4	SPI1SEL	130	A
SPI/I2S1	Bus	pclk2	-	-	FMAX / 4	-
SPI4, SPI5	Kernel	pclk2	0(4)	SPI45SEL	200	A
SPI4, SPI5	Kernel	pll2_q_ck	1	SPI45SEL	200	A
SPI4, SPI5	Kernel	pll3_q_ck	2	SPI45SEL	200	A
SPI4, SPI5	Kernel	hsi_ker_ck	3	SPI45SEL	200	A
SPI4, SPI5	Kernel	csi_ker_ck	4	SPI45SEL	200	A
SPI4, SPI5	Kernel	hse_ker_ck	5	SPI45SEL	200	A
SPI4, SPI5	Bus	pclk2	-	-	FMAX / 4	-
SPI/I2S3, SPI/I2S2	Kernel	pll1_q_ck	0(4)	SPI23SEL	200	A
SPI/I2S3, SPI/I2S2	Kernel	pll2_p_ck	1	SPI23SEL	200	A
SPI/I2S3, SPI/I2S2	Kernel	pll3_p_ck	2	SPI23SEL	200	A
SPI/I2S3, SPI/I2S2	Kernel	I2S_CKIN	3	SPI23SEL	200	A
SPI/I2S3, SPI/I2S2	Kernel	per_ck	4	SPI23SEL	200	A
SPI/I2S3, SPI/I2S2	Bus	pclk1	-	-	FMAX / 4	-
TAMPER	Kernel	no clock	0(4)	RTCSEL	4	A
TAMPER	Kernel	lse_ck	1	RTCSEL	4	A
TAMPER	Kernel	lsi_ck	2	RTCSEL	4	A
TAMPER	Kernel	hse_ker_ck/ (RTCDIV+1)	3	RTCSEL	4	A
TAMPER	Bus	pclk4	-	-	FMAX / 4	-
DTS	Kernel	lse_ck	-	-	10	A
DTS	Bus	pclk4	-	-	FMAX / 4	-
TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13, TIM14	Kernel	timg1_ck	-	-	FMAX / 2	S
TIM2, TIM3, TIM4, TIM5, TIM6, TIM7, TIM12, TIM13, TIM14	Bus	pclk1	-	-	FMAX / 4	-
TIM1, TIM9, TIM15, TIM16, TIM17	Kernel	timg2_ck	-	-	FMAX / 2	S
TIM1, TIM9, TIM15, TIM16, TIM17	Bus	pclk2	-	-	FMAX / 4	-
USART1	Kernel	pclk2	0(4)	USART1SEL	FMAX / 4	A
USART1	Kernel	pll2_q_ck	1	USART1SEL	FMAX / 4	A
USART1	Kernel	pll3_q_ck	2	USART1SEL	FMAX / 4	A
USART1	Kernel	hsi_ker_ck	3	USART1SEL	FMAX / 4	A
USART1	Kernel	csi_ker_ck	4	USART1SEL	FMAX / 4	A
USART1	Kernel	lse_ck	5	USART1SEL	FMAX / 4	A
USART1	Bus	pclk2	-	-	FMAX / 4	-
USART2, USART3, UART4, UART5, UART7, UART8	Kernel	pclk1	0(4)	UART234578SEL	FMAX / 4	A
USART2, USART3, UART4, UART5, UART7, UART8	Kernel	pll2_q_ck	1	UART234578SEL	FMAX / 4	A
USART2, USART3, UART4, UART5, UART7, UART8	Kernel	pll3_q_ck	2	UART234578SEL	FMAX / 4	A
USART2, USART3, UART4, UART5, UART7, UART8	Kernel	hsi_ker_ck	3	UART234578SEL	FMAX / 4	A
USART2, USART3, UART4, UART5, UART7, UART8	Kernel	csi_ker_ck	4	UART234578SEL	FMAX / 4	A
USART2, USART3, UART4, UART5, UART7, UART8	Kernel	lse_ck	5	UART234578SEL	FMAX / 4	A
USART2, USART3, UART4, UART5, UART7, UART8	Bus	pclk1	-	-	FMAX / 4	-
UCPD	Kernel	ucpd_ker_ck	-	-	25	A
UCPD	Bus	pclk1	-	-	FMAX / 4	-
USBPHYC	Kernel	hse_ker_ck	0(4)	USBPHYCSEL	32	A
USBPHYC	Kernel	hse_ker_ck / 2	1	USBPHYCSEL	32	A
USBPHYC	Kernel	pll3_q_ck	2	USBPHYCSEL	32	A
VREFBUF	Bus	pclk4	-	-	FMAX / 4	-
WWDG1	Bus	pclk1	-	-	FMAX / 4	-

Table 2 (pages 51–51)

Table 2 · 2 columns × 3 rows · p.51–51 · CSV

XSPIM features	i/f avaibility
Supports up to two single/dual/quad interfaces	Both
Fully I/O multiplexing capability	Both
Supports time-multiplexed mode	Both
Supports high-speed interface	Both
Chip select selection if XSPI provides dual chip select	Package dependent
Supports 16-bit data interface and dual-octal mode	Only a single i/f, package dependent

Table 3 (pages 52–52)

Table 3 · 2 columns × 22 rows · p.52–52 · CSV

Feature	XSPI1/2
HyperBus standard compliant	X
Xccela standard compliant	X
XSPI (JESD251C) standard compliant	X
AMBA® AXI compliant data interface	X
Asynchronous AHB clock versus kernel clock	X
Functional modes: indirect, automatic status-polling, and memory-mapped	X
Dual chip select support (NCS1 and NCS2)	X
Read and write support in memory-mapped mode	X
Dual-quad configuration	X
Dual-octal configuration	X
SDR (single-data rate) and DTR (double-transfer rate)	X
Data strobe (DS, DQS)	X
Fully programmable opcode	X
Fully programmable frame format	X
Integrated FIFO for reception and transmission	X
8, 16, and 32-bit data accesses	X
Interrupt on FIFO threshold, timeout, operation complete, and access error	X
Compliant with dual-XSPI arbiter (communication regulation)	X
Extended CSHT timeout	X
Memory-mapped write	X
Refresh counter	X
High-speed interface	X
GP/HPDMA interface	X
Prefetch disable	-
Prefetch hardware software	-

Table 4 (pages 53–53)

Table 4 · 3 columns × 0 rows · p.53–53 · CSV

Calibration value name	Description	Memory address
TS_CAL1	Temperature sensor 12-bit raw data acquired by ADC1 at 30 °C (± 5 °C), VDDA = VREF+ = 3.3 V (± 10 mV)	0x08FF F814 -0x08FF F815
TS_CAL2	Temperature sensor 12-bit raw data acquired by ADC1 at 130 °C (± 5 °C), VDDA = VREF+ = 3.3 V (± 10 mV)	0x08FF F818 -0x08FF F819

Table 5 (pages 55–55)

Table 5 · 2 columns × 11 rows · p.55–55 · CSV

Mode or feature	ADF1
Number of filters (DFLTx) and serial interfaces (SITFx)	1
ADF_CKI0 connected to pins	-
Sound activity detection (SAD)	X
RXFIFO depth (number of 24-bit words)	4
ADC connected to ADCITF1	ADC1
ADC connected to ADCITF2	ADC2
Motor dedicated features (SCD, OLD, OEC, INT, snapshot, break)	-
Main path with CIC4, CIC5	X
Main path with CIC1,2, 3 or FastSinc	-
RSFLT, HPF, SAT, SCALE, DLY, Discard functions	X
Autonomous in Stop modes	-

Table 6 (pages 58–58)

Table 6 · 8 columns × 9 rows · p.58–58 · CSV

Timer type	Timer	Counter resolution	Counter type	Prescaler factor	DMA request generation	Capture/ compare channels	Comple-mentary output
Advanced-control	TIM1	16-bit	Up, Down, Up/down	Any integer between 1 and 65536	Yes	4	4
General purpose	TIM2,TIM3, TIM4 TIM5	32-bit	Up, Down, Up/down	Any integer between 1 and 65536	Yes	4	No
General purpose	TIM9,TIM12	16-bit	Up	Any integer between 1 and 65536	No	2	No
General purpose	TIM13,TIM14	16-bit	Up	Any integer between 1 and 65536	No	1	No
General purpose	TIM15	16-bit	Up	Any integer between 1 and 65536	Yes	2	1
General purpose	TIM16, TIM17	16-bit	Up	Any integer between 1 and 65536	Yes	1	1
Basic	TIM6, TIM7	16-bit	Up	Any integer between 1 and 65536	Yes	0	No
Low-power timer	LPTIM1, LPTIM2, LPTIM3	16-bit	Up	1, 2, 4, 8, 16, 32, 64, 128	Yes	2	No
Low-power timer	LPTIM4, LPTIM5	16-bit	Up	1, 2, 4, 8, 16, 32, 64, 128	No	0	No

Table 7 (pages 64–64)

Table 7 · 2 columns × 5 rows · p.64–64 · CSV

Instance	STM32H7Rxx8
USART1	Full
USART2	Full
USART3	Full
UART4	Basic
UART5	Basic
UART7	Basic
UART8	Basic
LPUART1	Low-power

Table 8 (pages 66–66)

Table 8 · 3 columns × 4 rows · p.66–66 · CSV

SPI feature	SPI2S1, SPI2S2, SPI2S3 and SPI2S6 (full feature set instances)	SPI4 and SPI5 (full feature set instances)
Data and CRC size	Configurable from 4 to 32-bit	Configurable from 4 to 16-bit
CRC computation	CRC polynomial length configurable from 5 to 33-bit	CRC polynomial length configurable from 5 to 17-bit
Size of FIFOs	16x8-bit	8x8-bit
Number of data control (TSIZE)	Up to 65536	Up to 65536
I2S feature	Yes	No
Autonomous in Stop modes with wakeup capability	No	No
Autonomous in LP-Stop and Standby modes with wakeup capability	No	No

Table 9 (pages 67–67)

Table 9 · 3 columns × 1 rows · p.67–67 · CSV

SAI features	SAI1	SAI2
I2S, LSB or MSB-justified, PCM/DSP, TDM, AC’97	X
FIFO size	8 words
SPDIF	X
PDM	X(2)	-

Table 10 (pages 69–70)

Table 10 · 4 columns × 4 rows · p.69–70 · CSV

Mode	HS (480 Mbit/s)	FS (12 Mbit/s)	LS (1.5 Mbit/s)
Host mode	-	X	X
Device mode	-	X	-
Host mode	X	X	X
Device mode	X	X	-

Table 11 (pages 73–73)

Table 11 · 11 columns × 0 rows · p.73–73 · CSV

	1	2	3	4	5	6	7	8	9	10
A	PB8	PB6	PB3	BOOT0	PM14	PM12	PM9	PM6	PM8	PM2
B	PC14-OSC32_IN	PB9	PB7	PB4	PM13	PM11	DVDD	PM5	PM3	PM1

Table 12 (pages 74–74)

Table 12 · 12 columns × 3 rows · p.74–74 · CSV

	1 2	3	4	5	6	7	8	9	10	11	12
A	VSS PB8	PB6	PB5	PD7	BOOT0	PM11	PM9	PM6	VDD33USB	VDD50USB	VSS
B	VBAT PC13	PE1	PE0	PB3	PD5	PM12	PM8	PM5	PM2	PM3	PD4
	PC14-PC15-
C	OSC32_I OSC32_	PB9	PE2	PB4	PD6	PM14	DVDD	VSS	PM1	PD2	PC12
	N OUT

Table 13 (pages 75–75)

Table 13 · 13 columns × 0 rows · p.75–75 · CSV

	1 2	3	4	5	6	7	8	9	10	11	12	13
A	PB8 PB6	PE0	PB3	PF1	PD7	PD5	PM11	PM6	PM5	PM2	PM3	PG1
B	VBAT PB7	PE2	PB5	PF2	PD6	PM14	PM12	VSS	VDD50USB	PM1	PD4	PE13
C	PC15-PC14-OSC32_ OSC32_IOUT N	VDD	VSS	VDD	VSS	PM9	VDD33USB	VSS	VDD	PD3	PE12	PE11

Table 14 (pages 76–76)

Table 14 · 12 columns × 3 rows · p.76–76 · CSV

	1 2	3	4	5	6	7	8	9	10	11	12
A	VSS PB8	PB6	PD7	PD5	PM12	VDD50USB	PD4	PC10	PA15	PA9	VSS
B	VBAT PB9	PE1	PB5	PD6	PM11	VDD33USB	PD3	PD0	PA13	PA12	PC8
	PC14-PC15-
C	OSC32_I OSC32_	PC13	PB7	PB3	BOOT0	VSS	PG1	PD2	PA14	PA8	PC6
	N OUT

Table 15 (pages 77–77)

Table 15 · 12 columns × 1 rows · p.77–77 · CSV

	1 2	3	4	5	6	7	8 9	10	11	12	13
A	PB8 PB6	PE0	PB3	PF1	PD7	PD5	PM11 VDD50U SB	PE13	PE11	PC10	PA15
B	VBAT PB7	PE2	PB5	PF2	PG2	PD6	PM12 PG1	PD4	PD1	PD0	PA13
C	PC15-PC14-OSC32_ OSC32_IOUT N	VDD	VSS	VDD	VSS	PM14	VDD33U SB VSS	VDD	PC12	PA14	PA11
D	VDDSMP VSSSMPS S	PE3	PB9	PE1	PF0	PM13	PG0 PD3	PE14	VSS	PA12	PA9

Table 16 (pages 78–78)

Table 16 · 12 columns × 3 rows · p.78–78 · CSV

	1 2	3	4	5	6	7	8 9 10 11	12	13	14	15
A	VSS PB6	PB5	PF3	PF1	PD7	PD5	PM12 PM14 PM6 PM8	PM3	PD4	PE15	VSS
B	PB8 PE1	PE2	PB3	PF4	PF0	PD6	PM11 PM9 PM5 VDD50US B	PM1	PG0	PE13	PE11
C	VBAT PB9	PB7	PE0	PB4	PF2	BOOT0	PM13 DVDD VSSUSB PM2	PM0	PE14	PE12	PD1
D	PC14-OSC32_I VSS N	PC13	VDD	VSS	VSS	VDD	VSS VDD33US B VDD VSS	PD3	PD2	PD0	PC12
	PC15-
E	VSS OSC32_O	VSS	VSS					VSS	PC11	PC10	PA15

Table 17 (pages 79–79)

Table 17 · 15 columns × 2 rows · p.79–79 · CSV

	1	2	3	4	5	6	7	8 9	10	11	12	13	14	15
A	VSS	PB6	PB5	PF3	PF1	PG3	PD7	PD5 PM14	PM11	PD4	PE15	PE11	PD1	VSS
B	PB8	PE1	PE2	PB3	PF4	PF0	PD6	BOOT0 PM13	PM12	PG0	PE13	PE12	PD0	PC12
C	VBAT	PB9	PB7	PE0	PB4	PF2	PG2	VSS VDD50US B	PG1	PD3	PE14	PD2	PC11	PA15
D	PC14-OSC32_IN	VSS	PC13	VDD	VSS	VSS	VDD	VSS VDD33US B	VDD	VSS	VSS	PC10	PA13	PA11
		PC15-

Table 18 (pages 80–81)

Table 18 · 3 columns × 39 rows · p.80–81 · CSV

	176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
VBAT	1 132	VSS
PC13	2 131	PE15
PC14-OSC32_IN	3 130	PE14
PC15-OSC32_OUT	4 129	PE13
VDD	5 128	PE12
VSS	6 127	PE11
PE3	7 126	PD2
PE4	8 125	PD1
PE5	9 124	PD0
PE6	10 123	PC12
VSS	11 122	PC11
VDD	12 121	PC10
VSSSMPS	13 120	VDD
VLXSMPS	14 119	VDDLDO
VDDSMPS	15 118	VSS
VFBSMPS	16 117	VCAP3
PF5	17 116	PA15
PF6	18 115	PA14
PF7	19 114	PA13
PF8	20 113	PA12
PF9	21 112	PA11
VBAT	1 132	PD0
PC13	2 131	PC12
PC14-OSC32_IN	3 130	PC11
PC15-OSC32_OUT	4 129	PC10
VDD	5 128	VDD
VSS	6 127	VDDLDO
PE3	7 126	VSS
PE4	8 125	VCAP3
PE5	9 124	PA15
PE6	10 123	PA14
VSS	11 122	PA13
VDD	12 121	PA12
VSSSMPS	13 120	PA11
VLXSMPS	14 119	PA10
VDDSMPS	15 118	PA9
VFBSMPS	16 117	PA8
PF5	17 116	VDD
PF6	18 115	PC9
PF7	19 114	PC8
PF8	20 113	PC7
PF9	21 112	PC6

Table 19 (pages 82–82)

Table 19 · 8 columns × 10 rows · p.82–82 · CSV

	2 4		6		8		10
	1 3	5		7		9	11
A	VDD50USB PM5		PM12		VDD		VCAP4
	VDD VDD3USB	PM6		PM11		VSS	PC14-OSC32_IN
C	VSS VSSUSB		PM9		PD7		VDDLDO
							PC15-
	VCAP3 PM0	DVDD		PM13		PB5	OSC32_O
							UT
E	VDDLDO PM1		PM8		PB3		VSS
	PA15 PC10	PM3		BOOT0		PB6	VDD
G	PA14 PC11		PM14		PB7		PC13

Table 20 (pages 83–84)

Table 20 · 14 columns × 2 rows · p.83–84 · CSV

	1 2	3	4	5	6	7	8 9	10	11	12	13	14	15
A	VSS PE0	PF3	PF2	PG3	BOOT0	PM12	VSS PM6	PM3	VSS	PD3	PE14	PD2	VSS
B	PB8 PE2	PB5	PF4	PF0	PD7	PM11	PM9 PM5	PM2	PG0	PE13	PD1	PC10	PC11
C	VBAT PB9	PE1	PB3	PF1	PG2	PM13	PM14 PM8	PM1	PD4	PE11	PD0	PA12	PA11
D	PC15-PC14-OSC32_O OSC32_IUT N	VSS	PB7	PB4	VSS	PD5	DVDD VDD50US B	PM0	PE15	PC12	PA14	PA9	PC8
E	PE6 PE4	VSS	PC13	PB6	VCAP4	PD6	VSSUSB VSS	PG1	PE12	PA13	PA10	PC9	PC6

Table 21 (pages 85–85)

Table 21 · 3 columns × 5 rows · p.85–85 · CSV

	68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
VBAT	1 51	VCAP3
PC13	2 50	PA15
PC14-OSC32_IN	3 49	PA14
PC15-OSC32_OUT	4 48	PA13
PH0-OSC_IN	5 47	PA12
PH1-OSC_OUT	6 46	PA11
NRST	7 45	PA10
VSS	8 44	PA9

Table 22 (pages 86–86)

Table 22 · 3 columns × 9 rows · p.86–86 · CSV

	100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
VBAT	1 75	PM2
PC13	2 74	PM1
PC14-OSC32_IN	3 73	PM0
PC15-OSC32_OUT	4 72	PC12
PH0-OSC_IN	5 71	PC11
PH1-OSC_OUT	6 70	PC10
NRST	7 69	VDD
VSS	8 68	VSS
VDD	9 67	VCAP3
PC0	10 66	PA15
PC1	11 65	PA14
VSSA	12 64	PA13

Table 23 (pages 87–87)

Table 23 · 2 columns × 14 rows · p.87–87 · CSV

144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
1 108	VDD
2 107	VSS
3 106	PD2
4 105	PD1
5 104	PD0
6 103	PC12
7 102	PC11
8 101	PC10
9 100	VDD
10 99	VSS
11 98	VCAP3
12 97	PA15
13 96	PA14
14 95	PA13
15 94	PA12
16 93	PA11
17 92	PA10

Table 24 (pages 88–88)

Table 24 · 4 columns × 17 rows · p.88–88 · CSV

Name		Abbreviation	Definition
Pin name		Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
Pin type		S	Supply pin
Pin type		I	Input only pin
Pin type	Pin type	I/O	Input/output pin
I/O structure	I/O structure	FT	5V-tolerant I/O
I/O structure	I/O structure	TT	3.6V-tolerant I/O
I/O structure	I/O structure	B	Dedicated BOOT pin
I/O structure	I/O structure	RST	Bidirectional reset pin with embedded weak pull-up resistor
I/O structure	I/O structure	Option for TT or FT I/Os(1)	Option for TT or FT I/Os(1)
I/O structure	I/O structure	_a	I/O, with analog switch function supplied by VDDA
I/O structure	I/O structure	_f	I/O, Fm+ capable
I/O structure	I/O structure	_h	I/O with high-speed low-voltage mode (HSLV)
I/O structure	I/O structure	_s	I/O supplied only by V DDIOx(2)
I/O structure	I/O structure	_t	I/O with tamper function functional in VBAT mode
I/O structure	I/O structure	_c	I/O power delivery
I/O structure	I/O structure	_d	I/O i/o dead battery
I/O structure	I/O structure	_u	I/O USB
Notes	Notes	Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.	Unless otherwise specified by a note, all I/Os are set as analog inputs during and after reset.
Pin functions	Alternate functions	Functions selected through GPIOx_AFR registers	Functions selected through GPIOx_AFR registers
Pin functions	Additional functions	Functions directly selected/enabled through peripheral registers	Functions directly selected/enabled through peripheral registers

Table 25 (pages 89–127)

Table 25 · 21 columns × 256 rows · p.89–127 · CSV

Pin number															Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
TFBGA100 SMPS GP	UFBGA144 SMPS GP	UFBGA144 SMPS GFx	UFBGA169 SMPS GFx	UFBGA169 SMPS GP	UFBGA176 SMPS GP	LQFP176 SMPS GP	LQFP176 SMPS GFx	UFBGA176 SMPS GFx	WLCSP101 SMPS GP	TFBGA225 OCTO SMPS	TFBGA225 HEXA SMPS	VFQFPN68 GP	LQFP100 GP	LQFP144 GP	Pin name (function after reset)	Pin type	I/O structure	Notes	Alternate functions	Additional functions
B2	C3	B2	D4	D4	C2	176	176	C2	-	C2	C2	68	100	2	PB9	I/O	FT_fh	-	TIM17_CH1, TIM4_CH4, I2C1_SDA/I3C1_SDA, SPI2_NSS/I2S2_WS, PSSI_D7, SDMMC1_CDIR, UART4_TX, FDCAN1_TX, SDMMC2_D5, SDMMC1_D5, DCMIPP_D7, EVENTOUT	TAMP_IN2/ TAMP_OUT1
C3	B1	B1	B1	B1	C1	1	1	C1	H9	C1	C1	1	1	3	VBAT	S	-	-	-	-
C1	A1	A1	C4	B9	A1	-	-	A1	B9	A1	A1	-	-	-	VSS	S	-	-	-	-
D3	B2	C3	E4	E4	D3	2	2	D3	G10	E4	E4	2	2	4	PC13	I/O	-	Note(2)(3)	EVENTOUT	TAMP_IN1/ TAMP_OUT2, RTC_OUT1/ RTC_TS, WKUP3
C5	A12	A12	C6	C4	A15	-	-	A15	C2	A8	A8	-	-	-	VSS	S	-	-	-	-
B1	C1	C1	C2	C2	D1	3	3	D1	B11	D2	D2	3	3	5	PC14-OSC32_IN(OSC32_IN)	I/O	-	Note(2)	EVENTOUT	OSC32_IN
C2	C2	C2	C1	C1	E2	4	4	E2	D11	D1	D1	4	4	6	PC15-OSC32_OUT(OSC32_OUT)	I/O	-	Note(2)	EVENTOUT	OSC32_OUT
D5	D6	D4	C3	C3	D4	5	5	D4	F11	F7	F7	-	-	7	VDD	S	-	-	-	-
C7	C9	C7	C9	C6	D2	6	6	C8	E10	A11	A11	-	-	8	VSS	S	-	-	-	-
-	D3	D3	D3	D3	F2	7	7	F2	-	F5	F5	-	-	9	PE3	I/O	FT_h	-	TRACED0, LPTIM5_ETR, TIM15_BKIN, SAI1_SD_B, ETH_MII_RXD3, FMC_D12/FMC_AD12, EVENTOUT	-
-	E3	E3	E3	E3	F3	8	8	F3	-	E2	E2	-	-	10	PE4	I/O	FT_h	-	TRACED1, SAI1_D2, ADF1_SDI0, TIM15_CH1N, SPI4_NSS, SAI1_FS_A, PSSI_D4, FMC_D13/FMC_AD13, DCMIPP_D4, EVENTOUT	-
-	D1	D1	F5	F5	F1	9	9	F1	-	F4	F4	-	-	11	PE5	I/O	FT_h	-	TRACED2, ADF1_CCK1, SAI1_CK2, TIM15_CH1, SPI4_MISO, SAI1_SCK_A, PSSI_D6, FMC_D14/FMC_AD14, DCMIPP_D6, EVENTOUT	-
-	E2	E2	F4	F4	G3	10	10	G3	-	E1	E1	-	-	12	PE6	I/O	FT_h	-	TRACED3, TIM1_BKIN2, SAI1_D1, ADF1_SDI0, TIM15_CH2, SPI4_MOSI, SAI1_SD_A, PSSI_D7, SAI2_MCLK_B, FMC_D15/FMC_AD15, DCMIPP_D7, EVENTOUT	-
E3	D9	D7	C5	-	D7	-	-	D7	-	F9	F9	-	-	-	VDD	S	-	-	-	-
E4	D2	D2	D11	C9	D5	-	-	D2	R4	A15	A15	-	-	-	VSS	S	-	-	-	-
-	-	-	-	-	-	-	-	-	-	F3	F3	-	-	-	PG11	I/O	FT_h	-	LPTIM1_IN2, SPI1_SCK/I2S1_CK, SPDIFRX_IN0, PSSI_D3, SDMMC2_D2, ETH_MII_TX_EN/ETH_RMII_TX_EN, FMC_D28, DCMIPP_D3, EVENTOUT	-
-	-	-	-	-	-	-	-	-	-	F2	F2	-	-	-	PG12	I/O	FT_h	-	LPTIM1_IN1, SPI6_MISO/I2S6_SDI, SPDIFRX_IN1, SDMMC2_D3, ETH_MII_TXD1/ETH_RMII_TXD1, FMC_D29, LCD_G1, EVENTOUT	-
-	-	-	-	-	-	-	-	-	-	G5	G5	-	-	-	PG13	I/O	FT_h	-	TRACED0, LPTIM1_CH1, SPI6_SCK/I2S6_CK, SDMMC2_D6, ETH_MII_TXD0/ETH_RMII_TXD0, FMC_D30, LCD_CLK, EVENTOUT	-
-	-	-	-	-	-	-	-	-	-	F1	F1	-	-	-	PG14	I/O	FT_h	-	TRACED1, LPTIM1_ETR, SPI6_MOSI/I2S6_SDO, SDMMC2_D7, ETH_MII_TXD1/ETH_RMII_TXD1, FMC_D31, LCD_B1, EVENTOUT	-
-	-	-	-	-	-	-	-	-	-	G4	G4	-	-	-	PG15	I/O	FT_h	-	LPTIM1_CH2, PSSI_D13, FMC_NBL3, DCMIPP_D13, EVENTOUT	-
F6	D5	E4	F3	D11	D6	11	11	D5	T1	D3	D3	-	-	-	VSS	S	-	-	-	-
E7	E4	F4	C10	C5	D10	12	12	D10	-	F10	F10	-	-	-	VDD	S	-	-	-	-
D2	E1	E1	D2	D2	G1	13	13	G1	H11	H2	H2	-	-	-	VSSSMPS	S	-	-	-	-
E2	F1	F1	E2	E2	G2	14	14	G2	J10	G1	G1	-	-	-	VLXSMPS	S	-	-	-	-
D1	F2	F2	D1	D1	H2	15	15	H2	K11	H1	H1	-	-	-	VDDSMPS	S	-	-	-	-
E1	F3	F3	E1	E1	H1	16	16	H1	L10	G2	G2	-	-	-	VFBSMPS	S	-	-	-	-
-	-	-	-	F1	H3	17	17	H3	-	G3	G3	-	-	-	PF5	I/O	FT_h	-	DCMIPP_D15, UCPD_FRSTX1, PSSI_D15, FMC_CLE, ETH_MII_RXD2, FMC_A16, EVENTOUT	-
-	-	-	F2	F2	J1	18	18	J1	-	H5	H5	-	-	-	PF6	I/O	FT_h	-	TIM16_CH1, SPI5_NSS, SAI1_SD_B, UART7_RX, FMC_ALE, FMC_A17, EVENTOUT	-
-	-	-	G4	G4	J3	19	19	J3	-	H4	H4	-	-	-	PF7	I/O	FT_h	-	TIM17_CH1, SPI5_SCK, SAI1_MCLK_B, UART7_TX, FMC_A18, LCD_G0, EVENTOUT	-
-	-	-	F1	G1	J2	20	20	J2	-	H3	H3	-	-	-	PF8	I/O	FT_h	-	TIM16_CH1N, DCMIPP_PIXCLK, SPI5_MISO, SAI1_SCK_B, UART7_RTS/UART7_DE, PSSI_PDCK, TIM13_CH1, FMC_A19, LCD_G1, EVENTOUT	-
-	-	-	G5	G5	K2	21	21	K2	-	J2	J2	-	-	-	PF9	I/O	FT_h	-	TIM17_CH1N, SPI5_MOSI, SAI1_FS_B, UART7_CTS, TIM14_CH1, FMC_A21, LCD_R0, EVENTOUT	-
-	-	-	-	-	K1	22	22	K1	-	J3	J3	-	-	-	PF10	I/O	FT_h	-	TIM16_BKIN, SAI1_D3, DCMIPP_D15, PSSI_D15, PSSI_D11, FMC_A22, DCMIPP_D11, LCD_R1, EVENTOUT	-
F1	G2	G2	G2	G2	L2	23	23	L2	M11	K1	K1	5	5	13	PH0-OSC_IN(PH0)	I/O	FT_h	-	EVENTOUT	OSC_IN
F2	H1	H1	G1	H1	M1	24	24	M1	P11	K2	K2	6	6	14	PH1-OSC_OUT(PH1)	I/O	FT_h	-	EVENTOUT	OSC_OUT
F3	F4	G4	H4	H4	M2	25	25	M2	K9	J4	J4	7	7	15	NRST	I/O	RST	-	-	-
F8	D7	E8	F7	F3	D8	-	-	D6	T7	D6	D6	-	-	-	VSS	-	-	-	-	-
H4	E7	F5	F11	F7	D11	26	26	D8	V9	E3	E3	8	8	16	VSS	S	-	-	-	-
G4	F9	F9	E11	C10	F12	27	27	F12	W10	G6	G6	9	9	17	VDD	S	-	-	-	-
G7	G4	H9	G3	E11	G4	-	-	G4	-	H6	H6	-	-	-	VDD	-	-	-	-	-
G1	G3	G3	H3	H3	N1	28	28	N1	M9	K3	K3	-	10	18	PC0	I/O	FT_h	-	GFXTIM_FCKCAL, SAI2_FS_B, FMC_NBL1, GFXTIM_LCKCAL, EVENTOUT	ADC12_INP10
H1	G5	H5	H5	H5	P1	29	29	P1	L8	L1	L1	-	11	19	PC1	I/O	FT_h	-	TRACED0, SAI1_D1, ADF1_SDI0, SPI2_MOSI/I2S2_SDO, SAI1_SD_A, FMC_A16, SDMMC2_CK, ETH_MDC, FMC_A0, MDIOS_MDC, EVENTOUT	ADC12_INP11, ADC12_INN10, TAMP_IN7/TAMP_OUT8, WKUP4
-	J1	J1	H2	H2	P2	30	30	P2	-	L2	L2	-	-	20	PC2	I/O	FT_h	-	TIM1_CH1, SPI2_MISO/I2S2_SDI, FMC_A17, ETH_MII_TXD2, FMC_A1, EVENTOUT	ADC12_INP12, ADC12_INN11
-	H2	H2	H1	J1	N2	31	31	N2	-	L3	L3	-	-	21	PC3	I/O	FT_h	-	TIM1_CH2, SPI2_MOSI/I2S2_SDO, FMC_A18, ETH_MII_TX_CLK, FMC_A2, EVENTOUT	ADC12_INP13, ADC12_INN12
G3	H3	J3	J4	J4	L4	32	32	L4	R10	J5	J5	10	12	22	VSSA	S	-	-	-	-
F4	H5	H4	J3	J3	N3	33	33	N3	N10	K4	K4	-	13	23	VREFM	S	-	-	-	-
J1	K3	K3	K3	K3	M3	34	34	M3	U10	K5	K5	11	14	24	VREFP	S	-	-	-	-
H2	J3	H3	K4	K4	M4	35	35	M4	T11	J6	J6	12	15	25	VDDA	S	-	-	-	-
K1	K1	J2	J1	K1	R2	36	36	R2	P9	M1	M1	13	16	26	PA0	I/O	FT_h	-	TIM2_CH1, TIM5_CH1, TIM9_CH1, TIM15_BKIN, SPI6_NSS/I2S6_WS, USART2_CTS/USART2_NSS, UART4_TX, SDMMC2_CMD, SAI2_SD_B, FMC_AD7/FMC_D7, LCD_G3, EVENTOUT	ADC12_INP0, ADC12_INN1, WKUP1
G2	J2	K1	L1	L1	P3	37	37	P3	K7	M2	M2	14	17	27	PA1	I/O	FT_h	-	TIM2_CH2, TIM5_CH2, LPTIM3_IN1, TIM15_CH1N, DCMIPP_D0, PSSI_D0, USART2_RTS/USART2_DE, UART4_RX, SAI2_MCLK_B, ETH_MII_RX_CLK/ETH_RMII_REF_CLK, FMC_AD6/FMC_D6, LCD_G2, EVENTOUT	ADC12_INP1
J2	L1	L1	K1	M1	R3	38	38	R3	V11	L4	L4	15	18	28	PA2	I/O	FT_h	-	TIM2_CH3, TIM5_CH3, LPTIM3_IN2, TIM15_CH1, USART2_TX, SAI2_SCK_B, ETH_MDIO, FMC_AD5/FMC_D5, LCD_B7, MDIOS_MDIO, EVENTOUT	ADC12_INP14, WKUP2
-	K2	K2	J5	J5	N4	39	39	N4	-	N1	N1	16	19	29	PA3	I/O	FT_h	-	TIM2_CH4, TIM5_CH4, LPTIM3_CH1, TIM15_CH2, I2S6_MCK, SPI4_RDY, USART2_RX, GFXTIM_LCKCAL, SPI5_RDY, SPI1_RDY, ETH_MII_COL, GFXTIM_FCKCAL, LCD_DE, TIM1_CH3, EVENTOUT	ADC12_INP15
-	G1	G1	G7	G6	E3	40	40	D12	-	F6	F6	-	20	30	VSS	S	-	-	-	-
-	J5	J4	K2	G3	J12	41	41	K4	-	H10	H10	-	-	31	VDD	S	-	-	-	-
K2	L2	M2	L2	L2	M5	42	42	M5	N8	M3	M3	17	21	32	PA4	I/O	FT_h	-	TIM5_ETR, LPTIM3_CH2, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, USART2_CK, SPI6_NSS/I2S6_WS, PSSI_DE, OTG_HS_SOF, ETH_MDIO, LCD_R3, DCMIPP_HSYNC, EVENTOUT	ADC1_INP18
H3	J4	L2	L3	L3	P4	43	43	P4	J6	N2	N2	18	22	33	PA5	I/O	FT_h	-	PWR_CSTOP, TIM2_CH1, TIM2_ETR, TIM9_CH2, SPI1_SCK/I2S1_CK, PSSI_D8, SPI6_SCK/I2S6_CK, FMC_NOE, DCMIPP_D8, LCD_CLK, EVENTOUT	ADC2_INP18
-	G8	G5	G8	G7	E4	-	-	E1	-	F15	F15	-	-	-	VSS	S	-	-	-	-
-	J9	-	K10	G11	K4	-	-	M6	-	K6	K6	19	23	-	VDD	S	-	-	-	-
K3	M2	M3	M1	N1	R4	44	44	R4	M7	P1	P1	20	24	34	PA6	I/O	FT_h	-	PWR_CSLEEP, TIM1_BKIN, TIM3_CH1, LPTIM3_ETR, SPI1_MISO/I2S1_SDI, PSSI_PDCK, SPI6_MISO/I2S6_SDI, TIM13_CH1, MDIOS_MDC, LCD_B7, DCMIPP_PIXCLK, LCD_HSYNC, EVENTOUT	ADC12_INP3
J3	K4	L3	M2	M2	N5	45	45	N5	T9	M4	M4	21	25	35	PA7	I/O	FT_h	-	TIM1_CH1N, TIM3_CH2, SPI1_MOSI/I2S1_SDO, SPI6_MOSI/I2S6_SDO, TIM14_CH1, LCD_R4, ETH_MII_RX_DV/ETH_RMII_CRS_DV, FMC_INT, LCD_B1, EVENTOUT	ADC12_INP7, ADC12_INN3
-	L3	K4	N1	N2	P5	46	46	P5	-	L5	L5	-	-	36	PC4	I/O	FT_h	-	I2S1_MCK, FMC_A19, SPDIFRX_IN2, ETH_MII_RXD0/ETH_RMII_RXD0, FMC_A3, EVENTOUT	ADC12_INP4
-	M3	M4	N2	L4	R5	47	47	R5	-	N3	N3	-	-	37	PC5	I/O	FT_h	-	SAI1_D3, DCMIPP_D15, PSSI_D15, FMC_A21, SPDIFRX_IN3, ETH_MII_RXD1/ETH_RMII_RXD1, FMC_A5, EVENTOUT	ADC12_INP8, ADC12_INN4
F5	L4	L4	K5	K5	N6	48	48	N6	R8	P2	P2	22	26	38	PB0	I/O	FT_h	-	TIM1_CH2N, TIM3_CH3, TIM9_CH1, SPI1_SCK/I2S1_CK, UART4_CTS, ETH_MII_TXD0/ETH_RMII_TXD0, GFXTIM_TE, [RNG_S1], LCD_VSYNC, EVENTOUT	ADC12_INP9, ADC12_INN5
K4	M4	J6	M3	M3	R6	49	49	R6	L6	R2	R2	23	27	39	PB1	I/O	FT_h	-	TIM1_CH3N, TIM3_CH4, TIM9_CH2, FDCAN2_TX, LCD_G2, ETH_MII_TXD1/ETH_RMII_TXD1, FMC_NOE, [RNG_S2], EVENTOUT	ADC12_INP5
G5	L5	L5	L4	N3	P6	50	50	P6	N6	N4	N4	24	28	40	PB2	I/O	FT_h	-	RTC_OUT2, SAI1_D1, ADF1_SDI0, SAI1_SD_A, SPI3_MOSI/I2S3_SDO, LCD_B2, FMC_NWE, EVENTOUT	-
-	-	-	L5	K2	L12	51	51	M12	-	K8	K8	-	-	41	VDD	S	-	-	-	-
-	H4	G8	H7	G8	E12	52	52	E3	-	G8	G8	-	-	-	VSS	S	-	-	-	-
-	-	-	N3	M4	R7	53	53	R7	-	M5	M5	-	-	-	PF11	I/O	FT_h	-	SPI5_MOSI, PSSI_D12, SAI2_SD_B, FMC_A23, DCMIPP_D12, LCD_B0, EVENTOUT	ADC1_INP2
-	-	-	-	-	N7	-	-	N7	-	R3	R3	-	-	-	PF12	I/O	FT_h	-	USART1_RX, SPI5_MISO, FMC_D19, EVENTOUT	ADC1_INP6, ADC1_INN2
-	-	-	-	-	P7	-	-	P7	-	P3	P3	-	-	-	PF13	I/O	FT_h	-	USART1_TX, SPI5_NSS, PSSI_D10, FMC_D20, DCMIPP_D10, EVENTOUT	ADC2_INP2
-	-	-	-	-	-	-	-	-	-	P4	P4	-	-	-	PF14	I/O	FT_h	-	USART1_CTS, SPI5_MOSI, FMC_A24, LCD_G0, EVENTOUT	ADC2_INP6, ADC2_INN2
-	-	-	-	-	-	-	-	-	-	N5	N5	-	-	-	PF15	I/O	FT_h	-	USART1_RTS/USART1_DE, SPI5_SCK, FMC_A25, LCD_G1, EVENTOUT	-
-	-	-	K6	K6	P8	54	54	P8	-	M6	M6	-	-	-	PE7	I/O	FT_h	-	TIM1_ETR, UART7_RX, FMC_A20, SAI2_SD_B, FMC_A4, EVENTOUT	-
-	-	-	M4	N4	R8	55	55	R8	-	R4	R4	-	-	-	PE8	I/O	FT_h	-	TIM1_CH1N, UART7_TX, FMC_A12, EVENTOUT	-
-	-	-	M5	J7	N8	56	56	N8	-	P5	P5	-	-	-	PE9	I/O	FT_h	-	TIM1_CH1, UART7_RTS/UART7_DE, FMC_A14, FMC_BA0, EVENTOUT	-
-	-	-	N4	M5	N9	57	57	N9	-	R5	R5	-	-	-	PE10	I/O	FT_h	-	TIM1_CH2N, UART7_CTS, FMC_A15, FMC_BA1, EVENTOUT	-
-	-	-	-	K10	M6	58	58	-	-	K10	K10	-	-	41	VDD	S	-	-	-	-
-	G6	G6	H6	H6	J7	59	59	J7	U8	J7	J7	-	-	-	VDDLDO	S	-	-	-	-
-	H7	H7	H11	H7	F4	60	60	E4	-	G10	G10	-	-	42	VSS	S	-	-	-	-
-	H6	H6	J6	J6	K7	61	61	K7	W8	L7	L7	-	-	43	VCAP1	S	-	-	-	-
-	-	-	-	-	-	-	-	-	-	N6	-	-	-	-	PG4	I/O	FT_h	-	TIM1_BKIN2, ETH_MII_RXD0/ETH_RMII_RXD0, FMC_D22, EVENTOUT	-
-	-	-	-	-	-	-	-	-	-	P6	-	-	-	-	PG5	I/O	FT_h	-	TIM1_ETR, ETH_MII_RXD1/ETH_RMII_RXD1, FMC_D23, EVENTOUT	-
-	-	-	-	-	-	-	-	-	-	M7	-	-	-	-	PG6	I/O	FT_h	-	TIM17_BKIN, PSSI_D12, ETH_MDC, FMC_NBL2, DCMIPP_D12, EVENTOUT	-
-	-	-	-	-	-	-	-	-	-	N7	-	-	-	-	PG7	I/O	FT_h	-	SAI1_MCLK_A, PSSI_D13, FMC_D24, DCMIPP_D13, EVENTOUT	-
-	-	-	-	-	-	-	-	-	-	P7	-	-	-	-	PG8	I/O	FT_h	-	SPI6_NSS/I2S6_WS, SPDIFRX_IN2, ETH_PPS_OUT, FMC_D25, LCD_G0, EVENTOUT	-
-	-	-	-	-	-	-	-	-	-	R7	-	-	-	-	PG9	I/O	FT_h	-	SPI1_MISO/I2S1_SDI, SPDIFRX_IN3, PSSI_RDY, SAI2_FS_B, SDMMC2_D0, FMC_D26, DCMIPP_VSYNC, EVENTOUT	-
-	-	-	-	-	-	-	-	-	U4	-	L8	-	-	-	VDDXSPI1	S	-	-	-	-
-	-	-	-	-	-	-	-	-	-	-	H7	-	-	-	VSS	S	-	-	-	-
-	-	-	-	-	-	-	-	-	-	-	N6	-	-	-	PP12	I/O	FT_h	-	XSPIM_P1_IO12	-
-	-	-	-	-	-	-	-	-	-	-	P6	-	-	-	PP11	I/O	FT_h	-	XSPIM_P1_IO11	-
-	-	-	-	-	-	-	-	-	-	-	N7	-	-	-	PP14	I/O	FT_h	-	XSPIM_P1_IO14	-
-	-	-	-	-	-	-	-	-	-	-	R7	-	-	-	PP13	I/O	FT_h	-	XSPIM_P1_IO13	-
J4	J6	J7	K7	K7	P9	62	62	P9	P7	P8	P7	-	29	44	PO1	I/O	FT_h	-	XSPIM_P1_NCS2	-
G6	K5	K5	K8	K8	K9	63	63	K9	V1	L8	L10	-	30	45	VDDXSPI1	S	-	-	-	-
-	K8	J5	K11	J2	F8	64	64	F4	-	H7	H8	-	31	46	VSS	S	-	-	-	-
-	-	-	-	-	-	-	-	-	-	-	P8	-	-	-	PP15	I/O	FT_h	-	XSPIM_P1_IO15	-
K5	M5	M5	N5	N5	R9	65	65	R9	U6	R8	R8	-	32	47	PP4	I/O	FT_h	-	XSPIM_P1_IO4	-
J5	L6	L6	M6	M6	P10	66	66	P10	R6	N8	N9	25	33	48	PP2	I/O	FT_h	-	XSPIM_P1_IO2	-
K6	M6	M6	N6	N6	R10	67	67	R10	V5	N9	P9	26	34	49	PP3	I/O	FT_h	-	XSPIM_P1_IO3	-
-	K10	K6	L6	K11	F9	68	68	F7	-	H8	H9	27	35	50	VSS	S	-	-	-	-
H5	K7	K7	L7	L7	M8	69	69	M8	V7	L10	M8	28	36	51	VDDXSPI1	S	-	-	-	-
J6	L7	L7	M7	M7	P11	70	70	P11	T5	R9	P10	-	37	52	PO5	I/O	FT_h	-	XSPIM_P1_NCLK	-
K7	M7	M7	N7	N7	R11	71	71	R11	P5	R10	R10	29	38	53	PO4	I/O	FT_h	-	XSPIM_P1_CLK	-
J7	M8	M8	M8	M8	N11	72	72	N11	N4	P10	N10	-	39	54	PP5	I/O	FT_h	-	XSPIM_P1_IO5	-
K8	L8	L8	N8	N8	R12	73	73	R12	P3	N10	P11	30	40	55	PP0	I/O	FT_h	-	XSPIM_P1_IO0	-
-	M1	K8	L8	L6	F10	74	74	F8	-	H9	H11	-	41	56	VSS	S	-	-	-	-
H7	K9	K9	L9	L9	M10	75	75	M10	-	M10	M10	-	42	57	VDDXSPI1	S	-	-	-	-
J8	M9	M9	M9	M9	P12	76	76	P12	T3	R11	R11	-	43	58	PP6	I/O	FT_h	-	XSPIM_P1_IO6	-
K9	L9	L9	N9	N9	R13	77	77	R13	V3	P11	N11	-	44	59	PO2	I/O	FT_h	-	XSPIM_P1_DQS0	-
J9	M10	M10	M10	M10	P13	78	78	P13	R2	N11	P12	-	45	60	PP7	I/O	FT_h	-	XSPIM_P1_IO7	-
K10	L10	L10	N10	N10	R14	79	79	R14	U2	P12	N12	31	46	61	PP1	I/O	FT_h	-	XSPIM_P1_IO1	-
-	M12	M1	L10	L8	G6	80	80	F9	-	H11	J1	32	47	62	VSS	S	-	-	-	-
-	-	-	-	-	-	81	81	-	-	-	-	33	48	63	VDDXSPI1	S	-	-	-	-
H8	J7	J8	K9	K9	P14	82	82	P14	N2	N12	R13	34	49	64	PO0	I/O	FT_h	-	XSPIM_P1_NCS1	-
-	-	-	-	-	-	-	-	-	-	-	P13	-	-	-	PP8	I/O	FT_h	-	XSPIM_P1_IO8	-
-	-	-	-	-	-	-	-	-	-	-	M11	-	-	-	PO3	I/O	FT_h	-	XSPIM_P1_DQS1	-
-	-	-	-	-	-	-	-	-	-	-	R14	-	-	-	PP9	I/O	FT_h	-	XSPIM_P1_IO9	-
-	-	-	-	-	-	-	-	-	-	-	M12	-	-	-	PP10	I/O	FT_h	-	XSPIM_P1_IO10	-
-	-	-	-	-	-	-	-	-	-	-	J8	-	-	-	VSS	S	-	-	-	-
-	-	-	-	-	-	-	-	-	-	R13	-	-	-	-	PG10	I/O	FT_h	-	SPI1_NSS/I2S1_WS, PSSI_D2, SAI2_SD_B, SDMMC2_D1, FMC_D27, DCMIPP_D2, EVENTOUT	-
-	J8	-	J7	N11	N12	83	-	N12	-	M11	-	-	-	65	PD8	I/O	FT_h	-	USART3_TX, SPDIFRX_IN1, ETH_MII_TX_EN/ETH_RMII_TX_EN, FMC_NBL0, LCD_R0, EVENTOUT	-
-	-	-	N11	N12	P15	84	-	-	-	P13	-	-	-	66	PD9	I/O	FT_h	-	USART3_RX, FMC_SDCLK, LCD_R1, EVENTOUT	-
-	M11	-	M11	M11	N13	85	-	-	-	R14	-	-	-	67	PD10	I/O	FT_h	-	TIM1_CH4, DCMIPP_D4, SPI4_RDY, USART3_CK, PSSI_D4, SPI5_RDY, SPI1_RDY, FMC_CLK, LCD_B0, EVENTOUT	TAMP_IN8/TAMP_OUT7
-	L11	-	-	N13	N14	86	-	-	-	M12	-	-	-	68	PD11	I/O	FT_h	-	TIM1_ETR, LPTIM2_IN2, DCMIPP_D6, USART3_CTS/USART3_NSS, PSSI_D6, SAI2_SD_A, FMC_D16, EVENTOUT	-
-	-	-	-	L5	M12	87	-	-	P1	L9	L9	-	-	69	VDD	S	-	-	-	-
-	-	M12	-	L10	G8	88	-	F10	-	J1	J10	-	-	70	VSS	S	-	-	-	-
-	K11	-	-	L11	M13	89	-	-	M5	N13	N13	-	-	71	PD12	I/O	FT_h	-	LPTIM1_IN1, TIM4_CH1, LPTIM2_IN1, USART3_RTS/USART3_DE, PSSI_D12, SAI2_FS_A, FMC_NE1, DCMIPP_D12, LCD_DE, EVENTOUT	-
-	L12	-	-	M12	N15	90	-	-	-	P14	P14	-	-	72	PD13	I/O	FT_h	-	LPTIM1_CH1, TIM4_CH2, UCPD_FRSTX2, SAI2_SCK_A, PSSI_D13, FMC_INT, DCMIPP_D13, EVENTOUT	-
H9	J10	J9	L11	L12	M14	91	83	N13	M3	P15	P15	35	50	73	PB10	I/O	FT_fh	-	TIM2_CH3, LPTIM2_IN1, I2C2_SCL, SPI2_SCK/I2S2_CK, USART3_TX, ETH_MII_RX_ER, FMC_D11/FMC_AD11, LCD_G7, EVENTOUT	-
J10	K12	M11	N12	M13	M15	92	84	P15	K5	N14	N14	36	51	74	PB11	I/O	FT_fh	-	TIM2_CH4, LPTIM2_ETR, I2C2_SDA, USART3_RX, ETH_MII_TX_EN/ETH_RMII_TX_EN, FMC_D10/FMC_AD10, LCD_G6, EVENTOUT	-
G9	H10	K10	J8	J8	L13	93	85	L13	L4	L12	L12	37	52	75	PB12	I/O	FT_h	-	TIM1_BKIN, LPTIM2_IN2, I2C2_SMBA, SPI2_NSS/I2S2_WS, USART3_CK, FDCAN2_RX, FMC_D9/FMC_AD9, LCD_G5, UART5_RX, EVENTOUT	-
H10	J11	L12	M12	L13	L15	94	86	N14	-	N15	N15	-	53	76	PB13	I/O	FT_h	-	TIM1_CH1N, LPTIM2_CH1, SPI2_SCK/I2S2_CK, SDMMC1_D0, USART3_CTS/USART3_NSS, PSSI_D2, FDCAN2_TX, LCD_G4, ETH_MII_RXD3, FMC_D8/FMC_AD8, DCMIPP_D2, UART5_TX, EVENTOUT	-
F9	H9	K11	J9	J9	L14	95	87	K13	L2	M13	M13	38	54	77	PB14	I/O	FT_h	-	TIM1_CH2N, TIM12_CH1, LPTIM2_CH2, USART1_TX, SPI2_MISO/I2S2_SDI, USART3_RTS/USART3_DE, UART4_RTS/UART4_DE, SDMMC2_D0, FMC_NE1, LCD_DE, EVENTOUT	-
G10	J12	L11	N13	K12	K15	96	88	M13	M1	M14	M14	39	55	78	PB15	I/O	FT_h	-	RTC_REFIN, TIM1_CH3N, TIM12_CH2, USART1_RX, SPI2_MOSI/I2S2_SDO, UART4_CTS, SDMMC2_D1, LCD_G7, FMC_A20, EVENTOUT	PVD_IN
G8	H8	H8	H9	H9	K10	97	89	K10	-	K11	K11	40	56	79	VCAP2	S	-	-	-	-
-	-	-	-	-	G12	98	90	G6	-	J8	J12	41	57	80	VSS	S	-	-	-	-
F7	G7	G7	H8	H8	H8	99	91	H8	-	J9	J9	-	-	-	VDDLDO	S	-	-	-	-
-	-	-	-	-	-	100	92	-	-	-	-	42	58	81	VDD	S	-	-	-	-
-	H11	-	-	K13	K13	101	-	-	-	L14	L14	-	-	82	PD14	I/O	FT_h	-	LPTIM1_CH2, TIM4_CH3, LPTIM2_CH1, DCMIPP_D7, UCPD_FRSTX1, UART8_CTS, PSSI_D7, FMC_D17, EVENTOUT	-
-	-	-	-	J10	K14	102	-	-	-	L13	L13	-	-	83	PD15	I/O	FT_h	-	TIM4_CH4, LPTIM5_OUT, DCMIPP_D9, UCPD_FRSTX2, UART8_RTS/UART8_DE, PSSI_D9, FMC_D18, EVENTOUT	-
-	-	-	J10	-	-	-	-	-	-	L15	L15	-	-	-	PN12	I/O	FT_h	-	XSPIM_P2_NCS2	-
-	-	E10	G11	-	-	-	93	H10	-	H12	H12	-	-	-	VDDXSPI2	S	-	-	-	-
-	-	-	-	-	H6	-	94	G12	-	J12	K7	-	-	-	VSS	S	-	-	-	-
-	-	K12	M13	-	-	-	95	N15	-	K13	K13	-	-	-	PN8	I/O	FT_h	-	XSPIM_P2_IO4, FMC_D4/FMC_AD4	-
-	-	J11	L12	-	-	-	96	M14	-	K14	K14	-	-	-	PN4	I/O	FT_h	-	XSPIM_P2_IO2, FMC_D2/FMC_AD2	-
-	-	J12	L13	-	-	-	97	M15	-	K15	K15	-	-	-	PN5	I/O	FT_h	-	XSPIM_P2_IO3, FMC_D3/FMC_AD3	-
-	-	-	-	-	H7	-	98	H4	-	J15	K9	-	-	-	VSS	S	-	-	-	-
-	-	G10	H10	-	-	-	99	J12	-	J11	J11	-	-	-	VDDXSPI2	S	-	-	-	-
-	-	H11	K12	-	-	-	100	L14	-	J13	J13	-	-	-	PN7	I/O	FT_h	-	XSPIM_P2_NCLK, FMC_CLK	-
-	-	H12	K13	-	-	-	101	L15	-	J14	J14	-	-	-	PN6	I/O	FT_h	-	XSPIM_P2_CLK, FMC_SDCLK	-
-	-	G12	J12	-	-	-	102	K14	-	H14	H14	-	-	-	PN9	I/O	FT_h	-	XSPIM_P2_IO5, FMC_D5/FMC_AD5	-
-	-	G11	J13	-	-	-	103	K15	-	H15	H15	-	-	-	PN2	I/O	FT_h	-	XSPIM_P2_IO0, FMC_D0/FMC_AD0	-
-	-	-	-	-	H9	-	104	H6	-	K7	L6	-	-	-	VSS	S	-	-	-	-
-	-	J10	J11	-	-	-	105	L12	-	K12	K12	-	-	-	VDDXSPI2	S	-	-	-	-
-	-	F12	H12	-	-	-	106	J13	-	H13	H13	-	-	-	PN10	I/O	FT_h	-	XSPIM_P2_IO6, FMC_D6/FMC_AD6	-
-	-	F11	H13	-	-	-	107	J15	-	G14	G14	-	-	-	PN0	I/O	FT_h	-	XSPIM_P2_DQS0, FMC_NE4	-
-	-	E12	G12	-	-	-	108	J14	-	G15	G15	-	-	-	PN11	I/O	FT_h	-	XSPIM_P2_IO7, FMC_D7/FMC_AD7	-
-	-	E11	G13	-	-	-	109	H15	-	G13	G13	-	-	-	PN3	I/O	FT_h	-	XSPIM_P2_IO1, FMC_D1/FMC_AD1	-
-	-	-	-	-	H10	-	-	H7	-	K9	L11	-	-	-	VSS	S	-	-	-	-
-	-	-	-	-	-	-	110	-	-	-	-	-	-	-	VDDXSPI2	S	-	-	-	-
-	-	G9	G10	-	-	-	111	H14	-	F14	F14	-	-	-	PN1	I/O	FT_h	-	XSPIM_P2_NCS1, FMC_NBL0	-
-	H12	C12	F13	H10	J13	103	112	G15	-	E15	E15	-	-	84	PC6	I/O	FT_h	-	TIM3_CH1, TIM9_CH1, I2S2_MCK, SDMMC1_D0DIR, PSSI_D0, SDMMC2_D6, SDMMC1_D6, DCMIPP_D0, EVENTOUT	-
-	G9	D12	G9	G10	J14	104	113	G14	-	F13	F13	-	-	85	PC7	I/O	FT_h	-	TRGIO, TIM3_CH2, TIM9_CH2, I2S3_MCK, SDMMC1_D123DIR, PSSI_D1, SDMMC2_D7, SDMMC1_D7, DCMIPP_D1, EVENTOUT	-
-	G11	B12	F12	J11	J15	105	114	F15	-	D15	D15	-	-	86	PC8	I/O	FT_h	-	TRACED1, TIM3_CH3, I2C3_SMBA, UART5_RTS/UART5_DE, PSSI_D2, SDMMC1_D0, DCMIPP_D2, EVENTOUT	-
-	G10	D11	F10	G9	H14	106	115	G13	-	E14	E14	-	-	87	PC9	I/O	FT_fh	-	MCO2, TIM3_CH4, I2C3_SDA, I2S_CKIN, UART5_CTS, PSSI_D3, SDMMC1_D1, DCMIPP_D3, EVENTOUT	-
-	-	-	-	-	-	107	116	-	-	-	-	-	-	88	VDD	S	-	-	-	-
-	-	-	-	-	H12	108	-	H9	-	L6	M7	-	-	89	VSS	S	-	-	-	-
E8	F10	C11	E13	H12	G14	109	117	F14	K1	F12	F12	43	59	90	PA8	I/O	FT_fh	-	MCO1, TIM1_CH1, I2C3_SCL, USART1_CK, OTG_FS_SOF, UART7_RX, FMC_AD4/FMC_D4, LCD_B6, EVENTOUT	-
F10	G12	A11	D13	J12	H15	110	118	E15	J2	D14	D14	44	60	91	PA9	I/O	FT_fh	-	TIM1_CH2, LPUART1_TX, I2C3_SDA, SPI2_SCK/I2S2_CK, PSSI_D0, USART1_TX, FMC_AD3/FMC_D3, DCMIPP_D0, LCD_B5, EVENTOUT	-
E9	F11	D10	E12	F10	G13	111	119	F13	H1	E13	E13	45	61	92	PA10	I/O	FT_h	-	TIM1_CH3, LPUART1_RX, PSSI_D1, USART1_RX, MDIOS_MDIO, FMC_AD2/FMC_D2, DCMIPP_D1, LCD_B4, EVENTOUT	-
E10	F12	E9	C13	J13	G15	112	120	D15	K3	C15	C15	46	62	93	PA11	I/O	FT_h	-	TIM1_CH4, LPUART1_CTS, SPI2_NSS/I2S2_WS, UART4_RX, USART1_CTS/USART1_NSS, FDCAN1_RX, FMC_AD1/FMC_D1, LCD_B3, EVENTOUT	-
D9	E11	B11	D12	G12	F14	113	121	E14	J4	C14	C14	47	63	94	PA12	I/O	FT_h	-	TIM1_ETR, LPUART1_RTS/LPUART1_DE, SPI2_SCK/I2S2_CK, UART4_TX, USART1_RTS/USART1_DE, SAI2_FS_B, FDCAN1_TX, FMC_AD0/FMC_D0, LCD_B2, EVENTOUT	-
D10	E12	B10	B13	H13	F15	114	122	D14	H3	E12	E12	48	64	95	PA13(JTMS/SWDIO)	I/O	FT_h	Note(5)	JTMS-SWDIO, EVENTOUT	-
C9	E10	C10	C12	F12	F13	115	123	E13	G2	D13	D13	49	65	96	PA14(JTCK/SWCLK)	I/O	FT_h	Note(5)	JTCK-SWCLK, EVENTOUT	-
C10	D12	A10	A13	G13	E15	116	124	C15	F1	G11	G11	50	66	97	PA15(JTDI)	I/O	FT_h	Note(5)	JTDI, TIM2_CH1, TIM2_ETR, HDMI_CEC, SPI1_NSS/I2S1_WS, SPI3_NSS/I2S3_WS, SPI6_NSS/I2S6_WS, UART4_RTS/UART4_DE, UART7_TX, FMC_D15/FMC_AD15, LCD_R5, EVENTOUT	-
D8	F8	F8	F9	F9	G10	117	125	G10	D1	F11	F11	51	67	98	VCAP3	S	-	-	-	-
-	-	-	-	-	H13	118	126	H12	-	L11	M9	52	68	99	VSS	S	-	-	-	-
E6	F7	F7	F8	F8	G9	119	127	G9	E2	G9	G9	-	-	-	VDDLDO	S	-	-	-	-
-	-	-	-	-	-	120	128	-	B1	-	-	53	69	100	VDD	S	-	-	-	-
-	D11	A9	A12	F13	E14	121	129	D13	F3	B14	B14	-	70	101	PC10	I/O	FT_h	-	TIM1_BKIN, SPI3_SCK/I2S3_CK, USART3_TX, UART4_TX, PSSI_D14, SDMMC1_D2, DCMIPP_D14, EVENTOUT	-
-	E9	D9	E10	E12	E13	122	130	C14	G4	B15	B15	-	71	102	PC11	I/O	FT_h	-	SPI3_MISO/I2S3_SDI, USART3_RX, UART4_RX, PSSI_D4, SDMMC1_D3, DCMIPP_D4, EVENTOUT	-
-	C12	-	C11	E13	D15	123	131	B15	-	D12	D12	-	72	103	PC12	I/O	FT_h	-	TRACED3, TIM1_CH4, TIM15_CH1, SPI6_SCK/I2S6_CK, SPI3_MOSI/I2S3_SDO, USART3_CK, UART5_TX, PSSI_D9, SDMMC1_CK, DCMIPP_D9, EVENTOUT	-
-	-	B9	B12	E10	D14	124	132	B14	-	C13	C13	-	-	104	PD0	I/O	FT_h	-	PSSI_DE, FMC_A22, UART4_RX, FDCAN1_RX, FMC_A6, DCMIPP_HSYNC, EVENTOUT	-
-	-	-	B11	D13	C15	125	133	A14	-	B13	B13	-	-	105	PD1	I/O	FT_h	-	FMC_A23, UART4_TX, FDCAN1_TX, FMC_A7, EVENTOUT	-
-	C11	C9	E9	D12	D13	126	134	C13	-	A14	A14	-	-	106	PD2	I/O	FT_h	-	TRACED2, TIM1_ETR, TIM3_ETR, TIM15_BKIN, PSSI_D11, UART5_RX, SDMMC1_CMD, DCMIPP_D11, EVENTOUT	-
-	-	-	-	-	J6	-	-	J4	-	M9	N8	-	-	-	VSS	S	-	-	-	-
-	-	-	A11	C13	B15	127	135	A13	-	C12	C12	-	-	-	PE11	I/O	FT_h	-	TIM1_CH2, SPI4_NSS, SAI2_SD_B, LCD_VSYNC, FMC_SDNWE, EVENTOUT	-
-	-	-	E8	C12	C14	128	136	B13	-	E11	E11	-	-	-	PE12	I/O	FT_h	-	TIM1_CH3N, SPI4_SCK, SAI2_SCK_B, FMC_SDNRAS, EVENTOUT	-
-	-	-	A10	B13	B14	129	137	B12	-	B12	B12	-	-	-	PE13	I/O	FT_h	-	TIM1_CH3, SPI4_MISO, SAI2_FS_B, FMC_SDNCAS, EVENTOUT	-
-	-	-	D10	-	C13	130	138	C12	-	A13	A13	-	-	-	PE14	I/O	FT_h	-	TIM1_CH4, GFXTIM_FCKCAL, SPI4_MOSI, SAI2_MCLK_B, FMC_SDNE0, GFXTIM_LCKCAL, EVENTOUT	-
-	-	-	-	-	A14	131	139	A12	-	D11	D11	-	-	-	PE15	I/O	FT_h	-	TIM1_BKIN, GFXTIM_LCKCAL, FMC_SDCKE0, GFXTIM_FCKCAL, EVENTOUT	-
-	-	-	-	-	J8	132	140	J6	-	M15	R1	-	-	107	VSS	S	-	-	-	-
-	-	-	-	-	-	133	141	-	-	-	-	-	-	108	VDD	S	-	-	-	-
-	D10	B8	D9	C11	D12	134	142	C11	-	A12	A12	-	-	109	PD3	I/O	FT_h	-	TIM1_CH3N, SPI2_SCK/I2S2_CK, PSSI_D5, USART2_CTS/USART2_NSS, FMC_NWAIT, DCMIPP_D5, LCD_B1, EVENTOUT	-
-	B12	A8	B10	B12	A13	135	143	A11	-	C11	C11	-	-	110	PD4	I/O	FT_h	-	DCMIPP_HSYNC, PSSI_DE, USART2_RTS/USART2_DE, ETH_PHY_INTN, FMC_NL, EVENTOUT	TAMP_IN6/TAMP_OUT3
-	-	D8	D8	D10	B13	-	144	B11	-	B11	B11	-	-	-	PG0	I/O	FT_h	-	TIM1_CH4N, LCD_R7, EVENTOUT	-
-	-	C8	B9	A13	-	-	145	C10	-	E10	E10	-	-	-	PG1	I/O	FT_h	-	LCD_R6, EVENTOUT	-
C8	E8	-	-	E9	C12	136	-	-	D3	D10	D10	-	73	111	PM0	I/O	FT_uc	Note(4)	-	UCPD_CC1
B10	C10	-	-	B11	B12	137	-	-	E4	C10	C10	-	74	112	PM1	I/O	FT_uc	Note(4)	-	UCPD_CC2
A10	B10	-	-	A11	C11	138	-	-	H5	B10	B10	-	75	113	PM2	I/O	FT_ud	-	-	UCPD_DB1
B9	B11	-	-	A12	A12	139	-	-	F5	A10	A10	-	76	114	PM3	I/O	FT_ud	-	-	UCPD_DB2
-	-	-	-	-	J10	-	-	J8	-	P9	R6	-	-	-	VSS	S	-	-	-	-
C6	A11	A7	A9	B10	B11	140	146	C9	A2	D9	D9	-	77	115	VDD50USB	S	-	-	-	-
-	-	-	-	-	-	141	147	-	-	-	-	54	78	116	VDD33USB	S	-	-	-	-
D6	D8	-	-	D8	C10	142	-	J10	C4	E8	E8	-	79	117	VSSUSB	S	-	-	-	-
B8	B9	-	-	A10	B10	143	-	-	A4	B9	B9	-	80	118	PM5	I/O	FT_u	-	-	OTG_HS_DM
A8	A9	-	-	A9	A10	144	-	-	B5	A9	A9	-	81	119	PM6	I/O	FT_u	-	-	OTG_HS_DP
B7	C8	-	-	E8	C9	145	-	-	D5	D8	D8	-	82	120	DVDD	S	-	-	-	-
A9	B8	-	-	D9	A11	146	-	-	E6	C9	C9	-	83	121	PM8	I/O	FT_u	-	UART7_RX, OTG_HS_VBUS	-
A7	A8	-	-	C7	B9	147	-	-	C6	B8	B8	-	84	122	PM9	I/O	FT_u	-	UART7_TX, OTG_HS_ID	-
-	-	-	-	-	-	148	-	-	A8	-	-	-	85	123	VDD	S	-	-	-	-
-	-	-	-	-	K3	-	-	K6	-	R1	R9	-	-	-	VSS	S	-	-	-	-
A6	B7	A6	B8	B8	A8	149	148	B10	A6	A7	A7	55	86	124	PM12	I/O	FT_u	-	SPI5_NSS	OTG_FS_DM
B6	A7	B6	A8	A8	B8	150	149	A10	B7	B7	B7	56	87	125	PM11	I/O	FT_u	-	SPI5_SCK	OTG_FS_DP
A5	C7	E7	C7	B7	A9	151	150	A9	G6	C8	C8	57	88	126	PM14	I/O	FT_u	-	SPI5_MISO, OTG_FS_VBUS	-
B5	E6	D6	D7	D7	C8	152	151	B9	D7	C7	C7	58	89	127	PM13	I/O	FT_u	-	SPI5_MOSI, OTG_FS_ID	-
A4	A6	C6	E7	E7	C7	153	152	B8	F7	A6	A6	59	90	128	BOOT0	I	B	-	-	[VPP]
-	B6	A5	A7	A7	A7	154	153	A8	-	D7	D7	-	-	129	PD5	I/O	FT_h	-	TIM1_CH4N, DCMIPP_PIXCLK, PSSI_PDCK, USART2_TX, FMC_NCE, FMC_NE2, EVENTOUT	TAMP_IN5/TAMP_OUT4
-	C6	B5	B7	B6	B7	155	154	B7	-	E7	E7	-	-	130	PD6	I/O	FT_h	-	SAI1_D1, ADF1_SDI0, ETH_CLK, SPI3_MOSI/I2S3_SDO, SAI1_SCK_A, USART2_RX, PSSI_D10, FMC_INT, SDMMC2_CK, FMC_NE3, DCMIPP_D10, EVENTOUT	-
-	A5	A4	A6	A6	A6	156	155	A7	C8	B6	B6	-	-	131	PD7	I/O	FT_h	-	ETH_MII_RX_CLK/ETH_RMII_REF_CLK, SPI1_MOSI/I2S1_SDO, PSSI_D2, USART2_CK, SPDIFRX_IN0, SDMMC2_CMD, FMC_D8/FMC_AD8, DCMIPP_D2, EVENTOUT	-
-	-	-	B6	-	-	-	156	C7	-	C6	C6	-	-	-	PG2	I/O	FT_h	-	LCD_HSYNC, EVENTOUT	-
-	-	-	-	-	-	-	-	A6	-	A5	A5	-	-	-	PG3	I/O	FT_h	-	DCMIPP_HSYNC, PSSI_DE, ETH_PPS_OUT, FMC_D21, EVENTOUT	-
-	-	-	-	-	K6	-	-	K8	-	R6	R12	-	-	132	VSS	S	-	-	-	-
-	-	-	-	-	-	157	157	-	-	-	-	-	-	133	VDD	S	-	-	-	-
-	-	-	D6	D6	B6	158	158	B6	-	B5	B5	-	-	-	PF0	I/O	FT_fh	-	I2C2_SDA, LCD_R2, FMC_A8, EVENTOUT	-
-	-	-	A5	A5	A5	159	159	A5	-	C5	C5	-	-	-	PF1	I/O	FT_fh	-	I2C2_SCL, FMC_A9, EVENTOUT	-
-	-	-	B5	B5	C6	160	160	C6	-	A4	A4	-	-	-	PF2	I/O	FT_h	-	I2C2_SMBA, DCMIPP_D14, PSSI_D14, FMC_A10, EVENTOUT	-
-	-	-	-	-	A4	161	161	A4	-	A3	A3	-	-	-	PF3	I/O	FT_h	-	DCMIPP_D9, PSSI_D9, ETH_MII_CRS, FMC_A11, EVENTOUT	-
-	-	-	-	-	B5	162	162	B5	-	B4	B4	-	-	-	PF4	I/O	FT_h	-	DCMIPP_D8, PSSI_D8, ETH_MII_TX_ER, FMC_A13, EVENTOUT	-
A3	B5	C5	A4	A4	B4	163	163	B4	E8	C4	C4	60	91	134	PB3(JTDO/TRACESWO)	I/O	FT_h	-	JTDO-SWO, TIM2_CH2, LPTIM4_IN1, DCMIPP_HSYNC, SPI1_SCK/I2S1_CK, SPI3_SCK/I2S3_CK, SPI6_SCK/I2S6_CK, SDMMC2_D2, CRS_SYNC, UART7_RX, FMC_D14/FMC_AD14, LCD_R4, PSSI_DE, EVENTOUT	-
B4	C5	E6	E6	E6	C5	164	164	C5	H7	D5	D5	61	92	135	PB4(NJTRST)	I/O	FT_h	Note(5)	NJTRST, TIM16_BKIN, TIM3_CH1, LPTIM4_ETR, DCMIPP_VSYNC, SPI1_MISO/I2S1_SDI, SPI3_MISO/I2S3_SDI, SPI2_NSS/I2S2_WS, SPI6_MISO/I2S6_SDI, SDMMC2_D3, UART7_TX, FMC_D13/FMC_AD13, LCD_R3, PSSI_RDY, EVENTOUT	-
D4	A4	B4	B4	B4	A3	165	165	A3	D9	B3	B3	62	93	136	PB5	I/O	FT_h	-	TIM17_BKIN, TIM3_CH2, LPTIM4_OUT, I2C1_SMBA, SPI1_MOSI/I2S1_SDO, PSSI_D10, SPI3_MOSI/I2S3_SDO, SPI6_MOSI/I2S6_SDO, FDCAN2_RX, LCD_R2, ETH_PPS_OUT, FMC_D12/FMC_AD12, DCMIPP_D10, UART5_RX, EVENTOUT	-
C4	E5	E5	E5	E5	F6	166	166	F6	A10	E6	E6	63	94	137	VCAP4	S	-	-	-	-
-	-	-	-	-	K8	167	167	K12	-	R12	R15	64	95	138	VSS	S	-	-	-	-
E5	F6	F6	F6	F6	G7	168	168	G7	C10	G7	G7	-	-	-	VDDLDO	S	-	-	-	-
-	-	-	-	-	-	169	169	-	-	-	-	65	96	139	VDD	S	-	-	-	-
-	B4	-	A3	A3	C4	170	170	C4	-	A2	A2	-	-	140	PE0	I/O	FT_h	-	LPTIM1_ETR, TIM4_ETR, LPTIM2_ETR, UART8_RX, PSSI_D2, SAI2_MCLK_A, FMC_D9/FMC_AD9, DCMIPP_D2, EVENTOUT	TAMP_IN4/TAMP_OUT5
-	B3	B3	D5	D5	B2	171	171	B2	-	C3	C3	-	-	141	PE1	I/O	FT_h	-	LPTIM1_IN2, LPTIM2_CH2, UART8_TX, PSSI_D3, FMC_D10/FMC_AD10, DCMIPP_D3, EVENTOUT	TAMP_IN3/TAMP_OUT6
-	C4	D5	B3	B3	B3	172	172	B3	-	B2	B2	-	-	142	PE2	I/O	FT_h	-	TRACECLK, ADF1_CCK0, SAI1_CK1, LPTIM5_IN1, SPI4_SCK, SAI1_MCLK_A, ETH_MII_TXD3, FMC_D11/FMC_AD11, TIM1_CH2N, EVENTOUT	-
A2	A3	A3	A2	A2	A2	173	173	A2	F9	E5	E5	-	97	143	PB6	I/O	FT_fh	-	TIM16_CH1N, TIM4_CH1, I2C1_SCL/I3C1_SCL, HDMI_CEC, PSSI_D5, USART1_TX, LPUART1_TX, FDCAN2_TX, ETH_MII_RX_CLK/ETH_RMII_REF_CLK, FMC_SDNE1, DCMIPP_D5, UART5_TX, EVENTOUT	-
B3	D4	C4	B2	B2	C3	174	174	C3	G8	D4	D4	66	98	144	PB7	I/O	FT_fh	-	TIM17_CH1N, TIM4_CH2, I2C1_SDA/I3C1_SDA, DCMIPP_D1, PSSI_RDY, USART1_RX, LPUART1_RX, PSSI_D1, ETH_MII_TXD1/ETH_RMII_TXD1, FMC_SDCKE1, DCMIPP_VSYNC, UART5_TX, EVENTOUT	-
A1	A2	A2	A1	A1	B1	175	175	B1	J8	B1	B1	67	99	1	PB8	I/O	FT_fh	-	TIM16_CH1, TIM4_CH3, USART3_CK, I2C1_SCL/I3C1_SCL, PSSI_D6, SDMMC1_CKIN, UART4_RX, FDCAN1_RX, SDMMC2_D4, ETH_MII_TXD3, SDMMC1_D4, DCMIPP_D6, FMC_D9/FMC_AD9, EVENTOUT	-
-	-	-	-	-	J9	-	-	J9	-	-	-	-	-	-	VDDLDO	S	-	-	-	-
D7	A10	B7	C8	C8	D9	-	-	D9	B3	F8	F8	-	-	-	VDD33USB	S	-	-	-	-
-	-	-	-	-	K12	-	-	L1	-	R15	-	-	-	-	VSS	S	-	-	-	-
-	-	-	-	-	J4	-	-	H13	-	M8	M15	-	-	-	VSS	S	-	-	-	-
-	-	-	-	-	H4	-	-	G8	-	J10	J15	-	-	-	VSS	S	-	-	-	-
-	K6	H10	J2	H11	F7	-	-	E12	-	G12	G12	-	-	-	VSS	S	-	-	-	-
H6	F5	F10	G6	F11	E1	-	-	D11	-	E9	E9	-	-	-	VSS	-	-	-	-	-
-	-	-	-	-	R15	-	-	R15	-	-	-	-	-	-	VSS	S	-	-	-	-
-	-	-	-	-	R1	-	-	R1	-	-	-	-	-	-	VSS	S	-	-	-	-
-	-	-	-	-	N10	-	-	N10	-	-	-	-	-	-	VSS	S	-	-	-	-
-	-	-	-	-	M11	-	-	M11	-	-	-	-	-	-	VSS	S	-	-	-	-
-	-	-	-	-	M9	-	-	M9	-	-	-	-	-	-	VSS	S	-	-	-	-
-	-	-	-	-	M7	-	-	M7	-	-	-	-	-	-	VSS	S	-	-	-	-
-	-	-	-	-	L3	-	-	L3	-	-	-	-	-	-	VSS	S	-	-	-	-
-	-	-	-	-	L1	-	-	-	-	-	-	-	-	-	VSS	S	-	-	-	-

Table 26 (pages 128–146)

Table 26 · 18 columns × 161 rows · p.128–146 · CSV

Port		AF0	AF1	AF2	AF3	AF4	AF5	AF6	AF7	AF8	AF9	AF10	AF11	AF12	AF13	AF14	AF15
Port		SYS	ADF1/LPTIM1/TIM1/2/16/17	GFXTIM/PDM_SAI1/TIM2/3/4/5/12/15	ADF1/LPTIM2/3/4/5/LPUART1/TIM9/USART3	CEC/DCMIPP/ETH/I2C/I3C/I2C2/3/TIM15/USART1	CEC/DCMIPP/SPI1/I2S1/SPI2/I2S2/SPI3/I2S3/SPI4/5/SPI6/I2S6	PSSI_/SAI1/SDMMC1/SPI3/I2S3/SPI4/UART4/UCPD	FMC/SDMMC1/SPI2/I2S2/SPI3/I2S3/SPI6/I2S6/UART7/USART1/2/3	GFXTIM/LPUART1/PSSI_/SAI2/SDMMC1/SPDIFRX/SPI6/I2S6/UART4/5/8	FDCAN1/2/FMC/OCTOSPIM_P1/2/PSSI_/SDMMC2/SPDIFRX/SPI5/TIM13/14	CRS/FMC/LCD/OTG1_FS/OTG1_HS/SAI2/SDMMC2/SPI1/I2S1	ETH/LCD/MDIOS/SDMMC1/2/UART7	FMC/GFXTIM/LCD/SDMMC1	DCMIPP/GFXTIM/LCD	FMC/LCD/MDIOS/PSSI_/TIM1/UART5	SYS
Port A	PA0	-	TIM2_CH1	TIM5_CH1	TIM9_CH1	TIM15_BKIN	SPI6_NSS/I2S6_WS	-	USART2_CTS/USART2_NSS	UART4_TX	SDMMC2_CMD	SAI2_SD_B	-	FMC_AD7/FMC_D7	LCD_G3	-	EVENTOUT
Port A	PA1	-	TIM2_CH2	TIM5_CH2	LPTIM3_IN1	TIM15_CH1N	DCMIPP_D0	PSSI_D0	USART2_RTS/USART2_DE	UART4_RX	-	SAI2_MCLK_B	ETH_MII_RX_CLK/ETH_RMII_REF_CLK	FMC_AD6/FMC_D6	LCD_G2	-	EVENTOUT
Port A	PA2	-	TIM2_CH3	TIM5_CH3	LPTIM3_IN2	TIM15_CH1	-	-	USART2_TX	SAI2_SCK_B	-	-	ETH_MDIO	FMC_AD5/FMC_D5	LCD_B7	MDIOS_MDIO	EVENTOUT
Port A	PA3	-	TIM2_CH4	TIM5_CH4	LPTIM3_CH1	TIM15_CH2	I2S6_MCK	SPI4_RDY	USART2_RX	GFXTIM_LCKCAL	SPI5_RDY	SPI1_RDY	ETH_MII_COL	GFXTIM_FCKCAL	LCD_DE	TIM1_CH3	EVENTOUT
Port A	PA4	-	-	TIM5_ETR	LPTIM3_CH2	-	SPI1_NSS/I2S1_WS	SPI3_NSS/I2S3_WS	USART2_CK	SPI6_NSS/I2S6_WS	PSSI_DE	OTG_HS_SOF	ETH_MDIO	LCD_R3	DCMIPP_HSYNC	-	EVENTOUT
Port A	PA5	PWR_CSTOP	TIM2_CH1	TIM2_ETR	TIM9_CH2	-	SPI1_SCK/I2S1_CK	PSSI_D8	-	SPI6_SCK/I2S6_CK	-	-	-	FMC_NOE	DCMIPP_D8	LCD_CLK	EVENTOUT
Port A	PA6	PWR_CSLEEP	TIM1_BKIN	TIM3_CH1	LPTIM3_ETR	-	SPI1_MISO/I2S1_SDI	PSSI_PDCK	-	SPI6_MISO/I2S6_SDI	TIM13_CH1	-	MDIOS_MDC	LCD_B7	DCMIPP_PIXCLK	LCD_HSYNC	EVENTOUT
Port A	PA7	-	TIM1_CH1N	TIM3_CH2	-	-	SPI1_MOSI/I2S1_SDO	-	-	SPI6_MOSI/I2S6_SDO	TIM14_CH1	LCD_R4	ETH_MII_RX_DV/ETH_RMII_CRS_DV	FMC_INT	LCD_B1	-	EVENTOUT
Port A	PA8	MCO1	TIM1_CH1	-	-	I2C3_SCL	-	-	USART1_CK	-	-	OTG_FS_SOF	UART7_RX	FMC_AD4/FMC_D4	LCD_B6	-	EVENTOUT
Port A	PA9	-	TIM1_CH2	-	LPUART1_TX	I2C3_SDA	SPI2_SCK/I2S2_CK	PSSI_D0	USART1_TX	-	-	-	-	FMC_AD3/FMC_D3	DCMIPP_D0	LCD_B5	EVENTOUT
Port A	PA10	-	TIM1_CH3	-	LPUART1_RX	-		PSSI_D1	USART1_RX	-	-	-	MDIOS_MDIO	FMC_AD2/FMC_D2	DCMIPP_D1	LCD_B4	EVENTOUT
Port A	PA11	-	TIM1_CH4	-	LPUART1_CTS	-	SPI2_NSS/I2S2_WS	UART4_RX	USART1_CTS/USART1_NSS	-	FDCAN1_RX	-	-	FMC_AD1/FMC_D1	LCD_B3	-	EVENTOUT
Port A	PA12	-	TIM1_ETR	-	LPUART1_RTS/LPUART1_DE	-	SPI2_SCK/I2S2_CK	UART4_TX	USART1_RTS/USART1_DE	SAI2_FS_B	FDCAN1_TX	-	-	FMC_AD0/FMC_D0	LCD_B2	-	EVENTOUT
Port A	PA13	JTMS-SWDIO	-	-	-	-	-	-	-	-	-	-	-	-	-	-	EVENTOUT
Port A	PA14	JTCK-SWCLK	-	-	-	-	-	-	-	-	-	-	-	-	-	-	EVENTOUT
Port A	PA15	JTDI	TIM2_CH1	TIM2_ETR	-	HDMI_CEC	SPI1_NSS/I2S1_WS	SPI3_NSS/I2S3_WS	SPI6_NSS/I2S6_WS	UART4_RTS/UART4_DE	-	-	UART7_TX	FMC_D15/FMC_AD15	LCD_R5	-	EVENTOUT
Port B	PB0	-	TIM1_CH2N	TIM3_CH3	TIM9_CH1	-	SPI1_SCK/I2S1_CK	-	-	UART4_CTS	-	-	ETH_MII_TXD0/ETH_RMII_TXD0	GFXTIM_TE	-	LCD_VSYNC	EVENTOUT
Port B	PB1	-	TIM1_CH3N	TIM3_CH4	TIM9_CH2	-	-	-	-	-	FDCAN2_TX	LCD_G2	ETH_MII_TXD1/ETH_RMII_TXD1	FMC_NOE	-	-	EVENTOUT
Port B	PB2	RTC_OUT2	-	SAI1_D1	ADF1_SDI0	-	-	SAI1_SD_A	SPI3_MOSI/I2S3_SDO	-	-	LCD_B2		FMC_NWE	-	-	EVENTOUT
Port B	PB3	JTDO-SWO	TIM2_CH2	-	LPTIM4_IN1	DCMIPP_HSYNC	SPI1_SCK/I2S1_CK	SPI3_SCK/I2S3_CK	-	SPI6_SCK/I2S6_CK	SDMMC2_D2	CRS_SYNC	UART7_RX	FMC_D14/FMC_AD14	LCD_R4	PSSI_DE	EVENTOUT
Port B	PB4	NJTRST	TIM16_BKIN	TIM3_CH1	LPTIM4_ETR	DCMIPP_VSYNC	SPI1_MISO/I2S1_SDI	SPI3_MISO/I2S3_SDI	SPI2_NSS/I2S2_WS	SPI6_MISO/I2S6_SDI	SDMMC2_D3	-	UART7_TX	FMC_D13/FMC_AD13	LCD_R3	PSSI_RDY	EVENTOUT
Port B	PB5	-	TIM17_BKIN	TIM3_CH2	LPTIM4_OUT	I2C1_SMBA	SPI1_MOSI/I2S1_SDO	PSSI_D10	SPI3_MOSI/I2S3_SDO	SPI6_MOSI/I2S6_SDO	FDCAN2_RX	LCD_R2	ETH_PPS_OUT	FMC_D12/FMC_AD12	DCMIPP_D10	UART5_RX	EVENTOUT
Port B	PB6	-	TIM16_CH1N	TIM4_CH1	-	I2C1_SCL/I3C1_SCL	HDMI_CEC	PSSI_D5	USART1_TX	LPUART1_TX	FDCAN2_TX	-	ETH_MII_RX_CLK/ETH_RMII_REF_CLK	FMC_SDNE1	DCMIPP_D5	UART5_TX	EVENTOUT
Port B	PB7	-	TIM17_CH1N	TIM4_CH2	-	I2C1_SDA/I3C1_SDA	DCMIPP_D1	PSSI_RDY	USART1_RX	LPUART1_RX	PSSI_D1	-	ETH_MII_TXD1/ETH_RMII_TXD1	FMC_SDCKE1	DCMIPP_VSYNC	UART5_TX	EVENTOUT
Port B	PB8	-	TIM16_CH1	TIM4_CH3	USART3_CK	I2C1_SCL/I3C1_SCL	-	PSSI_D6	SDMMC1_CKIN	UART4_RX	FDCAN1_RX	SDMMC2_D4	ETH_MII_TXD3	SDMMC1_D4	DCMIPP_D6	FMC_D9/FMC_AD9	EVENTOUT
Port B	PB9	-	TIM17_CH1	TIM4_CH4	-	I2C1_SDA/I3C1_SDA	SPI2_NSS/I2S2_WS	PSSI_D7	SDMMC1_CDIR	UART4_TX	FDCAN1_TX	SDMMC2_D5	-	SDMMC1_D5	DCMIPP_D7	-	EVENTOUT
Port B	PB10	-	TIM2_CH3	-	LPTIM2_IN1	I2C2_SCL	SPI2_SCK/I2S2_CK	-	USART3_TX	-	-	-	ETH_MII_RX_ER	FMC_D11/FMC_AD11	LCD_G7	-	EVENTOUT
Port B	PB11	-	TIM2_CH4	-	LPTIM2_ETR	I2C2_SDA	-	-	USART3_RX	-	-	-	ETH_MII_TX_EN/ETH_RMII_TX_EN	FMC_D10/FMC_AD10	LCD_G6	-	EVENTOUT
Port B	PB12	-	TIM1_BKIN	-	LPTIM2_IN2	I2C2_SMBA	SPI2_NSS/I2S2_WS	-	USART3_CK	-	FDCAN2_RX	-	-	FMC_D9/FMC_AD9	LCD_G5	UART5_RX	EVENTOUT
Port B	PB13	-	TIM1_CH1N	-	LPTIM2_CH1	-	SPI2_SCK/I2S2_CK	SDMMC1_D0	USART3_CTS/USART3_NSS	PSSI_D2	FDCAN2_TX	LCD_G4	ETH_MII_RXD3	FMC_D8/FMC_AD8	DCMIPP_D2	UART5_TX	EVENTOUT
Port B	PB14	-	TIM1_CH2N	TIM12_CH1	LPTIM2_CH2	USART1_TX	SPI2_MISO/I2S2_SDI	-	USART3_RTS/USART3_DE	UART4_RTS/UART4_DE	SDMMC2_D0	-	-	FMC_NE1	LCD_DE	-	EVENTOUT
Port B	PB15	RTC_REFIN	TIM1_CH3N	TIM12_CH2	-	USART1_RX	SPI2_MOSI/I2S2_SDO	-	-	UART4_CTS	SDMMC2_D1	LCD_G7	-	FMC_A20	-	-	EVENTOUT
Port C	PC0	-	-	GFXTIM_FCKCAL	-	-	-	-	-	SAI2_FS_B	-	-	-	FMC_NBL1	GFXTIM_LCKCAL	-	EVENTOUT
Port C	PC1	TRACED0	-	SAI1_D1	ADF1_SDI0	-	SPI2_MOSI/I2S2_SDO	SAI1_SD_A	FMC_A16	-	SDMMC2_CK	-	ETH_MDC	FMC_A0	-	MDIOS_MDC	EVENTOUT
Port C	PC2	-	TIM1_CH1	-	-	-	SPI2_MISO/I2S2_SDI	-	-	-	FMC_A17	-	ETH_MII_TXD2	FMC_A1	-	-	EVENTOUT
Port C	PC3	-	TIM1_CH2	-	-	-	SPI2_MOSI/I2S2_SDO	-	FMC_A18	-	-	-	ETH_MII_TX_CLK	FMC_A2	-	-	EVENTOUT
Port C	PC4	-	-	-	-	-	I2S1_MCK	-	FMC_A19	-	SPDIFRX_IN2	-	ETH_MII_RXD0/ETH_RMII_RXD0	FMC_A3	-	-	EVENTOUT
Port C	PC5	-	-	SAI1_D3	-	DCMIPP_D15	-	PSSI_D15	FMC_A21	-	SPDIFRX_IN3	-	ETH_MII_RXD1/ETH_RMII_RXD1	FMC_A5	-	-	EVENTOUT
Port C	PC6	-	-	TIM3_CH1	TIM9_CH1	-	I2S2_MCK	-	-	SDMMC1_D0DIR	PSSI_D0	SDMMC2_D6	SDMMC1_D6	-	DCMIPP_D0	-	EVENTOUT
Port C	PC7	TRGIO	-	TIM3_CH2	TIM9_CH2	-	-	I2S3_MCK	-	SDMMC1_D123DIR	PSSI_D1	SDMMC2_D7	SDMMC1_D7	-	DCMIPP_D1	-	EVENTOUT
Port C	PC8	TRACED1	-	TIM3_CH3	-	I2C3_SMBA	-	-	-	UART5_RTS/UART5_DE	PSSI_D2	-	SDMMC1_D0	-	DCMIPP_D2	-	EVENTOUT
Port C	PC9	MCO2	-	TIM3_CH4	-	I2C3_SDA	I2S_CKIN	-	-	UART5_CTS	PSSI_D3	-	SDMMC1_D1	-	DCMIPP_D3	-	EVENTOUT
Port C	PC10	-	TIM1_BKIN	-	-	-	-	SPI3_SCK/I2S3_CK	USART3_TX	UART4_TX	PSSI_D14	-	-	SDMMC1_D2	DCMIPP_D14	-	EVENTOUT
Port C	PC11	-		-	-	-	-	SPI3_MISO/I2S3_SDI	USART3_RX	UART4_RX	PSSI_D4	-	SDMMC1_D3	-	DCMIPP_D4	-	EVENTOUT
Port C	PC12	TRACED3	TIM1_CH4	TIM15_CH1	-	-	SPI6_SCK/I2S6_CK	SPI3_MOSI/I2S3_SDO	USART3_CK	UART5_TX	PSSI_D9	-	SDMMC1_CK	-	DCMIPP_D9	-	EVENTOUT
Port C	PC13	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	EVENTOUT
Port C	PC14	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	EVENTOUT
Port C	PC15	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	EVENTOUT
Port D	PD0	-	-	-	-	-	-	PSSI_DE	FMC_A22	UART4_RX	FDCAN1_RX	-	-	FMC_A6	DCMIPP_HSYNC	-	EVENTOUT
Port D	PD1	-	-	-	-	-	-	-	FMC_A23	UART4_TX	FDCAN1_TX	-	-	FMC_A7	-	-	EVENTOUT
Port D	PD2	TRACED2	TIM1_ETR	TIM3_ETR	-	TIM15_BKIN		PSSI_D11		UART5_RX			SDMMC1_CMD		DCMIPP_D11	-	EVENTOUT
Port D	PD3	-	TIM1_CH3N	-	-	-	SPI2_SCK/I2S2_CK	PSSI_D5	USART2_CTS/USART2_NSS	-	-	-		FMC_NWAIT	DCMIPP_D5	LCD_B1	EVENTOUT
Port D	PD4	-	-	-	-	-	DCMIPP_HSYNC	PSSI_DE	USART2_RTS/USART2_DE	-	-	-	ETH_PHY_INTN	FMC_NL	-	-	EVENTOUT
Port D	PD5	-	TIM1_CH4N	-	-	-	DCMIPP_PIXCLK	PSSI_PDCK	USART2_TX	-	-	FMC_NCE	-	FMC_NE2	-	-	EVENTOUT
Port D	PD6	-	-	SAI1_D1	ADF1_SDI0	ETH_CLK	SPI3_MOSI/I2S3_SDO	SAI1_SCK_A	USART2_RX	-	PSSI_D10	FMC_INT	SDMMC2_CK	FMC_NE3	DCMIPP_D10	-	EVENTOUT
Port D	PD7	-	-	-	-	ETH_MII_RX_CLK/ETH_RMII_REF_CLK	SPI1_MOSI/I2S1_SDO	PSSI_D2	USART2_CK	-	SPDIFRX_IN0	-	SDMMC2_CMD	FMC_D8/FMC_AD8	DCMIPP_D2	-	EVENTOUT
Port D	PD8	-	-	-	-	-	-	-	USART3_TX	-	SPDIFRX_IN1	-	ETH_MII_TX_EN/ETH_RMII_TX_EN	FMC_NBL0	LCD_R0	-	EVENTOUT
Port D	PD9	-	-	-	-	-	-	-	USART3_RX	-	-	-	-	FMC_SDCLK	LCD_R1	-	EVENTOUT
Port D	PD10	-	TIM1_CH4	-	-	-	DCMIPP_D4	SPI4_RDY	USART3_CK	PSSI_D4	SPI5_RDY	SPI1_RDY	-	FMC_CLK	LCD_B0	-	EVENTOUT
Port D	PD11	-	TIM1_ETR	-	LPTIM2_IN2	-	DCMIPP_D6	-	USART3_CTS/USART3_NSS	PSSI_D6	-	SAI2_SD_A	-	FMC_D16	-	-	EVENTOUT
Port D	PD12	-	LPTIM1_IN1	TIM4_CH1	LPTIM2_IN1	-	-	-	USART3_RTS/USART3_DE	-	PSSI_D12	SAI2_FS_A	-	FMC_NE1	DCMIPP_D12	LCD_DE	EVENTOUT
Port D	PD13	-	LPTIM1_CH1	TIM4_CH2	-	-	-	UCPD_FRSTX2	-	SAI2_SCK_A	PSSI_D13	FMC_INT	-		DCMIPP_D13	-	EVENTOUT
Port D	PD14	-	LPTIM1_CH2	TIM4_CH3	LPTIM2_CH1	-	DCMIPP_D7	UCPD_FRSTX1	-	UART8_CTS	PSSI_D7	-	-	FMC_D17	-	-	EVENTOUT
Port D	PD15	-	-	TIM4_CH4	LPTIM5_OUT	-	DCMIPP_D9	UCPD_FRSTX2	-	UART8_RTS/UART8_DE	PSSI_D9	-	-	FMC_D18	-	-	EVENTOUT
Port E	PE0	-	LPTIM1_ETR	TIM4_ETR	LPTIM2_ETR	-	-	-	-	UART8_RX	PSSI_D2	SAI2_MCLK_A	-	FMC_D9/FMC_AD9	DCMIPP_D2	-	EVENTOUT
Port E	PE1	-	LPTIM1_IN2	-	LPTIM2_CH2	-	-	-	-	UART8_TX	PSSI_D3	-	-	FMC_D10/FMC_AD10	DCMIPP_D3	-	EVENTOUT
Port E	PE2	TRACECLK	ADF1_CCK0	SAI1_CK1	LPTIM5_IN1	-	SPI4_SCK	SAI1_MCLK_A		-	-	-	ETH_MII_TXD3	FMC_D11/FMC_AD11	-	TIM1_CH2N	EVENTOUT
Port E	PE3	TRACED0	-	-	LPTIM5_ETR	TIM15_BKIN		SAI1_SD_B	-	-	-	-	ETH_MII_RXD3	FMC_D12/FMC_AD12	-	-	EVENTOUT
Port E	PE4	TRACED1	-	SAI1_D2	ADF1_SDI0	TIM15_CH1N	SPI4_NSS	SAI1_FS_A	-	-	PSSI_D4		-	FMC_D13/FMC_AD13	DCMIPP_D4	-	EVENTOUT
Port E	PE5	TRACED2	ADF1_CCK1	SAI1_CK2		TIM15_CH1	SPI4_MISO	SAI1_SCK_A	-	-	PSSI_D6		-	FMC_D14/FMC_AD14	DCMIPP_D6	-	EVENTOUT
Port E	PE6	TRACED3	TIM1_BKIN2	SAI1_D1	ADF1_SDI0	TIM15_CH2	SPI4_MOSI	SAI1_SD_A	-	-	PSSI_D7	SAI2_MCLK_B	-	FMC_D15/FMC_AD15	DCMIPP_D7	-	EVENTOUT
Port E	PE7	-	TIM1_ETR	-	-	-	-	-	UART7_RX	-	FMC_A20	SAI2_SD_B	-	FMC_A4	-	-	EVENTOUT
Port E	PE8	-	TIM1_CH1N	-	-	-	-	-	UART7_TX	-	-	-	-	FMC_A12	-	-	EVENTOUT
Port E	PE9	-	TIM1_CH1	-	-	-	-	-	UART7_RTS/UART7_DE	-	-	-	-	FMC_A14	-	FMC_BA0	EVENTOUT
Port E	PE10	-	TIM1_CH2N	-	-	-	-	-	UART7_CTS	-	-	-	-	FMC_A15	-	FMC_BA1	EVENTOUT
Port E	PE11	-	TIM1_CH2	-	-	-	SPI4_NSS	-	-	-	-	SAI2_SD_B	LCD_VSYNC	FMC_SDNWE	-	-	EVENTOUT
Port E	PE12	-	TIM1_CH3N	-	-	-	SPI4_SCK	-	-	-	-	SAI2_SCK_B	-	FMC_SDNRAS	-	-	EVENTOUT
Port E	PE13	-	TIM1_CH3	-	-	-	SPI4_MISO	-	-	-	-	SAI2_FS_B	-	FMC_SDNCAS	-	-	EVENTOUT
Port E	PE14	-	TIM1_CH4	GFXTIM_FCKCAL	-	-	SPI4_MOSI	-	-	-	-	SAI2_MCLK_B	-	FMC_SDNE0	GFXTIM_LCKCAL	-	EVENTOUT
Port E	PE15	-	TIM1_BKIN	GFXTIM_LCKCAL	-	-	-	-	-	-	-	-	-	FMC_SDCKE0	GFXTIM_FCKCAL	-	EVENTOUT
Port F	PF0	-	-	-	-	I2C2_SDA	-	-	-	-	-	-	LCD_R2	FMC_A8	-	-	EVENTOUT
Port F	PF1	-	-	-	-	I2C2_SCL	-	-	-	-	-	-		FMC_A9	-	-	EVENTOUT
Port F	PF2	-	-	-	-	I2C2_SMBA	DCMIPP_D14	-	-	-	PSSI_D14	-	-	FMC_A10	-	-	EVENTOUT
Port F	PF3	-	-	-	-	-	DCMIPP_D9	-	-	-	PSSI_D9	-	ETH_MII_CRS	FMC_A11	-	-	EVENTOUT
Port F	PF4	-	-	-	-	-	DCMIPP_D8	-	-	-	PSSI_D8	-	ETH_MII_TX_ER	FMC_A13	-	-	EVENTOUT
Port F	PF5	-	-	-	-	-	DCMIPP_D15	UCPD_FRSTX1	-	-	PSSI_D15	FMC_CLE	ETH_MII_RXD2	FMC_A16	-	-	EVENTOUT
Port F	PF6	-	TIM16_CH1	-	-	-	SPI5_NSS	SAI1_SD_B	UART7_RX	-	-	FMC_ALE		FMC_A17	-	-	EVENTOUT
Port F	PF7	-	TIM17_CH1	-	-	-	SPI5_SCK	SAI1_MCLK_B	UART7_TX	-	-	-	-	FMC_A18	LCD_G0	-	EVENTOUT
Port F	PF8	-	TIM16_CH1N	-	-	DCMIPP_PIXCLK	SPI5_MISO	SAI1_SCK_B	UART7_RTS/UART7_DE	PSSI_PDCK	TIM13_CH1	-	-	FMC_A19	LCD_G1	-	EVENTOUT
Port F	PF9	-	TIM17_CH1N	-	-	-	SPI5_MOSI	SAI1_FS_B	UART7_CTS	-	TIM14_CH1	-	-	FMC_A21	LCD_R0	-	EVENTOUT
Port F	PF10	-	TIM16_BKIN	SAI1_D3	-	DCMIPP_D15	-	PSSI_D15	-	-	PSSI_D11	-	-	FMC_A22	DCMIPP_D11	LCD_R1	EVENTOUT
Port F	PF11	-	-	-	-	-	SPI5_MOSI	-	-	-	PSSI_D12	SAI2_SD_B	-	FMC_A23	DCMIPP_D12	LCD_B0	EVENTOUT
Port F	PF12	-	-	-	-	USART1_RX	SPI5_MISO	-	-	-	-	-	-	FMC_D19	-	-	EVENTOUT
Port F	PF13	-	-	-	-	USART1_TX	SPI5_NSS	-	-	-	PSSI_D10	-	-	FMC_D20	DCMIPP_D10	-	EVENTOUT
Port F	PF14	-	-	-	-	USART1_CTS	SPI5_MOSI	-	-	-	-	-	-	FMC_A24	LCD_G0	-	EVENTOUT
Port F	PF15	-	-	-	-	USART1_RTS/USART1_DE	SPI5_SCK	-	-	-	-	-	-	FMC_A25	LCD_G1	-	EVENTOUT
Port G	PG0	-	TIM1_CH4N	-	-	-	-	-	-	-	-	-	-	-	LCD_R7	-	EVENTOUT
Port G	PG1	-	-	-	-	-	-	-	-	-	-	-	-	-	LCD_R6	-	EVENTOUT
Port G	PG2	-	-	-	-	-	-	-	-	-	-	-	-	-	LCD_HSYNC	-	EVENTOUT
Port G	PG3	-	-	-	-	-	DCMIPP_HSYNC	-	-	-	PSSI_DE	-	ETH_PPS_OUT	FMC_D21	-	-	EVENTOUT
Port G	PG4	-	TIM1_BKIN2	-	-	-	-	-	-	-	-	-	ETH_MII_RXD0/ETH_RMII_RXD0	FMC_D22	-	-	EVENTOUT
Port G	PG5	-	TIM1_ETR	-	-	-	-	-	-	-	-	-	ETH_MII_RXD1/ETH_RMII_RXD1	FMC_D23	-	-	EVENTOUT
Port G	PG6	-	TIM17_BKIN	-	-	-	-	-	-	-	PSSI_D12	-	ETH_MDC	FMC_NBL2	DCMIPP_D12	-	EVENTOUT
Port G	PG7	-	-	-	-	-	-	SAI1_MCLK_A	-	-	PSSI_D13	-		FMC_D24	DCMIPP_D13	-	EVENTOUT
Port G	PG8	-	-	-	-	-	SPI6_NSS/I2S6_WS	-	-	SPDIFRX_IN2	-	-	ETH_PPS_OUT	FMC_D25	LCD_G0	-	EVENTOUT
Port G	PG9	-	-	-	-	-	SPI1_MISO/I2S1_SDI	-	-	SPDIFRX_IN3	PSSI_RDY	SAI2_FS_B	SDMMC2_D0	FMC_D26	DCMIPP_VSYNC	-	EVENTOUT
Port G	PG10	-	-	-	-	-	SPI1_NSS/I2S1_WS	-	-		PSSI_D2	SAI2_SD_B	SDMMC2_D1	FMC_D27	DCMIPP_D2	-	EVENTOUT
Port G	PG11	-	LPTIM1_IN2	-	-	-	SPI1_SCK/I2S1_CK	-	-	SPDIFRX_IN0	PSSI_D3	SDMMC2_D2	ETH_MII_TX_EN/ETH_RMII_TX_EN	FMC_D28	DCMIPP_D3	-	EVENTOUT
Port G	PG12	-	LPTIM1_IN1	-	-	-	SPI6_MISO/I2S6_SDI	-	-	SPDIFRX_IN1	-	SDMMC2_D3	ETH_MII_TXD1/ETH_RMII_TXD1	FMC_D29	LCD_G1	-	EVENTOUT
Port G	PG13	TRACED0	LPTIM1_CH1	-	-	-	SPI6_SCK/I2S6_CK	-	-	-	-	SDMMC2_D6	ETH_MII_TXD0/ETH_RMII_TXD0	FMC_D30	LCD_CLK	-	EVENTOUT
Port G	PG14	TRACED1	LPTIM1_ETR	-	-	-	SPI6_MOSI/I2S6_SDO	-	-	-	-	SDMMC2_D7	ETH_MII_TXD1/ETH_RMII_TXD1	FMC_D31	LCD_B1	-	EVENTOUT
Port G	PG15	-	LPTIM1_CH2	-	-	-	-	-	-	-	PSSI_D13	-	-	FMC_NBL3	DCMIPP_D13	-	EVENTOUT
Port H	PH0	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	TRACED0
Port H	PH1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	TRACED1
Port M	PM0	-	-	-	-	-	-	UCPD_CC1	-	-	-	-	-	-	-	-
Port M	PM1	-	-	-	-	-	-	UCPD_CC2	-	-	-	-	-	-	-	-	-
Port M	PM2	-	-	-	-	-	-	UCPD_DB1	-	-	-	-	-	-	-	-	-
Port M	PM3	-	-	-	-	-	-	UCPD_DB2	-	-	-	-	-	-	-	-	-
Port M	PM5	-	-	-	-	-	-	-	-	-	-	OTG_HS_DM	-	-	-	-	-
Port M	PM6	-	-	-	-	-	-	-	-	-	-	OTG_HS_DP	-	-	-	-	-
Port M	PM8	-	-	-	-	-	-	-	UART7_RX	-	-	OTG_HS_VBUS	-	-	-	-	-
Port M	PM9	-	-	-	-	-	-	-	UART7_TX	-	-	OTG_HS_ID	-	-	-	-	-
Port M	PM11	-	-	-	-	-	SPI5_SCK	-	-	-	-	OTG_FS_DP	-	-	-	-	-
Port M	PM12	-	-	-	-	-	SPI5_NSS	-	-	-	-	OTG_FS_DM	-	-	-	-	-
Port M	PM13	-	-	-	-	-	SPI5_MOSI	-	-	-	-	OTG_FS_ID	-	-	-	-	-
Port M	PM14	-	-	-	-	-	SPI5_MISO	-	-	-	-	OTG_FS_VBUS	-	-	-	-	-
Port N	PN0	-	-	-	-	-	-	-	-	-	XSPIM_P2_DQS0	-	-	FMC_NE4	-	-	-
Port N	PN1	-	-	-	-	-	-	-	-	-	XSPIM_P2_NCS1	-	-	FMC_NBL0	-	-	-
Port N	PN2	-	-	-	-	-	-	-	-	-	XSPIM_P2_IO0	-	-	FMC_D0/FMC_AD0	-	-	-
Port N	PN3	-	-	-	-	-	-	-	-	-	XSPIM_P2_IO1	-	-	FMC_D1/FMC_AD1	-	-	-
Port N	PN4	-	-	-	-	-	-	-	-	-	XSPIM_P2_IO2	-	-	FMC_D2/FMC_AD2	-	-	-
Port N	PN5	-	-	-	-	-	-	-	-	-	XSPIM_P2_IO3	-	-	FMC_D3/FMC_AD3	-	-	-
Port N	PN6	-	-	-	-	-	-	-	-	-	XSPIM_P2_CLK	-	-	FMC_SDCLK	-	-	-
Port N	PN7	-	-	-	-	-	-	-	-	-	XSPIM_P2_NCLK	-	-	FMC_CLK	-	-	-
Port N	PN8	-	-	-	-	-	-	-	-	-	XSPIM_P2_IO4	-	-	FMC_D4/FMC_AD4	-	-	-
Port N	PN9	-	-	-	-	-	-	-	-	-	XSPIM_P2_IO5	-	-	FMC_D5/FMC_AD5	-	-	-
Port N	PN10	-	-	-	-	-	-	-	-	-	XSPIM_P2_IO6	-	-	FMC_D6/FMC_AD6	-	-	-
Port N	PN11	-	-	-	-	-	-	-	-	-	XSPIM_P2_IO7	-	-	FMC_D7/FMC_AD7	-	-	-
Port N	PN12	-	-	-	-	-	-	-	-	-	XSPIM_P2_NCS2	-	-	-	-	-	-
Port O	PO0	-	-	-	-	-	-	-	-	-	XSPIM_P1_NCS1	-	-	-	-	-	-
Port O	PO1	-	-	-	-	-	-	-	-	-	XSPIM_P1_NCS2	-	-	-	-	-	-
Port O	PO2	-	-	-	-	-	-	-	-	-	XSPIM_P1_DQS0	-	-	-	-	-	-
Port O	PO3	-	-	-	-	-	-	-	-	-	XSPIM_P1_DQS1	-	-	-	-	-	-
Port O	PO4	-	-	-	-	-	-	-	-	-	XSPIM_P1_CLK	-	-	-	-	-	-
Port O	PO5	-	-	-	-	-	-	-	-	-	XSPIM_P1_NCLK	-	-	-	-	-	-
Port P	PP0	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO0	-	-	-	-	-	-
Port P	PP1	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO1	-	-	-	-	-	-
Port P	PP2	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO2	-	-	-	-	-	-
Port P	PP3	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO3	-	-	-	-	-	-
Port P	PP4	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO4	-	-	-	-	-	-
Port P	PP5	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO5	-	-	-	-	-	-
Port P	PP6	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO6	-	-	-	-	-	-
Port P	PP7	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO7	-	-	-	-	-	-
Port P	PP8	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO8	-	-	-	-	-	-
Port P	PP9	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO9	-	-	-	-	-	-
Port P	PP10	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO10	-	-	-	-	-	-
Port P	PP11	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO11	-	-	-	-	-	-
Port P	PP12	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO12	-	-	-	-	-	-
Port P	PP13	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO13	-	-	-	-	-	-
Port P	PP14	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO14	-	-	-	-	-	-
Port P	PP15	-	-	-	-	-	-	-	-	-	XSPIM_P1_IO15	-	-	-	-	-	-

Table 27 (pages 152–152)

Table 27 · 7 columns × 10 rows · p.152–152 · CSV

Symbols	Ratings	Min	Max	Unit
VDDX -V SS(1)	External main supply voltage (including V DD(2)(3)(4) , VDDSMPS , VDDA , VDDUSB , V DDXSPIx(2)(3)(4) , VBAT, VREF+ )	-0.3	4.0	V
VDDX -VSS (3)	I/O supply when HSLV= 0	-0.3	4.0	V
VDDX -VSS (3)	I/O supply when HSLV= 1	-	2.8	V
V IN(5)	Input voltage on FT_xxx pins	VSS −0.3	MIN (MIN (VDD , VDDA , VDDUSB , VBAT ) + 4.0 V, 6.0 V )(6)(7)	V
V IN(5)	Input voltage on TT_xx pins	VSS −0.3	4.0	V
V IN(5)	Input voltage on BOOT0 pin	V SS	9.0	V
V IN(5)	Input voltage on any other pins	VSS -0.3	4.0	V
\	∆ VDDX \		Variations between different VDDX power pins of the same domain	-	50.0	mV
\	VSSX -VSS \		Variations between all the different ground pins	-	50.0	mV
Vref -VDDA	Allowed voltage difference for Vref + > VDDA	-	0.4	V

Table 28 (pages 153–153)

Table 28 · 8 columns × 13 rows · p.153–153 · CSV

Symbols		Ratings			Max		Unit
ΣIVDD	ΣIVDD	Total current into sum of all VDD power lines (source)(1)	Total current into sum of all VDD power lines (source)(1)	Total current into sum of all VDD power lines (source)(1)	620	620	mA
ΣIVSS	ΣIVSS	Total current out of sum of all VSS ground lines (sink)(1)	Total current out of sum of all VSS ground lines (sink)(1)	Total current out of sum of all VSS ground lines (sink)(1)	620	620	mA
IVDD	IVDD	Maximum current into each VDD power pin (source)(1)	Maximum current into each VDD power pin (source)(1)	Maximum current into each VDD power pin (source)(1)	100	100	mA
IVSS	IVSS	Maximum current out of each VSS ground pin (sink)(1)	Maximum current out of each VSS ground pin (sink)(1)	Maximum current out of each VSS ground pin (sink)(1)	100	100	mA
IIO	IIO	Output current sunk or sourced by any I/O and control pin, except Pxy_C	Output current sunk or sourced by any I/O and control pin, except Pxy_C	Output current sunk or sourced by any I/O and control pin, except Pxy_C	20	20	mA
ΣI(PIN)	ΣI(PIN)	Total output current sunk by sum of all I/Os and control pins(2)	Total output current sunk by sum of all I/Os and control pins(2)	Total output current sunk by sum of all I/Os and control pins(2)	140	140	mA
ΣI(PIN)	ΣI(PIN)	Total output current sourced by sum of all I/Os and control pins(2)	Total output current sourced by sum of all I/Os and control pins(2)	Total output current sourced by sum of all I/Os and control pins(2)	140	140	mA
IINJ(PIN) (3)(4)	IINJ(PIN) (3)(4)	Injected current on FT_xxx, TT_xx, RST and B pins	Injected current on FT_xxx, TT_xx, RST and B pins	Injected current on FT_xxx, TT_xx, RST and B pins	-5/+0	-5/+0	mA
ΣIINJ(PIN)	ΣIINJ(PIN)	Total injected current (sum of all I/Os and control pins)(5)	Total injected current (sum of all I/Os and control pins)(5)	Total injected current (sum of all I/Os and control pins)(5)	±25	±25	mA
1. All external main power power supplies, (VDD , VDDA in , the VDD33USB permitted ) and range. ground (VSS , VSSA ) pins must always be connected to the 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A never positive be exceeded. injection is Refer induced also by to V TableIN >VDD 21: while Voltage a negative characteristics injection for is the induced maximum by VIN allowed <VSS . IINJ(PIN) input voltage must values. 5. When positive several and negative inputs are injected submitted currents to a (instantaneous current injection, values). the maximum ΣIINJ(PIN) is the absolute sum of the Table 23. Thermal characteristics	1. All external main power power supplies, (VDD , VDDA in , the VDD33USB permitted ) and range. ground (VSS , VSSA ) pins must always be connected to the 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A never positive be exceeded. injection is Refer induced also by to V TableIN >VDD 21: while Voltage a negative characteristics injection for is the induced maximum by VIN allowed <VSS . IINJ(PIN) input voltage must values. 5. When positive several and negative inputs are injected submitted currents to a (instantaneous current injection, values). the maximum ΣIINJ(PIN) is the absolute sum of the Table 23. Thermal characteristics	1. All external main power power supplies, (VDD , VDDA in , the VDD33USB permitted ) and range. ground (VSS , VSSA ) pins must always be connected to the 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A never positive be exceeded. injection is Refer induced also by to V TableIN >VDD 21: while Voltage a negative characteristics injection for is the induced maximum by VIN allowed <VSS . IINJ(PIN) input voltage must values. 5. When positive several and negative inputs are injected submitted currents to a (instantaneous current injection, values). the maximum ΣIINJ(PIN) is the absolute sum of the Table 23. Thermal characteristics	1. All external main power power supplies, (VDD , VDDA in , the VDD33USB permitted ) and range. ground (VSS , VSSA ) pins must always be connected to the 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A never positive be exceeded. injection is Refer induced also by to V TableIN >VDD 21: while Voltage a negative characteristics injection for is the induced maximum by VIN allowed <VSS . IINJ(PIN) input voltage must values. 5. When positive several and negative inputs are injected submitted currents to a (instantaneous current injection, values). the maximum ΣIINJ(PIN) is the absolute sum of the Table 23. Thermal characteristics	1. All external main power power supplies, (VDD , VDDA in , the VDD33USB permitted ) and range. ground (VSS , VSSA ) pins must always be connected to the 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A never positive be exceeded. injection is Refer induced also by to V TableIN >VDD 21: while Voltage a negative characteristics injection for is the induced maximum by VIN allowed <VSS . IINJ(PIN) input voltage must values. 5. When positive several and negative inputs are injected submitted currents to a (instantaneous current injection, values). the maximum ΣIINJ(PIN) is the absolute sum of the Table 23. Thermal characteristics	1. All external main power power supplies, (VDD , VDDA in , the VDD33USB permitted ) and range. ground (VSS , VSSA ) pins must always be connected to the 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A never positive be exceeded. injection is Refer induced also by to V TableIN >VDD 21: while Voltage a negative characteristics injection for is the induced maximum by VIN allowed <VSS . IINJ(PIN) input voltage must values. 5. When positive several and negative inputs are injected submitted currents to a (instantaneous current injection, values). the maximum ΣIINJ(PIN) is the absolute sum of the Table 23. Thermal characteristics	1. All external main power power supplies, (VDD , VDDA in , the VDD33USB permitted ) and range. ground (VSS , VSSA ) pins must always be connected to the 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A never positive be exceeded. injection is Refer induced also by to V TableIN >VDD 21: while Voltage a negative characteristics injection for is the induced maximum by VIN allowed <VSS . IINJ(PIN) input voltage must values. 5. When positive several and negative inputs are injected submitted currents to a (instantaneous current injection, values). the maximum ΣIINJ(PIN) is the absolute sum of the Table 23. Thermal characteristics	1. All external main power power supplies, (VDD , VDDA in , the VDD33USB permitted ) and range. ground (VSS , VSSA ) pins must always be connected to the 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count QFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A never positive be exceeded. injection is Refer induced also by to V TableIN >VDD 21: while Voltage a negative characteristics injection for is the induced maximum by VIN allowed <VSS . IINJ(PIN) input voltage must values. 5. When positive several and negative inputs are injected submitted currents to a (instantaneous current injection, values). the maximum ΣIINJ(PIN) is the absolute sum of the Table 23. Thermal characteristics
Symbol	Ratings	Ratings	Ratings	Value	Value	Unit	Unit
TSTG	Storage temperature range	Storage temperature range	Storage temperature range	-65 to +150	-65 to +150	°C	°C
TJ	Maximum junction temperature	Maximum junction temperature	Industrial temperature range 6	130(1)	130(1)	°C	°C

Table 29 (pages 154–154)

Table 29 · 7 columns × 23 rows · p.154–154 · CSV

Symbol	Parameter	Operating conditions	Min	Typ	Max	Unit
VDD	Standard operating voltage	HSLV=0	1.71(1)	-	3.6	V
VDD	Standard operating voltage	HSLV=1	1.71(1)	-	2.7	V
VDDLDO	Supply voltage for the internal regulator.	-	1.71(1)	-	3.6	V
VDDSMPS (2)	Supply voltage for the internal SMPS step-down converter	-	1.71(1)	-	3.6	V
VDDXSPIx	Octo and HexaSPI supply	HSLV=0	1.62	-	3.6	V
VDDXSPIx	Octo and HexaSPI supply	HSLV=1	1.08	-	2.7	V
V DD50USB(2)	USB supply voltage	USB regulator ON	4.0	5.0	5.5	V
V DD50USB(2)	USB supply voltage	USB regulator OFF	VDD33USB	VDD33USB	VDD33USB	V
VDD33USB	USB supply voltage	USB used	3.0	-	3.6	V
VDD33USB	USB supply voltage	USB not used	0	-	3.6	V
VDDA	Analog operating voltage	ADC used	1.62	-	3.6	V
VDDA	Analog operating voltage	VREFBUF used	2.10	-	3.6	V
VDDA	Analog operating voltage	ADC, VREFBUF not used	0	-	3.6	V
VBAT	Supply voltage for backup domain	-	1.2(3)	-	3.6	V
VIN	I/O Input voltage	BOOT0	-0.3	-	9.0	V
VIN	I/O Input voltage	All IOs except BOOT0	-0.3	-	MIN (VDD , VDDA , VDD33USB , VDDXSPIx , 3.6 V) <, 5.5 V(4)(5)	V
VCORE	Internal regulator ON (LDO or SMPS)(6)	VOS low	1.15	1.21	1.26	V
VCORE	Internal regulator ON (LDO or SMPS)(6)	VOS high	1.15	1.36	1.4	V
VCORE	Regulator OFF: external VCORE voltage must be supplied from external regulator on VCAP pins	VOS low	1.2	-	1.26	V
VCORE	Regulator OFF: external VCORE voltage must be supplied from external regulator on VCAP pins	VOS high	1.37	-	1.4	V
VCORE	Regulator OFF: external VCORE voltage must be supplied from external regulator on VCAP pins	SVOS low(7)	0.7	0.74	0.8	V
VCORE	Regulator OFF: external VCORE voltage must be supplied from external regulator on VCAP pins	SVOS high(7)	0.95	1	1.05	V
DVDD	USB OTG_HS PHY digital supply voltage	-	0.95	-	1.4	V

Table 30 (pages 155–155)

Table 30 · 11 columns × 20 rows · p.155–155 · CSV

Symbol	Parameter		Operating conditions		Min		Typ	Max		Unit
fCPU	CPU clock frequency	CPU clock frequency	VOS low	VOS low	-	-	-	400	400	MHz
fCPU	CPU clock frequency	CPU clock frequency	VOS high	VOS high	-	-	-	600(8)	600(8)	MHz
fACLK	AXI clock frequency	AXI clock frequency	VOS low	VOS low	-	-	-	200	200	MHz
fACLK	AXI clock frequency	AXI clock frequency	VOS high	VOS high	-	-	-	300	300	MHz
fHCLK	AHB clock frequency	AHB clock frequency	VOS low	VOS low	-	-	-	200	200	MHz
fHCLK	AHB clock frequency	AHB clock frequency	VOS high	VOS high	-	-	-	300	300	MHz
Fpclk	APB clock frequency	APB clock frequency	VOS low	VOS low	-	-	-	100	100	MHz
Fpclk	APB clock frequency	APB clock frequency	VOS high	VOS high	-	-	-	150	150	MHz
TA	Ambient temperature for temperature range(9)	Ambient temperature for temperature range(9)	Maximum power dissipation	Maximum power dissipation	-40	-40	-	85	85	°C
TJ	Junction temperature	Junction temperature	VOS high	VOS high	-40	-40	-	105	105	°C
TJ	Junction temperature	Junction temperature	VOS low	VOS low	-40	-40	-	130	130	°C
1. When RESET is released, functionality is guaranteed down to BOR level 0 minimum voltage. 2. Not available on every package. 3. VBAT minimum value can be reduced to 0 V if VDD is present. 4. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min (VDD, VDDA, VDD33USB, VDDXSPIx) + 3.6 V < 5.5 V. 5. For resistors operation must with be disabled. voltage higher than Min (VDD , VDDA , VDDUSB , and VDDXSPIx ) +0.3 V, the internal Pull-up and Pull-Down 6. These values are factory trimmed per die. 7. Values for Regulator ON or OFF 8. With ECC disabled 9. The temperature device junction configuration temperature and Section must be 7.12: kept Package below maximum thermal characteristics). TJ indicated in Table 25: Supply voltage and maximum Table 25. Supply voltage and maximum temperature configuration	1. When RESET is released, functionality is guaranteed down to BOR level 0 minimum voltage. 2. Not available on every package. 3. VBAT minimum value can be reduced to 0 V if VDD is present. 4. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min (VDD, VDDA, VDD33USB, VDDXSPIx) + 3.6 V < 5.5 V. 5. For resistors operation must with be disabled. voltage higher than Min (VDD , VDDA , VDDUSB , and VDDXSPIx ) +0.3 V, the internal Pull-up and Pull-Down 6. These values are factory trimmed per die. 7. Values for Regulator ON or OFF 8. With ECC disabled 9. The temperature device junction configuration temperature and Section must be 7.12: kept Package below maximum thermal characteristics). TJ indicated in Table 25: Supply voltage and maximum Table 25. Supply voltage and maximum temperature configuration	1. When RESET is released, functionality is guaranteed down to BOR level 0 minimum voltage. 2. Not available on every package. 3. VBAT minimum value can be reduced to 0 V if VDD is present. 4. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min (VDD, VDDA, VDD33USB, VDDXSPIx) + 3.6 V < 5.5 V. 5. For resistors operation must with be disabled. voltage higher than Min (VDD , VDDA , VDDUSB , and VDDXSPIx ) +0.3 V, the internal Pull-up and Pull-Down 6. These values are factory trimmed per die. 7. Values for Regulator ON or OFF 8. With ECC disabled 9. The temperature device junction configuration temperature and Section must be 7.12: kept Package below maximum thermal characteristics). TJ indicated in Table 25: Supply voltage and maximum Table 25. Supply voltage and maximum temperature configuration	1. When RESET is released, functionality is guaranteed down to BOR level 0 minimum voltage. 2. Not available on every package. 3. VBAT minimum value can be reduced to 0 V if VDD is present. 4. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min (VDD, VDDA, VDD33USB, VDDXSPIx) + 3.6 V < 5.5 V. 5. For resistors operation must with be disabled. voltage higher than Min (VDD , VDDA , VDDUSB , and VDDXSPIx ) +0.3 V, the internal Pull-up and Pull-Down 6. These values are factory trimmed per die. 7. Values for Regulator ON or OFF 8. With ECC disabled 9. The temperature device junction configuration temperature and Section must be 7.12: kept Package below maximum thermal characteristics). TJ indicated in Table 25: Supply voltage and maximum Table 25. Supply voltage and maximum temperature configuration	1. When RESET is released, functionality is guaranteed down to BOR level 0 minimum voltage. 2. Not available on every package. 3. VBAT minimum value can be reduced to 0 V if VDD is present. 4. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min (VDD, VDDA, VDD33USB, VDDXSPIx) + 3.6 V < 5.5 V. 5. For resistors operation must with be disabled. voltage higher than Min (VDD , VDDA , VDDUSB , and VDDXSPIx ) +0.3 V, the internal Pull-up and Pull-Down 6. These values are factory trimmed per die. 7. Values for Regulator ON or OFF 8. With ECC disabled 9. The temperature device junction configuration temperature and Section must be 7.12: kept Package below maximum thermal characteristics). TJ indicated in Table 25: Supply voltage and maximum Table 25. Supply voltage and maximum temperature configuration	1. When RESET is released, functionality is guaranteed down to BOR level 0 minimum voltage. 2. Not available on every package. 3. VBAT minimum value can be reduced to 0 V if VDD is present. 4. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min (VDD, VDDA, VDD33USB, VDDXSPIx) + 3.6 V < 5.5 V. 5. For resistors operation must with be disabled. voltage higher than Min (VDD , VDDA , VDDUSB , and VDDXSPIx ) +0.3 V, the internal Pull-up and Pull-Down 6. These values are factory trimmed per die. 7. Values for Regulator ON or OFF 8. With ECC disabled 9. The temperature device junction configuration temperature and Section must be 7.12: kept Package below maximum thermal characteristics). TJ indicated in Table 25: Supply voltage and maximum Table 25. Supply voltage and maximum temperature configuration	1. When RESET is released, functionality is guaranteed down to BOR level 0 minimum voltage. 2. Not available on every package. 3. VBAT minimum value can be reduced to 0 V if VDD is present. 4. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min (VDD, VDDA, VDD33USB, VDDXSPIx) + 3.6 V < 5.5 V. 5. For resistors operation must with be disabled. voltage higher than Min (VDD , VDDA , VDDUSB , and VDDXSPIx ) +0.3 V, the internal Pull-up and Pull-Down 6. These values are factory trimmed per die. 7. Values for Regulator ON or OFF 8. With ECC disabled 9. The temperature device junction configuration temperature and Section must be 7.12: kept Package below maximum thermal characteristics). TJ indicated in Table 25: Supply voltage and maximum Table 25. Supply voltage and maximum temperature configuration	1. When RESET is released, functionality is guaranteed down to BOR level 0 minimum voltage. 2. Not available on every package. 3. VBAT minimum value can be reduced to 0 V if VDD is present. 4. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min (VDD, VDDA, VDD33USB, VDDXSPIx) + 3.6 V < 5.5 V. 5. For resistors operation must with be disabled. voltage higher than Min (VDD , VDDA , VDDUSB , and VDDXSPIx ) +0.3 V, the internal Pull-up and Pull-Down 6. These values are factory trimmed per die. 7. Values for Regulator ON or OFF 8. With ECC disabled 9. The temperature device junction configuration temperature and Section must be 7.12: kept Package below maximum thermal characteristics). TJ indicated in Table 25: Supply voltage and maximum Table 25. Supply voltage and maximum temperature configuration	1. When RESET is released, functionality is guaranteed down to BOR level 0 minimum voltage. 2. Not available on every package. 3. VBAT minimum value can be reduced to 0 V if VDD is present. 4. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min (VDD, VDDA, VDD33USB, VDDXSPIx) + 3.6 V < 5.5 V. 5. For resistors operation must with be disabled. voltage higher than Min (VDD , VDDA , VDDUSB , and VDDXSPIx ) +0.3 V, the internal Pull-up and Pull-Down 6. These values are factory trimmed per die. 7. Values for Regulator ON or OFF 8. With ECC disabled 9. The temperature device junction configuration temperature and Section must be 7.12: kept Package below maximum thermal characteristics). TJ indicated in Table 25: Supply voltage and maximum Table 25. Supply voltage and maximum temperature configuration	1. When RESET is released, functionality is guaranteed down to BOR level 0 minimum voltage. 2. Not available on every package. 3. VBAT minimum value can be reduced to 0 V if VDD is present. 4. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min (VDD, VDDA, VDD33USB, VDDXSPIx) + 3.6 V < 5.5 V. 5. For resistors operation must with be disabled. voltage higher than Min (VDD , VDDA , VDDUSB , and VDDXSPIx ) +0.3 V, the internal Pull-up and Pull-Down 6. These values are factory trimmed per die. 7. Values for Regulator ON or OFF 8. With ECC disabled 9. The temperature device junction configuration temperature and Section must be 7.12: kept Package below maximum thermal characteristics). TJ indicated in Table 25: Supply voltage and maximum Table 25. Supply voltage and maximum temperature configuration	1. When RESET is released, functionality is guaranteed down to BOR level 0 minimum voltage. 2. Not available on every package. 3. VBAT minimum value can be reduced to 0 V if VDD is present. 4. This formula has to be applied on power supplies related to the IO structure described by the pin definition table. Maximum I/O input voltage is the smallest value between Min (VDD, VDDA, VDD33USB, VDDXSPIx) + 3.6 V < 5.5 V. 5. For resistors operation must with be disabled. voltage higher than Min (VDD , VDDA , VDDUSB , and VDDXSPIx ) +0.3 V, the internal Pull-up and Pull-Down 6. These values are factory trimmed per die. 7. Values for Regulator ON or OFF 8. With ECC disabled 9. The temperature device junction configuration temperature and Section must be 7.12: kept Package below maximum thermal characteristics). TJ indicated in Table 25: Supply voltage and maximum Table 25. Supply voltage and maximum temperature configuration
Power scale	Power scale	VCORE source	VCORE source	Max. TJ (°C)	Max. TJ (°C)	Min. VDD (V)	Min. VDD (V)	Min. VDD (V)	Min. VDDLDO (V)	Min. VDDLDO (V)
VOS high	VOS high	LDO	LDO	105	105	1.71	1.71	1.71	1.71	1.71
VOS high	VOS high	External (Bypass)	External (Bypass)	105	105	1.71	1.71	1.71	-	-
VOS low	VOS low	LDO	LDO	130	130	1.71	1.71	1.71	1.71	1.71
VOS low	VOS low	External (Bypass)	External (Bypass)	130	130	-	-	-	-	-
SVOS high/SVOS low	SVOS high/SVOS low	LDO	LDO	130	130	2	2	2	2	2
SVOS high/SVOS low	SVOS high/SVOS low	LDO	LDO	105	105	1.71	1.71	1.71	1.71	1.71
SVOS high/SVOS low	SVOS high/SVOS low	External (Bypass)	External (Bypass)	130	130	1.71	1.71	1.71	-	-

Table 31 (pages 156–156)

Table 31 · 3 columns × 1 rows · p.156–156 · CSV

C ESR RLeak MS19044V2
1. Legend: ESR is the equivalent series resistance. Table 26. VCAP operating conditions(1)
Symbol	Parameter	Conditions
CEXT	Capacitance of external capacitor	2.2 µF(2)(3)
ESR	ESR of external capacitor	< 100 mΩ

Table 32 (pages 157–157)

Table 32 · 3 columns × 8 rows · p.157–157 · CSV

VDD VDDSMPS VDD VDDSMPS Cin L VLXSMPS Cin L VLXSMPS VFBSMPS Cfilt SMPS (ON) VDD_extern VFBSMPS Cfilt SMPS (ON) Cout1 VSSSMPS 2xCout1 VSSSMPS VCAP VCAP VDDLDO V V CORE CORE VDDLDO V V CORE CORE Voltage Vdd Voltage Cout2 VSS regulator (OFF) Cout2 VSS regulator (ON) Direct SMPS supply External SMPS supply, LDO supply MSv55526V3
Table 27. Characteristics of SMPS step-down converter external components
Symbol	Parameter	Conditions
Cin	Capacitance of external capacitor on VDDSMPS	4.7 µF
Cin	ESR of external capacitor	100 mΩ
Cfilt	Capacitance of external capacitor on VLXSMPS pin	220 pF
COUT	Capacitance of external capacitor on VFBSMPS pin	2x10 µF
COUT	ESR of external capacitor	20 mΩ
L	Inductance of external Inductor on VLXSMPS pin	2.2 µH
-	Serial DC resistor	150 mΩ
ISAT	DC current at which the inductance drops 30% from its value without current.	1.7 A
IRMS	Average current for a 40 °C rise: rated current for which the temperature of the inductor is raised 40°C by DC current	1.4 A

Table 33 (pages 158–158)

Table 33 · 12 columns × 14 rows · p.158–158 · CSV

Parameters		Conditions		Min	Typ		Max			Unit
V DDSMPS(1)	V DDSMPS(1)	VOUT = 1.8 V	VOUT = 1.8 V	2.3	-	-	3.6	3.6	3.6	V	V
V OUT(2)	V OUT(2)	Iout=600 mA	Iout=600 mA	1.62	1.8	1.8	1.98	1.98	1.98	V	V
IOUT	IOUT	External usage only(3)	External usage only(3)	-	-	-	600	600	600	mA	mA
RDSON	RDSON	-	-	-	100	100	120	120	120	mΩ	mΩ
IDDSMPS_Q	IDDSMPS_Q	Quiescent current	Quiescent current	-	220	220	-	-	-	µA	µA
TSMPS_START	TSMPS_START	VOUT = 1.8 V	VOUT = 1.8 V	-	270	270	405	405	405	µs	µs
1. The switching frequency is 2.4 MHz±10%. 2. Including line transient and load transient. 3. These characteristics are given for SMPSEXTHP bit is set in the PWR_CR3 register. Table 29. Inrush current and inrush electric charge characteristics for LDO and SMPS(1)(2)	1. The switching frequency is 2.4 MHz±10%. 2. Including line transient and load transient. 3. These characteristics are given for SMPSEXTHP bit is set in the PWR_CR3 register. Table 29. Inrush current and inrush electric charge characteristics for LDO and SMPS(1)(2)	1. The switching frequency is 2.4 MHz±10%. 2. Including line transient and load transient. 3. These characteristics are given for SMPSEXTHP bit is set in the PWR_CR3 register. Table 29. Inrush current and inrush electric charge characteristics for LDO and SMPS(1)(2)	1. The switching frequency is 2.4 MHz±10%. 2. Including line transient and load transient. 3. These characteristics are given for SMPSEXTHP bit is set in the PWR_CR3 register. Table 29. Inrush current and inrush electric charge characteristics for LDO and SMPS(1)(2)	1. The switching frequency is 2.4 MHz±10%. 2. Including line transient and load transient. 3. These characteristics are given for SMPSEXTHP bit is set in the PWR_CR3 register. Table 29. Inrush current and inrush electric charge characteristics for LDO and SMPS(1)(2)	1. The switching frequency is 2.4 MHz±10%. 2. Including line transient and load transient. 3. These characteristics are given for SMPSEXTHP bit is set in the PWR_CR3 register. Table 29. Inrush current and inrush electric charge characteristics for LDO and SMPS(1)(2)	1. The switching frequency is 2.4 MHz±10%. 2. Including line transient and load transient. 3. These characteristics are given for SMPSEXTHP bit is set in the PWR_CR3 register. Table 29. Inrush current and inrush electric charge characteristics for LDO and SMPS(1)(2)	1. The switching frequency is 2.4 MHz±10%. 2. Including line transient and load transient. 3. These characteristics are given for SMPSEXTHP bit is set in the PWR_CR3 register. Table 29. Inrush current and inrush electric charge characteristics for LDO and SMPS(1)(2)	1. The switching frequency is 2.4 MHz±10%. 2. Including line transient and load transient. 3. These characteristics are given for SMPSEXTHP bit is set in the PWR_CR3 register. Table 29. Inrush current and inrush electric charge characteristics for LDO and SMPS(1)(2)	1. The switching frequency is 2.4 MHz±10%. 2. Including line transient and load transient. 3. These characteristics are given for SMPSEXTHP bit is set in the PWR_CR3 register. Table 29. Inrush current and inrush electric charge characteristics for LDO and SMPS(1)(2)	1. The switching frequency is 2.4 MHz±10%. 2. Including line transient and load transient. 3. These characteristics are given for SMPSEXTHP bit is set in the PWR_CR3 register. Table 29. Inrush current and inrush electric charge characteristics for LDO and SMPS(1)(2)	1. The switching frequency is 2.4 MHz±10%. 2. Including line transient and load transient. 3. These characteristics are given for SMPSEXTHP bit is set in the PWR_CR3 register. Table 29. Inrush current and inrush electric charge characteristics for LDO and SMPS(1)(2)
Symbol	Parameter	Parameter	Conditions	Conditions	Conditions	Min	Min	Typ	Max	Max	Unit
IRUSH	Inrush current on voltage regulator power-on (POR or wakeup from Standby)	Inrush current on voltage regulator power-on (POR or wakeup from Standby)	On V DDLDO(3)	-	-	-	-	55	96(4)	96(4)	mA
IRUSH	Inrush current on voltage regulator power-on (POR or wakeup from Standby)	Inrush current on voltage regulator power-on (POR or wakeup from Standby)	On V DDSMPS(5)	SMPS supplies the VDDCORE	SMPS supplies the VDDCORE	-	-	100	420(6)	420(6)	mA
IRUSH	Inrush current on voltage regulator power-on (POR)	Inrush current on voltage regulator power-on (POR)	On V DDSMPS(5)	SMPS supplies external circuit, VOUT = 1.8 V(7)	SMPS supplies external circuit, VOUT = 1.8 V(7)	-	-	100	320(6)	320(6)	mA
QRUSH	Inrush charge on voltage regulator power-on (POR or wakeup from Standby)	Inrush charge on voltage regulator power-on (POR or wakeup from Standby)	On V DDLDO(3)	-	-	-	-	4.4	5.3(4)	5.3(4)	µC
QRUSH	Inrush charge on voltage regulator power-on (POR or wakeup from Standby)	Inrush charge on voltage regulator power-on (POR or wakeup from Standby)	On V DDSMPS(5)	SMPS supplies the VDDCORE	SMPS supplies the VDDCORE	-	-	7.3	18(6)	18(6)	µC
QRUSH	Inrush charge on voltage regulator power-on (POR)	Inrush charge on voltage regulator power-on (POR)	On V DDSMPS(5)	SMPS supplies external circuit, VOUT = 1.8 V(7)	SMPS supplies external circuit, VOUT = 1.8 V(7)	-	-	7.3	13.7(6)	13.7(6)	µC

Table 34 (pages 161–161)

Table 34 · 5 columns × 8 rows · p.161–161 · CSV

Symbol	Parameter	Min	Max	Unit
tVDD	VDD rise time rate	0	∞	µs/V
tVDD	VDD fall time rate	10	∞	µs/V
tVDDA	VDDA rise time rate	0	∞	µs/V
tVDDA	VDDA fall time rate	10	∞	µs/V
tVDDUSB	VDDUSB rise time rate	0	∞	µs/V
tVDDUSB	VDDUSB fall time rate	10	∞	µs/V
t VCORE(1)	VCORE rise time rate(2)	0	285	µs/V
t VCORE(1)	VCORE fall time rate	10	∞	µs/V

Table 35 (pages 162–163)

Table 35 · 7 columns × 38 rows · p.162–163 · CSV

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
t RSTTEMPO(1)	Reset temporization after BOR0 released	-	-	377	550	µs
VBOR0/POR/PDR	Power-on/power-down reset threshold	Rising edge(1)	1.62	1.67	1.71	V
VBOR0/POR/PDR	Power-on/power-down reset threshold	Falling edge	1.58	1.62	1.68	V
VBOR1	Brown-out reset threshold 1	Rising edge	2.04	2.10	2.15	V
VBOR1	Brown-out reset threshold 1	Falling edge	1.95	2.00	2.06	V
VBOR2	Brown-out reset threshold 2	Rising edge	2.34	2.41	2.47	V
VBOR2	Brown-out reset threshold 2	Falling edge	2.25	2.31	2.37	V
VBOR3	Brown-out reset threshold 3	Rising edge	2.63	2.70	2.78	V
VBOR3	Brown-out reset threshold 3	Falling edge	2.54	2.61	2.68	V
VPVD0	Programmable Voltage Detector threshold 0	Rising edge	1.90	1.96	2.01	V
VPVD0	Programmable Voltage Detector threshold 0	Falling edge	1.81	1.86	1.91	V
VPVD1	Programmable Voltage Detector threshold 1	Rising edge	2.05	2.10	2.16	V
VPVD1	Programmable Voltage Detector threshold 1	Falling edge	1.96	2.01	2.06	V
VPVD2	Programmable Voltage Detector threshold 2	Rising edge	2.19	2.26	2.32	V
VPVD2	Programmable Voltage Detector threshold 2	Falling edge	2.10	2.15	2.21	V
VPVD3	Programmable Voltage Detector threshold 3	Rising edge	2.35	2.41	2.47	V
VPVD3	Programmable Voltage Detector threshold 3	Falling edge	2.25	2.31	2.37	V
VPVD4	Programmable Voltage Detector threshold 4	Rising edge	2.49	2.56	2.62	V
VPVD4	Programmable Voltage Detector threshold 4	Falling edge	2.39	2.45	2.51	V
VPVD5	Programmable Voltage Detector threshold 5	Rising edge	2.64	2.71	2.78	V
VPVD5	Programmable Voltage Detector threshold 5	Falling edge	2.55	2.61	2.68	V
VPVD6	Programmable Voltage Detector threshold 6	Rising edge	2.78	2.86	2.94	V
VPVD6	Programmable Voltage Detector threshold 6	Falling edge in Run mode	2.69	2.76	2.83	V
Vhyst_POR_PDR	Hysteresis voltage for Power-on/power-down reset (including BOR0)	Hysteresis in Run mode	-	43	-	mV
Vhyst_BOR_PVD	Hysteresis voltage for BOR (except BOR0)	Hysteresis in Run mode	-	100	-	mV
I DD_BOR_PVD(1)	BOR and PVD consumption from VDD	-	-	-	0.63	µA
IDD_POR_PVD	POR and PVD consumption from VDD	-	0.8	-	1.2	µA
VAVM_0	Analog voltage detector for VDDA threshold 0	Rising edge	1.66	1.71	1.76	V
VAVM_0	Analog voltage detector for VDDA threshold 0	Falling edge	1.56	1.61	1.66	V
VAVM_1	Analog voltage detector for VDDA threshold 1	Rising edge	2.06	2.12	2.19	V
VAVM_1	Analog voltage detector for VDDA threshold 1	Falling edge	1.96	2.02	2.08	V
VAVM_2	Analog voltage detector for VDDA threshold 2	Rising edge	2.42	2.50	2.58	V
VAVM_2	Analog voltage detector for VDDA threshold 2	Falling edge	2.35	2.42	2.49	V
VAVM_3	Analog voltage detector for VDDA threshold 3	Rising edge	2.74	2.83	2.91	V
VAVM_3	Analog voltage detector for VDDA threshold 3	Falling edge	2.64	2.72	2.80	V
Vhyst_VDDA	Hysteresis of VDDA voltage detector	-	-	100	-	mV
IDD_PVM	PVM consumption from VDD(1)	-	-	-	0.25	µA
IDD_VDDA	Voltage detector consumption on V DDA(1)	Resistor bridge	-	-	2.5	µA

Table 36 (pages 164–164)

Table 36 · 9 columns × 14 rows · p.164–164 · CSV

Symbol		Parameter	Conditions	Min		Typ	Max	Unit
VREFINT	VREFINT	Internal reference voltages	-40°C < TJ < TJmax	1.18	1.18	1.216	1.255	V
t S_vrefint(1)(2)(3)	t S_vrefint(1)(2)(3)	ADC sampling time when reading the internal reference voltage	-	4.3	4.3	-	-	µs
t S_vbat(2)	t S_vbat(2)	VBAT sampling time when reading the internal VBAT reference voltage	-	9	9	-	-	µs
t start_vrefint(2)	t start_vrefint(2)	Start time of reference voltage buffer when ADC is enable	-	-	-	-	4.4	µs
I refbuf(2)	I refbuf(2)	Reference Buffer consumption for ADC	VDD = 3.3 V	9	9	13.5	23	µA
ΔVREFINT (2)	ΔVREFINT (2)	Internal reference voltage spread over the temperature range	-40°C < TJ < TJmax	-	-	5	15	mV
T coeff(2)	T coeff(2)	Average temperature coefficient	Average temperature coefficient	-	-	20	70	ppm/°C
V DDcoeff(2)	V DDcoeff(2)	Average Voltage coefficient	3.0 V < VDD < 3.6 V	-	-	10	1370	ppm/V
VREFINT_DIV1	VREFINT_DIV1	1/4 reference voltage	-	-	-	25	-	% VREFINT
VREFINT_DIV2	VREFINT_DIV2	1/2 reference voltage	-	-	-	50	-	% VREFINT
VREFINT_DIV3	VREFINT_DIV3	3/4 reference voltage	-	-	-	75	-	% VREFINT
1. The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. 3. Guaranteed by design. and tested in production at 3.3 V. Table 33. Internal reference voltage calibration values	1. The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. 3. Guaranteed by design. and tested in production at 3.3 V. Table 33. Internal reference voltage calibration values	1. The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. 3. Guaranteed by design. and tested in production at 3.3 V. Table 33. Internal reference voltage calibration values	1. The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. 3. Guaranteed by design. and tested in production at 3.3 V. Table 33. Internal reference voltage calibration values	1. The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. 3. Guaranteed by design. and tested in production at 3.3 V. Table 33. Internal reference voltage calibration values	1. The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. 3. Guaranteed by design. and tested in production at 3.3 V. Table 33. Internal reference voltage calibration values	1. The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. 3. Guaranteed by design. and tested in production at 3.3 V. Table 33. Internal reference voltage calibration values	1. The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. 3. Guaranteed by design. and tested in production at 3.3 V. Table 33. Internal reference voltage calibration values	1. The shortest sampling time for the application can be determined by multiple iterations. 2. Guaranteed by design. 3. Guaranteed by design. and tested in production at 3.3 V. Table 33. Internal reference voltage calibration values
Symbol	Parameter	Parameter	Parameter	Parameter	Memory address	Memory address	Memory address	Memory address
VREFIN_CAL	Raw data acquired at temperature of 30 °C, VDDA = 3.3 V	Raw data acquired at temperature of 30 °C, VDDA = 3.3 V	Raw data acquired at temperature of 30 °C, VDDA = 3.3 V	Raw data acquired at temperature of 30 °C, VDDA = 3.3 V	0x08FF F810 -0x08FF F811	0x08FF F810 -0x08FF F811	0x08FF F810 -0x08FF F811	0x08FF F810 -0x08FF F811

Table 37 (pages 166–170)

Table 37 · 12 columns × 50 rows · p.166–170 · CSV

Symbol	Parameter	Conditions		frcc_c_ck (MHz)	Typ LDO	Typ SMPS	Max(2) LDO				Unit
Symbol	Parameter	Conditions		frcc_c_ck (MHz)	Typ LDO	Typ SMPS	TJ =25°C	TJ =85°C	TJ =105°C	TJ =130°C	Unit
IDD	Supply current in Run mode	All peripherals disabled	VOS high	600	125.0	65.5	135.0	235.0	310.0	-	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS high	400	84.5	45.0	95.0	195.0	275.0	-	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS high(3)	400	90.0	48.0	100.0	200.0	280.0	-	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS low	400	73.5	36.5	91.5	190.0	260.0	405.0	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS low	300	57.0	29.0	75.0	170.0	245.0	390.0	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS high	600	175.0	90.0	180.0	280.0	355.0	-	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS high	400	115.0	62.5	130.0	230.0	305.0	-	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS high(3)	400	125.0	65.5	135.0	235.0	310.0	-	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS low	400	105.0	50.5	125.0	220.0	290.0	435.0	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS low	300	79.5	39.5	98.0	195.0	265.0	410.0	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS high	600	130.0	69.0	140.0	240.0	315.0	-	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS high	400	89.5	47.5	99.5	200.0	275.0	-	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS high(3)	400	92.0	49.0	105.0	205.0	280.0	-	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS low	400	77.5	38.5	96.0	195.0	265.0	410.0	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS low	300	60.5	30.5	78.5	175.0	245.0	395.0	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS high	600	180.0	94.5	190.0	285.0	360.0	-	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS high	400	125.0	65.5	135.0	235.0	310.0	-	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS high(3)	400	125.0	67.0	135.0	235.0	310.0	-	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS low	400	105.0	52.5	130.0	225.0	295.0	440.0	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS low	300	82.5	41.0	105.0	200.0	270.0	415.0	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS high	600	96.0	51.0	110.0	210.0	285.0	-	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS high	400	66.5	35.5	82.5	180.0	255.0	-	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS high(3)	400	70.5	37.5	87.0	185.0	260.0	-	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS low	400	57.5	28.5	79.5	175.0	245.0	390.0	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS low	300	46.0	23.5	66.5	160.0	235.0	380.0	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS high	600	145.0	77.5	160.0	255.0	330.0	-	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS high	400	99.5	53.0	115.0	215.0	290.0	-	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS high(3)	400	105.0	55.5	120.0	215.0	290.0	-	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS low	400	87.0	43.0	110.0	205.0	275.0	420.0	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS low	300	68.0	34.0	89.0	185.0	255.0	405.0	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS high	600	130.0	67.5	140.0	235.0	315.0	-	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS high	400	87.0	46.5	97.0	200.0	275.0	-	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS high(3)	400	89.5	48.0	99.5	200.0	280.0	-	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS low	400	75.5	37.0	93.5	190.0	265.0	410.0	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS low	300	58.5	29.5	76.5	175.0	245.0	395.0	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS high	600	175.0	92.5	185.0	285.0	360.0	-	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS high	400	120.0	64.0	130.0	230.0	305.0	-	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS high(3)	400	125.0	65.5	135.0	235.0	310.0	-	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS low	400	105.0	51.5	125.0	220.0	295.0	440.0	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS low	300	81.0	40.5	99.5	195.0	270.0	415.0	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS high	600	78.5	43.5	91.5	195.0	270.0	-	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS high	400	59.0	33.0	73.5	175.0	250.0	-	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS high(3)	400	60.5	34.0	75.0	175.0	250.0	-	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS low	400	49.5	26.5	68.5	165.0	235.0	385.0	mA
IDD	Supply current in Run mode	All peripherals disabled	VOS low	300	41.5	22.5	60.5	155.0	230.0	375.0	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS high	600	130.0	69.5	140.0	240.0	315.0	-	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS high	400	92.5	51.0	105.0	205.0	280.0	-	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS high(3)	400	94.0	52.0	110.0	205.0	280.0	-	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS low	400	78.5	40.5	98.5	195.0	265.0	415.0	mA
IDD	Supply current in Run mode	All peripherals enabled	VOS low	300	64.0	33.0	83.0	180.0	250.0	400.0	mA

Table 38 (pages 172–172)

Table 38 · 29 columns × 18 rows · p.172–172 · CSV

Symbol	Parameter		Conditions										Typ LDO		Typ SMPS				Max(1) LDO								Unit
Symbol	Parameter		Conditions										Typ LDO		Typ SMPS				TJ =25 °C	TJ =85 °C			TJ =105 °C		TJ =130 °C		Unit
IDD(Stop)	Stop	Stop	Flash memory in low-power mode	Flash memory in low-power mode	Flash memory in low-power mode	Flash memory in low-power mode	Flash memory in low-power mode	SVOS high	SVOS high	SVOS high	SVOS high	SVOS high	1.450	1.450	0.700	0.700	0.700	0.700	11.0	66.5	66.5	66.5	115.0	115.0	200.0	200.0	mA	mA
IDD(Stop)	Stop	Stop	Flash memory in low-power mode	Flash memory in low-power mode	Flash memory in low-power mode	Flash memory in low-power mode	Flash memory in low-power mode	SVOS low	SVOS low	SVOS low	SVOS low	SVOS low	0.605	0.605	0.265	0.265	0.265	0.265	4.3	32.5	32.5	32.5	56.0	56.0	105.0	105.0	mA	mA
IDD(Stop)	Stop	Stop	Flash memory in normal mode	Flash memory in normal mode	Flash memory in normal mode	Flash memory in normal mode	Flash memory in normal mode	SVOS high	SVOS high	SVOS high	SVOS high	SVOS high	1.500	1.500	0.705	0.705	0.705	0.705	11.0	66.5	66.5	66.5	115.0	115.0	200.0	200.0	mA	mA
IDD(Stop)	Stop	Stop	Flash memory in normal mode	Flash memory in normal mode	Flash memory in normal mode	Flash memory in normal mode	Flash memory in normal mode	SVOS low	SVOS low	SVOS low	SVOS low	SVOS low	0.605	0.605	0.265	0.265	0.265	0.265	4.3	32.5	32.5	32.5	56.0	56.0	105.0	105.0	mA	mA
1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode	1. Guaranteed by characterization results unless otherwise specified. Refer to Section 6.3.3: SMPS step-down converter for the SMPS maximum consumption. Table 42. Typical and maximum current consumption in Standby mode
Smbol	Smbol	Parameter	Parameter	Parameter	Conditions	Conditions	Conditions	Conditions	Conditions	Typ	Typ	Typ	Typ	Typ	Typ	Typ	Typ	Max (3.6 V)(1)	Max (3.6 V)(1)	Max (3.6 V)(1)	Max (3.6 V)(1)	Max (3.6 V)(1)	Max (3.6 V)(1)	Max (3.6 V)(1)	Max (3.6 V)(1)	Max (3.6 V)(1)	Max (3.6 V)(1)	Unit
Smbol	Smbol	Parameter	Parameter	Parameter	Backup SRAM	Backup SRAM	RTC and LSE(2)	RTC and LSE(2)	RTC and LSE(2)	1.8 V	2.4 V	2.4 V	2.4 V	3 V	3 V	3.3 V	3.3 V	TJ =25 °C	TJ =25 °C	TJ =25 °C	TJ =85 °C	TJ =85 °C	TJ =85 °C	TJ =105 °C	TJ =105 °C	TJ =130 °C	TJ =130 °C	Unit
IDD (Standby)	IDD (Standby)	Supply current in Standby mode, IWDG OFF	Supply current in Standby mode, IWDG OFF	Supply current in Standby mode, IWDG OFF	OFF	OFF	OFF	OFF	OFF	2.4	2.6	2.6	2.6	2.8	2.8	3.0	3.0	5.4	5.4	5.4	15.5	15.5	15.5	31.5	31.5	84.5	84.5	µA
IDD (Standby)	IDD (Standby)	Supply current in Standby mode, IWDG OFF	Supply current in Standby mode, IWDG OFF	Supply current in Standby mode, IWDG OFF	ON	ON	OFF	OFF	OFF	3.9	4.2	4.2	4.2	4.5	4.5	4.7	4.7	8.6	8.6	8.6	40.5	40.5	40.5	97.0	97.0	160.0	160.0	µA
IDD (Standby)	IDD (Standby)	Supply current in Standby mode, IWDG OFF	Supply current in Standby mode, IWDG OFF	Supply current in Standby mode, IWDG OFF	OFF	OFF	ON	ON	ON	3.0	3.1	3.1	3.1	3.5	3.5	3.7	3.7	-	-	-	-	-	-	-	-	-	-	µA
IDD (Standby)	IDD (Standby)	Supply current in Standby mode, IWDG OFF	Supply current in Standby mode, IWDG OFF	Supply current in Standby mode, IWDG OFF	ON	ON	ON	ON	ON	4.2	4.6	4.6	4.6	5.0	5.0	5.3	5.3	-	-	-	-	-	-	-	-	-	-	µA
1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode	1. Guaranteed by characterization results. 2. The LSE is in Low-drive mode. Table 43. Typical and maximum current consumption in VBAT mode
Sym-bol	Parameter	Parameter	Parameter	Conditions	Conditions	Conditions	Conditions	Conditions	Typ	Typ	Typ	Typ	Typ	Typ	Typ	Typ	Typ	Typ	Max (3.6 V)(1)	Max (3.6 V)(1)	Max (3.6 V)(1)	Max (3.6 V)(1)	Max (3.6 V)(1)	Max (3.6 V)(1)	Max (3.6 V)(1)	Max (3.6 V)(1)	Max (3.6 V)(1)	Unit
Sym-bol	Parameter	Parameter	Parameter	Backup SRAM	Backup SRAM	RTC and LSE(2)	RTC and LSE(2)	RTC and LSE(2)	1.62 V	1.62 V	1.62 V	2.4 V	2.4 V	3 V	3 V	3 V	3.3 V	3.3 V	25 TJ °C =	25 TJ °C =	25 TJ °C =	TJ =85 °C	TJ =85 °C	TJ =105 °C	TJ =105 °C	TJ =130 °C	TJ =130 °C	Unit
IDD(VBAT)	Supply current in VBAT mode	Supply current in VBAT mode	Supply current in VBAT mode	OFF	OFF	OFF	OFF	OFF	0.009	0.009	0.009	0.013	0.013	0.021	0.021	0.021	0.037	0.037	0.22	0.22	0.22	3.40	3.40	8.70	8.70	27.00	27.00	µA
IDD(VBAT)	Supply current in VBAT mode	Supply current in VBAT mode	Supply current in VBAT mode	ON	ON	OFF	OFF	OFF	1.5	1.5	1.5	1.8	1.8	1.8	1.8	1.8	1.9	1.9	2.85	2.85	2.85	19.00	19.00	41.00	41.00	87.00	87.00	µA
IDD(VBAT)	Supply current in VBAT mode	Supply current in VBAT mode	Supply current in VBAT mode	OFF	OFF	ON	ON	ON	0.4	0.4	0.4	0.5	0.5	0.7	0.7	0.7	0.8	0.8	1.10	1.10	1.10	4.25	4.25	9.55	9.55	28.50	28.50	µA
IDD(VBAT)	Supply current in VBAT mode	Supply current in VBAT mode	Supply current in VBAT mode	ON	ON	ON	ON	ON	1.9	1.9	1.9	2.1	2.1	2.4	2.4	2.4	2.5	2.5	3.70	3.70	3.70	19.50	19.50	41.50	41.50	89.00	89.00	µA

Table 39 (pages 174–174)

Table 39 · 8 columns × 16 rows · p.174–174 · CSV

Symbol	Parameter	Conditions	frcc_c_ck (MHz)	Memory frequency( MHz)	Typ	Max(3) TJ = 105°C	Unit
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	400	200	9.00	9.5	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	320	160	7.10	7.7	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	266	133	5.80	6.3	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	200	100	4.50	4.9	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	180	90	4.05	4.5	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	120	60	2.70	3.0	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	60	30	1.35	1.5	mA
1. MACRONIX_MX66UW1G45G. 2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case. 3. Guaranteed by characterization results. Table 45. Typical and maximum current consumption in Run mode, code with data processing running from 16-bit memory(1) , cache OFF(2)	1. MACRONIX_MX66UW1G45G. 2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case. 3. Guaranteed by characterization results. Table 45. Typical and maximum current consumption in Run mode, code with data processing running from 16-bit memory(1) , cache OFF(2)	1. MACRONIX_MX66UW1G45G. 2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case. 3. Guaranteed by characterization results. Table 45. Typical and maximum current consumption in Run mode, code with data processing running from 16-bit memory(1) , cache OFF(2)	1. MACRONIX_MX66UW1G45G. 2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case. 3. Guaranteed by characterization results. Table 45. Typical and maximum current consumption in Run mode, code with data processing running from 16-bit memory(1) , cache OFF(2)	1. MACRONIX_MX66UW1G45G. 2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case. 3. Guaranteed by characterization results. Table 45. Typical and maximum current consumption in Run mode, code with data processing running from 16-bit memory(1) , cache OFF(2)	1. MACRONIX_MX66UW1G45G. 2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case. 3. Guaranteed by characterization results. Table 45. Typical and maximum current consumption in Run mode, code with data processing running from 16-bit memory(1) , cache OFF(2)	1. MACRONIX_MX66UW1G45G. 2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case. 3. Guaranteed by characterization results. Table 45. Typical and maximum current consumption in Run mode, code with data processing running from 16-bit memory(1) , cache OFF(2)	1. MACRONIX_MX66UW1G45G. 2. Data are in DTCM for best computation performance, cache has no influence on consumption in this case. 3. Guaranteed by characterization results. Table 45. Typical and maximum current consumption in Run mode, code with data processing running from 16-bit memory(1) , cache OFF(2)
Symbol	Parameter	Conditions	frcc_c_ck (MHz)	Memory frequency( MHz)	Typ	Max(3) TJ = 105°C	Unit
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	400	200	4.55	5.0	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	320	160	3.70	4.1	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	266	133	3.10	3.4	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	200	100	2.35	2.6	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	180	90	2.10	2.4	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	120	60	1.45	1.6	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	60	30	0.76	0.8	mA

Table 40 (pages 175–176)

Table 40 · 8 columns × 32 rows · p.175–176 · CSV

Symbol	Parameter	Conditions	frcc_c_ck (MHz)	Memory frequency( MHz)	Typ	Max(2) TJ = 105°C	Unit
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	400	200	48.0	52.0	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	320	160	38.0	42.0	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	266	133	32.0	35.5	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	200	100	25.0	27.5	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	180	90	22.5	25.0	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	120	60	15.0	17.0	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	60	30	7.6	8.5	mA
1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG 2. Guaranteed by characterization results. Table 47. Typical and maximum current consumption: data write 25% toggle on 16-bit memory(1)	1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG 2. Guaranteed by characterization results. Table 47. Typical and maximum current consumption: data write 25% toggle on 16-bit memory(1)	1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG 2. Guaranteed by characterization results. Table 47. Typical and maximum current consumption: data write 25% toggle on 16-bit memory(1)	1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG 2. Guaranteed by characterization results. Table 47. Typical and maximum current consumption: data write 25% toggle on 16-bit memory(1)	1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG 2. Guaranteed by characterization results. Table 47. Typical and maximum current consumption: data write 25% toggle on 16-bit memory(1)	1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG 2. Guaranteed by characterization results. Table 47. Typical and maximum current consumption: data write 25% toggle on 16-bit memory(1)	1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG 2. Guaranteed by characterization results. Table 47. Typical and maximum current consumption: data write 25% toggle on 16-bit memory(1)	1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG 2. Guaranteed by characterization results. Table 47. Typical and maximum current consumption: data write 25% toggle on 16-bit memory(1)
Symbol	Parameter	Conditions	frcc_c_ck (MHz)	Memory frequency( MHz)	Typ	Max(2) TJ = 105°C	Unit
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	400	200	26.50	29.0	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	320	160	21.50	23.5	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	266	133	18.00	20.0	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	200	100	14.00	15.5	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	180	90	12.50	14.0	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	120	60	8.50	9.4	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	60	30	4.25	4.8	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	400	200	16.00	17.5	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	320	160	13.00	14.0	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	266	133	11.00	12.0	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	200	100	8.35	9.3	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	180	90	7.55	8.4	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	120	60	5.10	5.7	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	60	30	2.55	2.9	mA
1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG. 2. Guaranteed by characterization results. Table 49. Typical and maximum current consumption: data write 6.25% toggle on 16-bit memory(1)	1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG. 2. Guaranteed by characterization results. Table 49. Typical and maximum current consumption: data write 6.25% toggle on 16-bit memory(1)	1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG. 2. Guaranteed by characterization results. Table 49. Typical and maximum current consumption: data write 6.25% toggle on 16-bit memory(1)	1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG. 2. Guaranteed by characterization results. Table 49. Typical and maximum current consumption: data write 6.25% toggle on 16-bit memory(1)	1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG. 2. Guaranteed by characterization results. Table 49. Typical and maximum current consumption: data write 6.25% toggle on 16-bit memory(1)	1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG. 2. Guaranteed by characterization results. Table 49. Typical and maximum current consumption: data write 6.25% toggle on 16-bit memory(1)	1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG. 2. Guaranteed by characterization results. Table 49. Typical and maximum current consumption: data write 6.25% toggle on 16-bit memory(1)	1. AP_Memory_Hexa-SPI_PSRAM_APS256XXN OBR-BG. 2. Guaranteed by characterization results. Table 49. Typical and maximum current consumption: data write 6.25% toggle on 16-bit memory(1)
Symbol	Parameter	Conditions	frcc_c_ck (MHz)	Memory frequency (MHz)	Typ	Max(2) TJ = 105°C	Unit
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	400	200	10.50	11.5	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	320	160	8.55	9.5	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	266	133	7.35	8.0	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	200	100	5.60	6.2	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	180	90	5.05	5.6	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	120	60	3.40	3.8	mA
IDD_XSPI	XSPI current in Run mode	VDDXSPIx =1.8 V	60	30	1.70	1.9	mA

Table 41 (pages 179–184)

Table 41 · 7 columns × 134 rows · p.179–184 · CSV

Bus	Peripheral	LDO		SMPS		Unit
Bus	Peripheral	VOS high	VOS low	VOS high	VOS low	Unit
AHB1	ADC1/2 registers	2.57	1.89	1.34	1.00	µA/MHz
AHB1	ADC1/2 kernel	0.55	0.49	0.35	0.34	µA/MHz
AHB1	ADF1 registers	1.19	1.06	0.59	0.52	µA/MHz
AHB1	ADF1 kernel	2.45	2.18	1.23	1.09	µA/MHz
AHB1	ETHERNET MAC registers	11.44	9.56	6.05	4.90	µA/MHz
AHB1	ETHERNET MAC kernel	2.38	2.12	1.19	1.06	µA/MHz
AHB1	ETHERNETRX	0.44	0.39	0.22	0.20	µA/MHz
AHB1	ETHERNETTX	0.50	0.44	0.25	0.22	µA/MHz
AHB1	GPDMA1	1.27	0.99	0.62	0.45	µA/MHz
AHB1	OTG_FS registers	7.06	5.97	3.82	3.07	µA/MHz
AHB1	OTG_FS kernel	0.27	0.24	0.14	0.12	µA/MHz
AHB1	OTG_HS	15.46	13.37	8.33	6.85	µA/MHz
AHB1	USBPHYC registers	0.23	0.20	0.08	0.07	µA/MHz
AHB1	USBPHYC kernel	1.10	0.98	0.40	0.36	µA/MHz
AHB2	CORDIC	0.33	0.29	0.21	0.19	µA/MHz
AHB2	PSSI registers	1.85	1.69	1.05	0.85	µA/MHz
AHB2	PSSI kernel	0.43	0.33	0.20	0.18	µA/MHz
AHB2	SDMMC2	7.63	6.76	4.19	3.43	µA/MHz
AHB2	SRAM1	0.37	0.33	0.25	0.22	µA/MHz
AHB2	SRAM2	0.46	0.42	0.30	0.27	µA/MHz
AHB3	HASH	1.10	0.95	0.64	0.55	µA/MHz
AHB3	PKA	4.79	4.20	2.64	2.20	µA/MHz
AHB3	RNG	0.82	0.69	0.46	0.38	µA/MHz
AHB4	BKPRAM	1.34	1.17	0.84	0.75	µA/MHz
AHB4	CRC	0.25	0.22	0.13	0.10	µA/MHz
AHB4	GPIOA	0.14	0.12	0.09	0.07	µA/MHz
AHB4	GPIOB	0.14	0.14	0.10	0.08	µA/MHz
AHB4	GPIOC	0.16	0.14	0.12	0.10	µA/MHz
AHB4	GPIOD	0.12	0.11	0.07	0.06	µA/MHz
AHB4	GPIOE	0.12	0.11	0.07	0.06	µA/MHz
AHB4	GPIOF	0.16	0.14	0.08	0.06	µA/MHz
AHB4	GPIOG	0.13	0.12	0.09	0.08	µA/MHz
AHB4	GPIOH	0.15	0.13	0.08	0.07	µA/MHz
AHB4	GPIOM	0.17	0.16	0.09	0.08	µA/MHz
AHB4	GPION	0.17	0.15	0.09	0.08	µA/MHz
AHB4	GPIOO	0.31	0.28	0.21	0.18	µA/MHz
AHB4	GPIOP	0.30	0.27	0.22	0.19	µA/MHz
AHB5	DMA2D	1.29	1.15	0.78	0.65	µA/MHz
AHB5	FMC/MCE3 registers	2.47	2.21	1.39	1.13	µA/MHz
AHB5	FMC/MCE3 kernel	4.71	4.21	2.58	2.15	µA/MHz
AHB5	GFXMMU	0.63	0.59	0.41	0.29	µA/MHz
AHB5	GPU2D	6.00	5.37	3.37	2.73	µA/MHz
AHB5	HPDMA1	0.91	0.84	0.51	0.42	µA/MHz
AHB5	JPEG	1.47	1.38	0.86	0.68	µA/MHz
AHB5	SDMMC1	6.88	6.13	3.82	3.15	µA/MHz
AHB5	XSPI1/MCE1 registers	0.86	0.77	0.49	0.43	µA/MHz
AHB5	XSPI1/MCE1 kernel	1.02	0.99	0.57	0.51	µA/MHz
AHB5	XSPI2/MCE2 registers	0.74	0.71	0.46	0.37	µA/MHz
AHB5	XSPI2/MCE2 kernel	1.03	0.93	0.54	0.48	µA/MHz
AHB5	XSPIM	0.22	0.20	0.11	0.10	µA/MHz
AHB5	Flash	13.75	12.19	7.58	6.19	µA/MHz
AHB5	DTCM1	0.69	0.62	0.43	0.34	µA/MHz
AHB5	DTCM2	0.50	0.44	0.31	0.27	µA/MHz
AHB5	ITCM	0.72	0.64	0.44	0.37	µA/MHz
AHB5	AXI SRAM	10.02	8.95	5.56	4.52	µA/MHz
APB1	HDMI-CEC register	0.90	0.80	0.34	0.30	µA/MHz
APB1	HDMI-CEC kernel	8.65	7.69	4.33	3.85	µA/MHz
APB1	CRS	7.32	6.14	3.9	3.06	µA/MHz
APB1	FDCAN1/2 register	6.53	5.54	3.4	2.75	µA/MHz
APB1	FDCAN1/2 kernel	3.64	3.25	1.87	1.54	µA/MHz
APB1	I2C1 register	1.34	1.19	0.59	0.52	µA/MHz
APB1	I2C1 kernel	4.54	4.01	2.53	2.04	µA/MHz
APB1	I2C2 register	1.27	1.13	0.49	0.44	µA/MHz
APB1	I2C2 kernel	1.65	1.52	0.89	0.79	µA/MHz
APB1	I2C3 register	1.36	1.21	0.51	0.45	µA/MHz
APB1	I2C3 kernel	2.14	1.87	1.22	0.96	µA/MHz
APB1	LPTIM1 registers	1.33	1.18	0.63	0.50	µA/MHz
APB1	LPTIM1 kernel	3.38	2.93	1.83	1.50	µA/MHz
APB1	MDIOS	2.83	2.52	1.35	1.04	µA/MHz
APB1	SPDIF-RX registers	0.99	0.71	0.37	0.33	µA/MHz
APB1	SPDIF-RX kernel	2.34	2.21	1.33	1.10	µA/MHz
APB1	SPI2 registers	1.84	1.35	0.87	0.67	µA/MHz
APB1	SPI2 kernel	2.14	1.92	0.99	0.88	µA/MHz
APB1	SPI3 registers	1.79	1.41	0.84	0.62	µA/MHz
APB1	SPI3 kernel	1.91	1.78	1.07	0.98	µA/MHz
APB1	TIM12	1.90	1.52	0.92	0.72	µA/MHz
APB1	TIM13	1.39	1.04	0.59	0.42	µA/MHz
APB1	TIM14	1.49	1.1	0.64	0.51	µA/MHz
APB1	TIM2	3.40	2.97	1.83	1.49	µA/MHz
APB1	TIM3	3.56	3.04	1.87	1.50	µA/MHz
APB1	TIM4	3.58	3.11	1.85	1.49	µA/MHz
APB1	TIM5	3.48	3.01	1.81	1.45	µA/MHz
APB1	TIM6	1.02	0.86	0.51	0.45	µA/MHz
APB1	TIM7	0.91	0.74	0.45	0.4	µA/MHz
APB1	UART4 registers	2.12	1.63	1.07	0.78	µA/MHz
APB1	UART4 kernel	3.53	3.05	1.95	1.55	µA/MHz
APB1	UART5 registers	2.13	1.59	1.10	0.98	µA/MHz
APB1	UART5 kernel	3.62	3.14	1.94	1.61	µA/MHz
APB1	UART7 registers	2.24	1.68	1.14	1.01	µA/MHz
APB1	UART7 kernel	3.43	3.02	1.95	1.54	µA/MHz
APB1	UART8 registers	2.27	1.71	1.16	1.03	µA/MHz
APB1	UART8 kernel	3.61	3.17	1.96	1.58	µA/MHz
APB1	UCPD1	2.61	2.21	1.25	1.06	µA/MHz
APB1	USART2 registers	2.32	1.87	1.12	0.86	µA/MHz
APB1	USART2 kernel	3.41	3.03	1.89	1.55	µA/MHz
APB1	USART3 registers	2.07	1.66	1.04	0.79	µA/MHz
APB1	USART3 kernel	4.02	3.60	2.20	1.82	µA/MHz
APB1	WWDG	1.25	1.11	0.57	0.46	µA/MHz
APB2	SAI1 registers	1.17	1.01	0.56	0.41	µA/MHz
APB2	SAI1 kernel	1.56	1.38	0.87	0.68	µA/MHz
APB2	SAI2 registers	1.19	1.02	0.64	0.57	µA/MHz
APB2	SAI2kernel	1.41	1.22	0.73	0.64	µA/MHz
APB2	SPI1 registers	1.29	1.14	0.68	0.54	µA/MHz
APB2	SPI1 kernel	2.15	1.87	1.08	0.95	µA/MHz
APB2	SPI4 registers	1.25	1.11	0.66	0.53	µA/MHz
APB2	SPI4 kernel	1.48	1.35	0.88	0.69	µA/MHz
APB2	SPI5 registers	1.3	1.22	0.60	0.52	µA/MHz
APB2	SPI5kernel	1.69	1.42	0.91	0.69	µA/MHz
APB2	TIM1	4.50	3.97	2.43	1.98	µA/MHz
APB2	TIM15	2.25	2.02	1.25	0.99	µA/MHz
APB2	TIM16	1.54	1.45	0.88	0.69	µA/MHz
APB2	TIM17	1.60	1.42	0.87	0.74	µA/MHz
APB2	TIM9	1.39	1.24	0.67	0.58	µA/MHz
APB2	USART1 registers	1.50	1.33	0.78	0.62	µA/MHz
APB2	USART1 kernel	4.03	3.47	2.20	1.77	µA/MHz
APB4	DTS	2.10	1.63	1.01	0.89	µA/MHz
APB4	LPTIM2 registers	1.24	1.1	0.57	0.49	µA/MHz
APB4	LPTIM2 kernel	3.17	2.78	1.78	1.46	µA/MHz
APB4	LPTIM3 registers	1.23	0.97	0.61	0.51	µA/MHz
APB4	LPTIM3 kernel	3.35	2.99	1.84	1.5	µA/MHz
APB4	LPTIM4 registers	0.69	0.56	0.35	0.26	µA/MHz
APB4	LPTIM4 kernel	1.90	1.79	1.08	0.87	µA/MHz
APB4	LPTIM5 registers	0.73	0.58	0.36	0.31	µA/MHz
APB4	LPTIM5 kernel	2.24	1.92	1.25	1.04	µA/MHz
APB4	LPUART1 registers	1.39	1.07	0.68	0.64	µA/MHz
APB4	LPUART1 KERNEL	2.46	2.25	1.40	1.12	µA/MHz
APB4	RTCAPB	1.85	1.51	0.93	0.80	µA/MHz
APB4	SBS	0.71	0.63	0.33	0.29	µA/MHz
APB4	SPI6 registers	1.58	1.16	0.74	0.68	µA/MHz
APB4	SPI6 kernel	1.69	1.55	0.91	0.77	µA/MHz
APB4	VREF	0.27	0.24	0.12	0.11	µA/MHz
APB5	DCMIPP	5.71	5.03	3.14	2.60	µA/MHz
APB5	GFXTIM	1.12	1.03	0.67	0.56	µA/MHz
APB5	LTDC	3.42	3.03	1.87	1.55	µA/MHz

Table 42 (pages 185–185)

Table 42 · 6 columns × 10 rows · p.185–185 · CSV

Symbol	Parameter	Conditions	Typ(1)	Max(1)(2)(3)	Unit
t WUSLEEP(4)	Wakeup from Sleep	-	15	16	CPU clock cycles
t WUDSTOP(4)	Wakeup from Stop	SVOS low, HSI, Flash memory in normal mode	42.5	46.0	µs
t WUDSTOP(4)	Wakeup from Stop	SVOS low, HSI, Flash memory in low-power mode	42.5	46.0	µs
t WUDSTOP(4)	Wakeup from Stop	SVOS high, HSI, Flash memory in normal mode	16.0	17.5	µs
t WUDSTOP(4)	Wakeup from Stop	SVOS high, HSI, Flash memory in low-power mode	20.0	21.0	µs
t WUDSTOP(4)	Wakeup from Stop	SVOS low, CSI, Flash memory in normal mode	65.0	71.0	µs
t WUDSTOP(4)	Wakeup from Stop	SVOS low, CSI, Flash memory in low power mode	71.5	77.5	µs
t WUDSTOP(4)	Wakeup from Stop	SVOS high, CSI, Flash memory in normal mode	32.0	35.0	µs
t WUDSTOP(4)	Wakeup from Stop	SVOS high, CSI, Flash memory in low-power mode	48.5	54.0	µs
t WUSTDBY(4)	Wakeup from Standby mode	-	280.0	535.0	µs

Table 43 (pages 186–186)

Table 43 · 7 columns × 7 rows · p.186–186 · CSV

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fHSE_ext	User external clock source frequency	External digital/ analog clock	4	25	50	MHz
VHSEH	Digital OSC_IN input high-level voltage	External digital clock	0.7 VDD	-	VDD	V
VHSEL	Digital OSC_IN input low-level voltage	External digital cwlock	VSS	-	0.3 VDD	V
t W(HSE)(2)	OSC_IN high or low time(2)	External digital clock	7	-	-	ns
VlswHSE (VHSEH -VHSEL )(3)	Analog low swing OSC_IN peak-to-peak amplitud(3) e	External Analog Low Swing Clock	0.2	-	2/3 VDD	V
DuCyHSE	Analog low swing OSC_IN duty cycle	External analog low-swing clock	45	50	55	%
trHSE /tfHSE	Analog low swing OSC_IN rise and fall time(3)	External analog low -swing clock 10% to 90%	0.05 / fHSE_ext	-	0.3 / fHSE_ext	ns

Table 44 (pages 191–191)

Table 44 · 7 columns × 10 rows · p.191–191 · CSV

Symbol	Parameter	Operating conditions(2)	Min	Typ	Max	Unit
F	Oscillator frequency	-	4	-	50	MHz
RF	Feedback resistor	-	-	200	-	kΩ
IDD(HSE)	HSE current consumption	During startup(3)	-	-	10	mA
IDD(HSE)	HSE current consumption	VDD =3 V, Rm=20 Ω CL =10 pF at 4 MHz	-	0.44	-	mA
IDD(HSE)	HSE current consumption	VDD =3 V, Rm=20 Ω CL =10 pF at 8 MHz	-	0.44	-	mA
IDD(HSE)	HSE current consumption	VDD =3 V, Rm=20 Ω CL =10 pF at 16 MHz	-	0.55	-	mA
IDD(HSE)	HSE current consumption	VDD =3 V, Rm=20 Ω CL =10 pF at 32 MHz	-	0.67	-	mA
IDD(HSE)	HSE current consumption	VDD =3 V, Rm=20 Ω CL =10 pF at 48 MHz	-	1.17	-	mA
Gmcritmax	Maximum critical crystal gm	Startup	-	-	1.5	mA/V
t SU(4)	Start-up time	VDD is stabilized	-	2	-	ms

Table 45 (pages 194–195)

Table 45 · 7 columns × 24 rows · p.194–195 · CSV

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
fHSI48	HSI48 frequency	VDD =3.3 V, TJ=30 °C	47.5(1)	48	48.5(1)	MHz
TRIM(2)	USER trimming step	-	-	0.175	0.250	%
USER TRIMCOVERAGE(3)	USER trimming coverage	± 32 steps	±4.70	±5.6	-	%
DuCy (HSI48)(2)	Duty cycle	-	45	-	55	%
ACCHSI48_REL(3)(4)	Accuracy of the HSI48 oscillator over temperature (factory calibrated)	TJ =-40 to 130 °C	-4.5	-	3.5	%
ΔVDD (HSI48)(2)(4)	HSI48 oscillator frequency drift with V DD(5) (the reference is 3.3 V)	VDD =3 to 3.6 V	-	0.025	0.05	%
ΔVDD (HSI48)(2)(4)	HSI48 oscillator frequency drift with V DD(5) (the reference is 3.3 V)	VDD =1.62 V to 3.6 V	-	0.05	0.1	%
t su(HSI48)(2)	HSI48 oscillator start-up time	-	-	2.1	4.0	µs
I DD(HSI48)(2)	HSI48 oscillator power consumption	-	-	350	400	µA
NT jitter(2)	Next transition jitter Accumulated jitter on 28 cycles(6)	-	-	± 0.15	-	ns
PT jitter(2)	Paired transition jitter Accumulated jitter on 56 cycles(6)	-	-	± 0.25	-	ns
fHSI	HSI frequency	VDD =3.3 V, TJ =30 °C	63.7(2)	64	64.3(2)	MHz
TRIM	HSI user trimming step	Trimming is not a multiple of 32	-	0.24	0.32	%
TRIM	HSI user trimming step	Trimming is 128, 256 and 384	-5.2	-1.8	-	%
TRIM	HSI user trimming step	Trimming is 64, 192, 320 and 448	-1.4	-0.8	-	%
TRIM	HSI user trimming step	Other trimming are a multiple of 32 (not including multiple of 64 and 128)	-0.6	-0.25	-	%
DuCy(HSI)	Duty cycle	-	45	-	55	%
ΔVDD (HSI)	HSI oscillator frequency drift over VDD (the reference is 3.3 V)	VDD =1.71 to 3.6 V	-0.12	-	0.03	%
ΔTEMP(HSI)	HSI oscillator frequency drift over temperature (the reference is 64 MHz)	TJ =-20 to 105 °C	-1(3)	-	1(3)	%
ΔTEMP(HSI)	HSI oscillator frequency drift over temperature (the reference is 64 MHz)	TJ =-40 to TJ max °C	-2(3)	-	1(3)	%
tsu (HSI)	HSI oscillator start-up time	-	-	1.4	2	µs
tstab (HSI)	HSI oscillator stabilization time	at 1% of target frequency	-	4	8	µs
tstab (HSI)	HSI oscillator stabilization time	at 5% of target frequency	-	-	4	µs
IDD (HSI)	HSI oscillator power consumption	-	-	300	400	µA

Table 46 (pages 196–196)

Table 46 · 11 columns × 19 rows · p.196–196 · CSV

Symbol		Parameter		Conditions	Min	Typ	Max		Unit
fCSI	fCSI	CSI frequency	CSI frequency	VDD =3.3 V, TJ =30 °C	3.96(2)	4	4.04(2)	4.04(2)	MHz	MHz
TRIM	TRIM	CSI trimming step	CSI trimming step	Trimming is not a multiple of 16	-	0.40	0.75	0.75	%	%
TRIM	TRIM	CSI trimming step	CSI trimming step	Trimming is a multiple of 32	-4.75	-2.75	0.75	0.75	%	%
TRIM	TRIM	CSI trimming step	CSI trimming step	Other trimming values not multiple of 16 (excluding multiple of 32)	-0.43	0.00	0.75	0.75	%	%
DuCy(CSI)	DuCy(CSI)	Duty cycle	Duty cycle	-	45	-	55	55	%	%
ΔTEMP (CSI)	ΔTEMP (CSI)	CSI oscillator frequency drift over temperature	CSI oscillator frequency drift over temperature	TJ = 0 to 85 °C	-3.7(3)	-	4.5(3)	4.5(3)	%	%
ΔTEMP (CSI)	ΔTEMP (CSI)	CSI oscillator frequency drift over temperature	CSI oscillator frequency drift over temperature	TJ = -40 to 130 °C	-11(3)	-	7.5(3)	7.5(3)	%	%
ΔVDD (CSI)	ΔVDD (CSI)	CSI oscillator frequency drift over VDD	CSI oscillator frequency drift over VDD	VDD = 1.71 to 3.6 V	-0.06	-	0.06	0.06	%	%
tsu(CSI)	tsu(CSI)	CSI oscillator startup time	CSI oscillator startup time	-	-	1	2	2	µs	µs
tstab(CSI)	tstab(CSI)	CSI oscillator stabilization time (to reach ± 3% of fCSI )	CSI oscillator stabilization time (to reach ± 3% of fCSI )	-	-	-	4	4	cycle	cycle
IDD(CSI)	IDD(CSI)	CSI oscillator power consumption	CSI oscillator power consumption	-	-	23	30	30	µA	µA
1. Guaranteed by design, unless otherwise specified. 2. Guaranteed by test in production. 3. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 61. LSI oscillator characteristics	1. Guaranteed by design, unless otherwise specified. 2. Guaranteed by test in production. 3. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 61. LSI oscillator characteristics	1. Guaranteed by design, unless otherwise specified. 2. Guaranteed by test in production. 3. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 61. LSI oscillator characteristics	1. Guaranteed by design, unless otherwise specified. 2. Guaranteed by test in production. 3. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 61. LSI oscillator characteristics	1. Guaranteed by design, unless otherwise specified. 2. Guaranteed by test in production. 3. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 61. LSI oscillator characteristics	1. Guaranteed by design, unless otherwise specified. 2. Guaranteed by test in production. 3. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 61. LSI oscillator characteristics	1. Guaranteed by design, unless otherwise specified. 2. Guaranteed by test in production. 3. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 61. LSI oscillator characteristics	1. Guaranteed by design, unless otherwise specified. 2. Guaranteed by test in production. 3. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 61. LSI oscillator characteristics	1. Guaranteed by design, unless otherwise specified. 2. Guaranteed by test in production. 3. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 61. LSI oscillator characteristics	1. Guaranteed by design, unless otherwise specified. 2. Guaranteed by test in production. 3. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 61. LSI oscillator characteristics	1. Guaranteed by design, unless otherwise specified. 2. Guaranteed by test in production. 3. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 61. LSI oscillator characteristics
Symbol	Parameter	Parameter	Conditions	Conditions	Min	Typ	Typ	Max	Max	Unit
fLSI	LSI frequency	LSI frequency	VDD = 3.3 V, TJ = 25 °C	VDD = 3.3 V, TJ = 25 °C	31.4(1)	32	32	32.6(1)	32.6(1)	kHz
fLSI	LSI frequency	LSI frequency	TJ = –40 to 110 °C, VDD = 1.62 to 3.6 V	TJ = –40 to 110 °C, VDD = 1.62 to 3.6 V	29.76(2)	-	-	33.6(2)	33.6(2)	kHz
fLSI	LSI frequency	LSI frequency	TJ = –40 to 130 °C, VDD = 1.71 to 3.6 V	TJ = –40 to 130 °C, VDD = 1.71 to 3.6 V	29.4(2)	-	-	33.6(2)	33.6(2)	kHz
t su(LSI)(3)	LSI oscillator startup time	LSI oscillator startup time	-	-	-	80	80	130	130	µs
t stab(LSI)(3)	LSI oscillator stabilization time (5% of final value)	LSI oscillator stabilization time (5% of final value)	-	-	-	120	120	170	170	µs
I DD(LSI)(3)	LSI oscillator power consumption	LSI oscillator power consumption	-	-	-	130	130	280	280	nA

Table 47 (pages 197–198)

Table 47 · 8 columns × 34 rows · p.197–198 · CSV

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
fPLL_IN	PLL input clock	-	-	2	-	16	MHz
fPLL_IN	PLL input clock duty cycle	-	-	10	-	90	%
fPLL_P_OUT	PLL multiplier output clock P, Q, R, S, T	VOS high	VOS high	1.5	-	600(2)	MHz
fPLL_P_OUT	PLL multiplier output clock P, Q, R, S, T	VOS low	VOS low	1.5	-	400(2)	MHz
fVCO_OUT	PLL VCO output	-	-	192	-	836(3)	MHz
tLOCK	PLL lock time	Normal mode	Normal mode	15	50	150(3)	µs
tLOCK	PLL lock time	Sigma-delta mode (CKIN ≥ 8 MHz)	Sigma-delta mode (CKIN ≥ 8 MHz)	25	65	170	µs
Jitter (RMS)	Cycle-to-cycle jitter multiplier output clock P, Q, R, S, T	fVCO_OUT = 192 MHz	fVCO_OUT = 192 MHz	-	35	-	±ps
Jitter (RMS)	Cycle-to-cycle jitter multiplier output clock P, Q, R, S, T	fVCO_OUT = 836 MHz	fVCO_OUT = 836 MHz	-	15	-	±ps
Jitter (RMS)	Period jitter multiplier output clock P, Q, R, S, T	fVCO_OUT = 192 MHz	fVCO_OUT = 192 MHz	-	32	-	±ps
Jitter (RMS)	Period jitter multiplier output clock P, Q, R, S, T	fVCO_OUT = 836 MHz	fVCO_OUT = 836 MHz	-	10	-	±ps
Jitter (RMS)	Long term jitter multiplier output clock P, Q, R, S, T	Normal mode (FPLL IN = 2 MHz), fVCO_OUT = 192 MHz	Normal mode (FPLL IN = 2 MHz), fVCO_OUT = 192 MHz	-	±0.18	-	%(4)
Jitter (RMS)	Long term jitter multiplier output clock P, Q, R, S, T	Normal mode (FPLL IN = 16 MHz), fVCO_OUT = 192 MHz	Normal mode (FPLL IN = 16 MHz), fVCO_OUT = 192 MHz	-	±0.5	-	%(4)
IDD(PLL)	PLL power consumption	fVCO_OUT = 192 MHz	VDDA	-	390	548	µA
IDD(PLL)	PLL power consumption	fVCO_OUT = 192 MHz	VCORE	-	590	3800	µA
IDD(PLL)	PLL power consumption	fVCO_OUT = 836 MHz	VDDA	-	1000	1100	µA
IDD(PLL)	PLL power consumption	fVCO_OUT = 836 MHz	VCORE	-	3500	9020	µA
fPLL_IN	PLL input clock	-	-	1	-	2	MHz
fPLL_IN	PLL input clock duty cycle	-	-	10	-	90	%
fPLL_P_OUT	PLL multiplier output clock P, Q, R, S, T	VOS high	VOS high	1.17	-	210	MHz
fPLL_P_OUT	PLL multiplier output clock P, Q, R, S, T	VOS low	VOS low	1.17	-	210	MHz
fVCO_OUT	PLL VCO output	-	-	150	-	420	MHz
tLOCK	PLL lock time	Normal mode	Normal mode	-	60(2)	100(2)	µs
tLOCK	PLL lock time	Sigma-delta mode	Sigma-delta mode	Forbidden	Forbidden	Forbidden	µs
Jitter (RMS)	Cycle-to-cycle jitter multiplier output clock P, Q, R, S, T	fVCO_OUT = 150 MHz	fVCO_OUT = 150 MHz	-	20	-	±ps
Jitter (RMS)	Cycle-to-cycle jitter multiplier output clock P, Q, R, S, T	fVCO_OUT = 420 MHz	fVCO_OUT = 420 MHz	-	12	-	±ps
Jitter (RMS)	Period jitter multiplier output clock P, Q, R, S, T	fVCO_OUT = 150 MHz	fVCO_OUT = 150 MHz	-	15	-	±ps
Jitter (RMS)	Period jitter multiplier output clock P, Q, R, S, T	fVCO_OUT = 420 MHz	fVCO_OUT = 420 MHz	-	8	-	±ps
Jitter (RMS)	Long-term jitter multiplier output clock P, Q, R, S, T	Normal mode (FPLL_IN = 2 MHz) fVCO_OUT = 150 MHz	Normal mode (FPLL_IN = 2 MHz) fVCO_OUT = 150 MHz	-	±0.35	-	%(3)
Jitter (RMS)	Long-term jitter multiplier output clock P, Q, R, S, T	Normal mode (FPLL_IN = 2 MHz) fVCO_OUT = 420 MHz	Normal mode (FPLL_IN = 2 MHz) fVCO_OUT = 420 MHz	-	±0.55	-
IDD(PLL)	PLL power consumption	fVCO_OUT = 150 MHz	VDDA	-	200	290	µA
IDD(PLL)	PLL power consumption	fVCO_OUT = 150 MHz	VCORE	-	625	4880	µA
IDD(PLL)	PLL power consumption	fVCO_OUT = 420 MHz	VDDA	-	460	510	µA
IDD(PLL)	PLL power consumption	fVCO_OUT = 420 MHz	VCORE	-	1690	6400	µA

Table 48 (pages 200–200)

Table 48 · 6 columns × 5 rows · p.200–200 · CSV

Symbol	Parameter	Conditions	Monitored frequency band	Max vs. [fHSE /fCPU ]	Unit
Symbol	Parameter	Conditions	Monitored frequency band	8/600 MHz	Unit
SEMI	Peak level(1)	VDD = 3.6 V, TA = 25 °C, BGA225 package, compliant with IEC61967-2	0.1 to 30 MHz	10	dBµV
SEMI	Peak level(1)	VDD = 3.6 V, TA = 25 °C, BGA225 package, compliant with IEC61967-2	30 to 130 MHz	30	dBµV
SEMI	Peak level(1)	VDD = 3.6 V, TA = 25 °C, BGA225 package, compliant with IEC61967-2	130 MHz to 1 GHz	22	dBµV
SEMI	Peak level(1)	VDD = 3.6 V, TA = 25 °C, BGA225 package, compliant with IEC61967-2	1 GHz to 2 GHz	9	dBµV
SEMI	Level(2)	VDD = 3.6 V, TA = 25 °C, BGA225 package, compliant with IEC61967-2	0.1 MHz to 2 GHz	4.0	-

Table 49 (pages 201–201)

Table 49 · 10 columns × 5 rows · p.201–201 · CSV

Symbol	Ratings		Conditions		Packages	Class	Maximum value(1)		Unit
VESD(HBM)	Electrostatic discharge voltage (human body model)	Electrostatic discharge voltage (human body model)	TA = +25 °C conforming to ANSI/ESDA/JEDEC JS-001	TA = +25 °C conforming to ANSI/ESDA/JEDEC JS-001	All packages	2	2000	2000	V
VESD(CDM)	Electrostatic discharge voltage (charge device model)	Electrostatic discharge voltage (charge device model)	TA = +25 °C conforming to ANSI/ESDA/JEDEC JS-002	TA = +25 °C conforming to ANSI/ESDA/JEDEC JS-002	All packages	C2B	500	500	V
1. Evaluated by characterization – not tested in production. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 68. Electrical sensitivities	1. Evaluated by characterization – not tested in production. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 68. Electrical sensitivities	1. Evaluated by characterization – not tested in production. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 68. Electrical sensitivities	1. Evaluated by characterization – not tested in production. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 68. Electrical sensitivities	1. Evaluated by characterization – not tested in production. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 68. Electrical sensitivities	1. Evaluated by characterization – not tested in production. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 68. Electrical sensitivities	1. Evaluated by characterization – not tested in production. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 68. Electrical sensitivities	1. Evaluated by characterization – not tested in production. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 68. Electrical sensitivities	1. Evaluated by characterization – not tested in production. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 68. Electrical sensitivities	1. Evaluated by characterization – not tested in production. Static latchup Two complementary static tests are required on six parts to assess the latchup performance: • A supply overvoltage is applied to each power supply pin • A current injection is applied to each input, output and configurable I/O pin These tests are compliant with JESD78 IC latchup standard. Table 68. Electrical sensitivities
Symbol	Symbol	Parameter	Parameter	Conditions	Conditions	Conditions	Conditions	Class	Class
LU	LU	Static latchup class	Static latchup class	Conforming to JESD78, TJ = TJMax	Conforming to JESD78, TJ = TJMax	Conforming to JESD78, TJ = TJMax	Conforming to JESD78, TJ = TJMax	II level A	II level A

Table 50 (pages 202–202)

Table 50 · 5 columns × 2 rows · p.202–202 · CSV

Symbol	Description	Functional susceptibility		Unit
Symbol	Description	Negative injection	Positive injection	Unit
IINJ	Injected current on pins: PB2, PC14, PC15, PF15, PM0, PM1, PM5 and PM6	0	0	mA
-	Injected current on all other pins	5	NA	mA

Table 51 (pages 203–203)

Table 51 · 7 columns × 16 rows · p.203–203 · CSV

Symbol	Parameter	Condition	Min	Typ	Max	Unit
VIL	I/O input low level voltage except BOOT0	1.08 V < VDD < 3.6 V	-	-	0.3 V DDIOx(2)	V
VIL	I/O input low level voltage except BOOT0	1.08 V < VDD < 3.6 V	-	-	0.4 VDDIOx -0.1(3)	V
VIL	BOOT0 I/O input low level voltage	1.08 V < VDD < 3.6 V	-	-	0.19 VDDIOx + 0.1(3)	V
VIH	I/O input high level voltage except BOOT0	1.08 V < VDD < 3.6 V	0.7 V DDIOx(2)	-	-	V
VIH	I/O input high level voltage except BOOT0	1.08 V < VDD < 3.6 V	0.52 VDDIOx +0.18(3)	-	-	V
VIH	BOOT0 I/O input high level voltage	1.08 V < VDD < 3.6 V	0.17 VDDIOx +0.6(3)	-	-	V
V HYS(3)	TT_xx, FT_xxx and NRSTI/O input hysteresis	1.08 V < VDD < 3.6 V	-	250	-	mV
V HYS(3)	BOOT0 I/O input hysteresis	1.71 V < VDD < 3.6 V	-	200	-	mV
I leak(4)	FT_xx Input leakage current(3)	0 < VIN ≤ Max(VDDXXX )(7)	-	-	±250	nA
I leak(4)	FT_xx Input leakage current(3)	Max(VDDXXX ) < VIN ≤ Max(VDDXXX )+1 V)(5)(7)	-	-	2500	nA
I leak(4)	FT_xx Input leakage current(3)	Max(VDDXXX ) < VIN ≤5.5 V(5)(7)	-	-	750	nA
I leak(4)	TT_xx Input leakage current	0< VIN ≤ Max(V(7) DDXXX )	-	-	±250	nA
I leak(4)	BOOT0	0< VIN ≤ VDDOX	-	-	15	µA
RPU	Weak pull-up equivalent resistor(6)	VIN = VSS	30	40	50	kΩ
RPD	Weak pull-down equivalent resistor(6)	VIN = V DD(7)	30	40	50	kΩ
CIO	I/O pin capacitance	-	-	5	-	pF

Table 52 (pages 205–205)

Table 52 · 6 columns × 14 rows · p.205–205 · CSV

Symbol	Parameter	Conditions(1)	Min	Max	Unit
VOL	Output low level voltage	CMOS port(2) IIO = 8 mA 2.7 V≤ VDD ≤ 3.6 V	-	0.4	V
VOH	Output high level voltage	CMOS port(2) IIO = -8 mA 2.7 V≤ VDD ≤ 3.6 V	VDD -0.4	-	V
V OL(3)	Output low level voltage	TTL port(2) IIO = 8 mA 2.7 V≤ VDD ≤ 3.6 V	-	0.4	V
VOH (3)	Output high level voltage	TTL port(2) IIO = -8 mA 2.7 V≤ VDD ≤ 3.6 V	2.4	-	V
V OL(3)	Output low level voltage	IIO = 20 mA 2.7 V ≤ VDD ≤ 3.6 V	-	1.3	V
V OH(3)	Output high level voltage	IIO = -20 mA 2.7 V ≤ VDD ≤ 3.6 V	VDD -1.3	-	V
V OL(3)	Output low level voltage	IIO = 4 mA 1.71 V ≤ VDD ≤ 3.6 V	-	0.4	V
VOH (3)	Output high level voltage	IIO = -4 mA 1.71 V ≤ VDD <3.6 V	VDD -0.4	-	V
V OL(3)	Output low level voltage	IIO = 2 mA 1.08 V ≤ VDD ≤ 1.32 V	-	0.3 VDDXSPIx	V
V OL(3)	Output low level voltage	IIO = 2 mA 1.08 V ≤ VDD ≤ 1.32 V	-	0.3	V
VOH (3)	Output high level voltage	IIO = -2 mA 1.71 V ≤ VDD < 1.32 V	0.7 VDDXSPIx	-	V
V OLFM+(3)	Output low level voltage for an FTf I/O pin in (FT I/O with “f” option)	IIO = 20 mA 2.3 V≤ VDD ≤3.6 V	-	0.4	V
V OLFM+(3)	Output low level voltage for an FTf I/O pin in (FT I/O with “f” option)	IIO = 10 mA 1.71 V ≤ VDD ≤ 3.6 V	-	0.4	V
V OLFM+(3)	Output low level voltage for an FTf I/O pin in (FT I/O with “f” option)	IIO = 4.5 mA 1.08 V ≤ VDD ≤ 3.6 V	-	0.4	V

Table 53 (pages 206–206)

Table 53 · 6 columns × 14 rows · p.206–206 · CSV

Symbol	Parameter	Conditions(3)	Min	Max	Unit
VOL	Output low level voltage	CMOS port(2) IIO = 3 mA 2.7 V≤ VDD ≤3.6 V	-	0.4	V
VOH	Output high level voltage	CMOS port(2) IIO = -3 mA 2.7 V≤ VDD ≤3.6 V	VDD -0.4	-	V
V OL(3)	Output low level voltage	TTL port(2) IIO = 3 mA 2.7 V≤ VDD ≤3.6 V	-	0.4	V
V OH(3)	Output high level voltage	TTL port(2) IIO = -3 mA 2.7 V≤ VDD ≤3.6 V	2.4	-	V
V OL(3)	Output low level voltage	IIO = 1.5 mA 1.71 V≤ VDD ≤ 3.6 V	-	0.4	V
V OH(3)	Output high level voltage	IIO = −1.5 mA 1.71 V≤ VDD ≤ 3.6 V	VDD -0.4	-	V
1. The the sum IIO current of the currents sourced sourced or sunk by or the sunk device by all must the I/Os always (I/O respect ports and the control absolute pins) maximum must always rating respect specified the in absolute Table 22, and maximum ratings ΣIIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Specified by design -Not tested in production. Table 73. Output voltage characteristics for PC14 and PC15(1)	1. The the sum IIO current of the currents sourced sourced or sunk by or the sunk device by all must the I/Os always (I/O respect ports and the control absolute pins) maximum must always rating respect specified the in absolute Table 22, and maximum ratings ΣIIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Specified by design -Not tested in production. Table 73. Output voltage characteristics for PC14 and PC15(1)	1. The the sum IIO current of the currents sourced sourced or sunk by or the sunk device by all must the I/Os always (I/O respect ports and the control absolute pins) maximum must always rating respect specified the in absolute Table 22, and maximum ratings ΣIIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Specified by design -Not tested in production. Table 73. Output voltage characteristics for PC14 and PC15(1)	1. The the sum IIO current of the currents sourced sourced or sunk by or the sunk device by all must the I/Os always (I/O respect ports and the control absolute pins) maximum must always rating respect specified the in absolute Table 22, and maximum ratings ΣIIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Specified by design -Not tested in production. Table 73. Output voltage characteristics for PC14 and PC15(1)	1. The the sum IIO current of the currents sourced sourced or sunk by or the sunk device by all must the I/Os always (I/O respect ports and the control absolute pins) maximum must always rating respect specified the in absolute Table 22, and maximum ratings ΣIIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Specified by design -Not tested in production. Table 73. Output voltage characteristics for PC14 and PC15(1)	1. The the sum IIO current of the currents sourced sourced or sunk by or the sunk device by all must the I/Os always (I/O respect ports and the control absolute pins) maximum must always rating respect specified the in absolute Table 22, and maximum ratings ΣIIO. 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. Specified by design -Not tested in production. Table 73. Output voltage characteristics for PC14 and PC15(1)
Symbol	Parameter	Conditions(3)	Min	Max	Unit
VOL	Output low level voltage	CMOS port(2) IIO = 0.5 mA 2.7 V ≤ VDD ≤ 3.6 V	-	0.4	V
VOH	Output high level voltage	CMOS port(2) IIO = -0.5 mA 2.7 V ≤ VDD ≤ 3.6 V	VDD -0.4	-	V
V OL(3)	Output low level voltage	TTL port(2) IIO = 0.5 mA 2.7 V ≤ VDD ≤ 3.6 V	-	0.4	V
V OH(3)	Output high level voltage	TTL port(2) IIO = -0.5 mA 2.7 V ≤ VDD ≤ 3.6 V	2.4	-	V
V OL(3)	Output low level voltage	IIO = 0.25 mA 1.71 V ≤ VDD ≤ 3.6 V	-	0.4	V
V OH(3)	Output high level voltage	IIO = -0.25 mA 1.71 V ≤ VDD ≤ 3.6 V	VDD -0.4	-	V

Table 54 (pages 207–211)

Table 54 · 7 columns × 110 rows · p.207–211 · CSV

Speed	Symbol	Parameter	Conditions	Min	Max	Unit
00	F max(2)(3)	Maximum frequency	C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	8	MHz
00	F max(2)(3)	Maximum frequency	C = 50 pF, 1.71 V ≤ VDD ≤ 2 V	-	5	MHz
00	F max(2)(3)	Maximum frequency	C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	10	MHz
00	F max(2)(3)	Maximum frequency	C = 40 pF, 1.71 V ≤ VDD ≤ 2 V	-	5	MHz
00	F max(2)(3)	Maximum frequency	C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	12	MHz
00	F max(2)(3)	Maximum frequency	C = 30 pF, 1.71 V ≤ VDD ≤ 2 V	-	5	MHz
00	F max(2)(3)	Maximum frequency	C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	14	MHz
00	F max(2)(3)	Maximum frequency	C = 20 pF, 1.71 V ≤ VDD ≤ 2 V	-	5	MHz
00	F max(2)(3)	Maximum frequency	C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	16	MHz
00	F max(2)(3)	Maximum frequency	C = 10 pF, 1.71 V ≤ VDD ≤ 2 V	-	5	MHz
00	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	18.0	ns
00	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.71 V ≤ VDD ≤ 2 V	-	36.0	ns
00	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	17.0	ns
00	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.71 V ≤ VDD ≤ 2 V	-	34.0	ns
00	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	15.5	ns
00	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.71 V ≤ VDD ≤ 2 V	-	32.0	ns
00	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	14.2	ns
00	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.71 V ≤ VDD ≤ 2 V	-	30.0	ns
00	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	12.2	ns
00	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.71 V ≤ VDD ≤ 2 V	-	27	ns
01	F max(2)(3)	Maximum frequency	C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V		40	MHz
01	F max(2)(3)	Maximum frequency	C = 50 pF, 1.71 V ≤ VDD ≤ 2 V	-	12	MHz
01	F max(2)(3)	Maximum frequency	C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	45	MHz
01	F max(2)(3)	Maximum frequency	C = 40 pF, 1.71 V ≤ VDD ≤ 2 V	-	14	MHz
01	F max(2)(3)	Maximum frequency	C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	50	MHz
01	F max(2)(3)	Maximum frequency	C = 30 pF, 1.71 V ≤ VDD ≤ 2 V	-	16	MHz
01	F max(2)(3)	Maximum frequency	C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	55	MHz
01	F max(2)(3)	Maximum frequency	C = 20 pF, 1.71 V ≤ VDD ≤ 2 V	-	18	MHz
01	F max(2)(3)	Maximum frequency	C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	60	MHz
01	F max(2)(3)	Maximum frequency	C = 10 pF, 1.71 V ≤ VDD ≤ 2 V	-	20	MHz
01	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	6.2	ns
01	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.71 V ≤ VDD ≤ 2 V	-	11.4	ns
01	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	5.7	ns
01	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.71 V ≤ VDD ≤ 2 V	-	10.5	ns
01	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	5.1	ns
01	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.71 V ≤ VDD ≤ 2 V	-	9.5	ns
01	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	4.5	ns
01	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.71 V ≤ VDD ≤ 2 V		8.4	ns
01	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V		3.7	ns
01	tr /t f(4)(5)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.71 V ≤ VDD ≤ 2 V		7.0	ns
10	F max(2)(3)(6)	Maximum frequency	C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	80	MHz
10	F max(2)(3)(6)	Maximum frequency	C = 50 pF, 1.71 V ≤ VDD ≤ 2 V	-	30	MHz
10	F max(2)(3)(6)	Maximum frequency	C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	90	MHz
10	F max(2)(3)(6)	Maximum frequency	C = 40 pF, 1.71 V ≤ VDD ≤ 2 V	-	35	MHz
10	F max(2)(3)(6)	Maximum frequency	C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	100	MHz
10	F max(2)(3)(6)	Maximum frequency	C = 30 pF, 1.71 V ≤ VDD ≤ 2 V	-	40	MHz
10	F max(2)(3)(6)	Maximum frequency	C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	110	MHz
10	F max(2)(3)(6)	Maximum frequency	C = 20 pF, 1.71 V ≤ VDD ≤ 2 V	-	45	MHz
10	F max(2)(3)(6)	Maximum frequency	C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	133	MHz
10	F max(2)(3)(6)	Maximum frequency	C = 10 pF, 1.71 V ≤ VDD ≤ 2 V	-	50	MHz
10	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	3.8	ns
10	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.71 V ≤ VDD ≤ 2 V	-	7.5	ns
10	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	3.4	ns
10	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.71 V ≤ VDD ≤ 2 V	-	6.6	ns
10	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	2.9	ns
10	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.71 V ≤ VDD ≤ 2 V	-	5.7	ns
10	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	2.5	ns
10	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.71 V ≤ VDD ≤ 2 V	-	4.7	ns
10	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	1.9	ns
10	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.71 V ≤ VDD ≤ 2 V	-	3.7	ns
11	F max(2)(3)(6)	Maximum frequency	C = 50 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	100	MHz
11	F max(2)(3)(6)	Maximum frequency	C = 50 pF, 1.71 V ≤ VDD ≤ 2 V	-	40	MHz
11	F max(2)(3)(6)	Maximum frequency	C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	120	MHz
11	F max(2)(3)(6)	Maximum frequency	C = 40 pF, 1.71 V ≤ VDD ≤ 2 V	-	50	MHz
11	F max(2)(3)(6)	Maximum frequency	C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	140	MHz
11	F max(2)(3)(6)	Maximum frequency	C = 30 pF, 1.71 V ≤ VDD ≤ 2 V	-	60	MHz
11	F max(2)(3)(6)	Maximum frequency	C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	166	MHz
11	F max(2)(3)(6)	Maximum frequency	C = 20 pF, 1.71 V ≤ VDD ≤ 2 V	-	70	MHz
11	F max(2)(3)(6)	Maximum frequency	C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	200	MHz
11	F max(2)(3)(6)	Maximum frequency	C = 10 pF, 1.71 V ≤ VDD ≤ 2 V	-	80	MHz
11	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 2.7 V≤ VDD ≤ 3.6 V	-	3.3	ns
11	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.71 V ≤ VDD ≤ 2 V	-	6.3	ns
11	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	2.8	ns
11	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.71 V ≤ VDD ≤ 2 V	-	5.5	ns
11	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	2.3	ns
11	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.71 V ≤ VDD ≤ 2 V	-	4.6	ns
11	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	1.9	ns
11	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.71 V ≤ VDD ≤ 2 V	-	3.7	ns
11	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 2.7 V ≤ VDD ≤ 3.6 V	-	1.4	ns
11	tr /t f(4)(5)(6)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.71 V ≤ VDD ≤ 2 V	-	3	ns
00	F max(2)	Maximum frequency	C = 50 pF, 1.71 V ≤ VDD ≤2 V	-	8	MHz
00	F max(2)	Maximum frequency	C = 40 pF, 1.71 V ≤ VDD ≤2 V	-	10	MHz
00	F max(2)	Maximum frequency	C = 30 pF, 1.71 V ≤ VDD ≤2 V	-	12	MHz
00	F max(2)	Maximum frequency	C = 20 pF, 1.71 V ≤ VDD ≤2 V	-	14	MHz
00	F max(2)	Maximum frequency	C = 10 pF, 1.71 V ≤ VDD ≤2 V	-	16	MHz
00	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.71 V ≤ VDD ≤2 V	-	17.8	ns
00	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.71 V ≤ VDD ≤2 V	-	15.8	ns
00	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.71 V ≤ VDD ≤2 V	-	14.4	ns
00	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.71 V ≤ VDD ≤2 V	-	13.1	ns
00	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.71 V ≤ VDD ≤2 V	-	11.4	ns
01	F max(2)	Maximum frequency	C = 50 pF, 1.71 V ≤ VDD ≤2 V	-	40	MHz
01	F max(2)	Maximum frequency	C = 40 pF, 1.71 V ≤ VDD ≤2 V	-	45	MHz
01	F max(2)	Maximum frequency	C = 30 pF, 1.71 V ≤ VDD ≤2 V	-	50	MHz
01	F max(2)	Maximum frequency	C = 20 pF, 1.71 V ≤ VDD ≤2 V	-	55	MHz
01	F max(2)	Maximum frequency	C = 10 pF, 1.71 V ≤ VDD ≤2 V	-	60	MHz
01	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.71 V ≤ VDD ≤2 V	-	7.2	ns
01	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.71 V ≤ VDD ≤2 V	-	6.5	ns
01	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.71 V ≤ VDD ≤2 V	-	5.6	ns
01	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.71 V ≤ VDD ≤2 V	-	4.8	ns
01	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.71 V ≤ VDD ≤2 V	-	3.8	ns
10	Fmax (2)(4)	Maximum frequency	C = 50 pF, 1.71 V ≤ VDD ≤2 V	-	60	MHz
10	Fmax (2)(4)	Maximum frequency	C = 40 pF, 1.71 V ≤ VDD ≤2 V	-	70	MHz
10	Fmax (2)(4)	Maximum frequency	C = 30 pF, 1.71 V ≤ VDD ≤2 V	-	90	MHz
10	Fmax (2)(4)	Maximum frequency	C = 20 pF, 1.71 V ≤ VDD ≤2 V	-	110	MHz
10	Fmax (2)(4)	Maximum frequency	C = 10 pF, 1.71 V ≤ VDD ≤2 V	-	140	MHz
10	tr /tf (3)(4)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.71 V ≤ VDD ≤2 V	-	5.3	ns
10	tr /tf (3)(4)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.71 V ≤ VDD ≤2 V	-	4.6	ns
10	tr /tf (3)(4)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.71 V ≤ VDD ≤2 V	-	3.8	ns
10	tr /tf (3)(4)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.71 V ≤ VDD ≤2 V	-	3.0	ns
10	tr /tf (3)(4)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.71 V ≤ VDD ≤2 V	-	2.2	ns

Table 55 (pages 212–212)

Table 56 · 7 columns × 70 rows · p.213–215 · CSV

Speed	Symbol	Parameter	conditions	Min	Max	Unit
01	F max(2)	Maximum frequency	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	5	MHz
01	F max(2)	Maximum frequency	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	5	MHz
01	F max(2)	Maximum frequency	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	5	MHz
01	F max(2)	Maximum frequency	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	5	MHz
01	F max(2)	Maximum frequency	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	5	MHz
01	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	24.5	ns
01	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	22.2	ns
01	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	20.0	ns
01	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	17.8	ns
01	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	15.0	ns
10	F max(2)	Maximum frequency	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	10	MHz
10	F max(2)	Maximum frequency	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	10	MHz
10	F max(2)	Maximum frequency	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	10	MHz
10	F max(2)	Maximum frequency	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	10	MHz
10	F max(2)	Maximum frequency	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	10	MHz
10	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	16.2	ns
10	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	14.3	ns
10	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	12.2	ns
10	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	10.0	ns
10	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	7.9	ns
11	F max(2)(4)	Maximum frequency	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	20	MHz
11	F max(2)(4)	Maximum frequency	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	23	MHz
11	F max(2)(4)	Maximum frequency	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	25	MHz
11	F max(2)(4)	Maximum frequency	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	28	MHz
11	F max(2)(4)	Maximum frequency	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	30	MHz
11	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	14.0	ns
11	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	12.0	ns
11	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	10.0	ns
11	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	8.0	ns
11	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	6.0	ns
00	Fmax (2)	Maximum frequency	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	5	MHz
00	Fmax (2)	Maximum frequency	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	5	MHz
00	Fmax (2)	Maximum frequency	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	5	MHz
00	Fmax (2)	Maximum frequency	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	5	MHz
00	Fmax (2)	Maximum frequency	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	5	MHz
00	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	32.5	ns
00	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	30.0	ns
00	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	27.5	ns
00	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	25.0	ns
00	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	22.5	ns
01	Fmax (2)	Maximum frequency	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	15.0	MHz
01	Fmax (2)	Maximum frequency	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	17.5	MHz
01	Fmax (2)	Maximum frequency	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	20.0	MHz
01	Fmax (2)	Maximum frequency	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	22.5	MHz
01	Fmax (2)	Maximum frequency	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	25.0	MHz
01	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	14.6	ns
01	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	12.9	ns
01	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	11.2	ns
01	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	9.3	ns
01	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	7.3	ns
10	Fmax (2)(4)	Maximum frequency	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	25	MHz
10	Fmax (2)(4)	Maximum frequency	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	30	MHz
10	Fmax (2)(4)	Maximum frequency	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	33	MHz
10	Fmax (2)(4)	Maximum frequency	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	44	MHz
10	Fmax (2)(4)	Maximum frequency	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	55	MHz
10	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	11.6	ns
10	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	9.7	ns
10	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	7.8	ns
10	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	6.1	ns
10	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	4.3	ns
11	Fmax (2)(4)	Maximum frequency	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	30	MHz
11	Fmax (2)(4)	Maximum frequency	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	35	MHz
11	Fmax (2)(4)	Maximum frequency	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	44	MHz
11	Fmax (2)(4)	Maximum frequency	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	55	MHz
11	Fmax (2)(4)	Maximum frequency	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	77	MHz
11	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	11.1	ns
11	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	9.2	ns
11	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	7.2	ns
11	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	5.4	ns
11	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	3.6	ns

Table 56 (pages 213–215)

Table 55 · 9 columns × 22 rows · p.212–212 · CSV

Speed	Symbol	Parameter		Conditions	Min		Max	Unit
11	Fmax (2)(4)	Maximum frequency	Maximum frequency	C = 50 pF, 1.71 V ≤ VDD ≤2 V	-	-	67	MHz
11	Fmax (2)(4)	Maximum frequency	Maximum frequency	C = 40 pF, 1.71 V ≤ VDD ≤2 V	-	-	100	MHz
11	Fmax (2)(4)	Maximum frequency	Maximum frequency	C = 30 pF, 1.71 V ≤ VDD ≤2 V	-	-	120	MHz
11	Fmax (2)(4)	Maximum frequency	Maximum frequency	C = 20 pF, 1.71 V ≤ VDD ≤2 V	-	-	155	MHz
11	Fmax (2)(4)	Maximum frequency	Maximum frequency	C = 10 pF, 1.71 V ≤ VDD ≤2 V	-	-	200	MHz
11	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.71 V ≤ VDD ≤2 V	-	-	5.0	ns
11	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.71 V ≤ VDD ≤2 V	-	-	4.1	ns
11	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.71 V ≤ VDD ≤2 V	-	-	3.3	ns
11	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.71 V ≤ VDD ≤2 V	-	-	2.5	ns
11	tr /t f(3)(4)	Output high to low level fall time and output low to high level rise time	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.71 V ≤ VDD ≤2 V	-	-	1.8	ns
1. Specified by design -Not tested in production. 2. The maximum frequency is defined with the following conditions: (t Skewr +tf ) ≤ ≤ 2/3 1/20 T T 45% < Duty cycle < 55% 3. The fall and rise times are defined, respectively, between 90 and 10% and between 10 and 90% of the output waveform. 4. Compensation system enabled. Table 76. Output timing characteristics VDDXSPIx 1.2 V range (HSLV OFF)(1)	1. Specified by design -Not tested in production. 2. The maximum frequency is defined with the following conditions: (t Skewr +tf ) ≤ ≤ 2/3 1/20 T T 45% < Duty cycle < 55% 3. The fall and rise times are defined, respectively, between 90 and 10% and between 10 and 90% of the output waveform. 4. Compensation system enabled. Table 76. Output timing characteristics VDDXSPIx 1.2 V range (HSLV OFF)(1)	1. Specified by design -Not tested in production. 2. The maximum frequency is defined with the following conditions: (t Skewr +tf ) ≤ ≤ 2/3 1/20 T T 45% < Duty cycle < 55% 3. The fall and rise times are defined, respectively, between 90 and 10% and between 10 and 90% of the output waveform. 4. Compensation system enabled. Table 76. Output timing characteristics VDDXSPIx 1.2 V range (HSLV OFF)(1)	1. Specified by design -Not tested in production. 2. The maximum frequency is defined with the following conditions: (t Skewr +tf ) ≤ ≤ 2/3 1/20 T T 45% < Duty cycle < 55% 3. The fall and rise times are defined, respectively, between 90 and 10% and between 10 and 90% of the output waveform. 4. Compensation system enabled. Table 76. Output timing characteristics VDDXSPIx 1.2 V range (HSLV OFF)(1)	1. Specified by design -Not tested in production. 2. The maximum frequency is defined with the following conditions: (t Skewr +tf ) ≤ ≤ 2/3 1/20 T T 45% < Duty cycle < 55% 3. The fall and rise times are defined, respectively, between 90 and 10% and between 10 and 90% of the output waveform. 4. Compensation system enabled. Table 76. Output timing characteristics VDDXSPIx 1.2 V range (HSLV OFF)(1)	1. Specified by design -Not tested in production. 2. The maximum frequency is defined with the following conditions: (t Skewr +tf ) ≤ ≤ 2/3 1/20 T T 45% < Duty cycle < 55% 3. The fall and rise times are defined, respectively, between 90 and 10% and between 10 and 90% of the output waveform. 4. Compensation system enabled. Table 76. Output timing characteristics VDDXSPIx 1.2 V range (HSLV OFF)(1)	1. Specified by design -Not tested in production. 2. The maximum frequency is defined with the following conditions: (t Skewr +tf ) ≤ ≤ 2/3 1/20 T T 45% < Duty cycle < 55% 3. The fall and rise times are defined, respectively, between 90 and 10% and between 10 and 90% of the output waveform. 4. Compensation system enabled. Table 76. Output timing characteristics VDDXSPIx 1.2 V range (HSLV OFF)(1)	1. Specified by design -Not tested in production. 2. The maximum frequency is defined with the following conditions: (t Skewr +tf ) ≤ ≤ 2/3 1/20 T T 45% < Duty cycle < 55% 3. The fall and rise times are defined, respectively, between 90 and 10% and between 10 and 90% of the output waveform. 4. Compensation system enabled. Table 76. Output timing characteristics VDDXSPIx 1.2 V range (HSLV OFF)(1)	1. Specified by design -Not tested in production. 2. The maximum frequency is defined with the following conditions: (t Skewr +tf ) ≤ ≤ 2/3 1/20 T T 45% < Duty cycle < 55% 3. The fall and rise times are defined, respectively, between 90 and 10% and between 10 and 90% of the output waveform. 4. Compensation system enabled. Table 76. Output timing characteristics VDDXSPIx 1.2 V range (HSLV OFF)(1)
Speed	Symbol	Parameter	conditions	conditions	conditions	Min	Max	Unit
00	F max(2)	Maximum frequency	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	1	MHz
00	F max(2)	Maximum frequency	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	1	MHz
00	F max(2)	Maximum frequency	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	1	MHz
00	F max(2)	Maximum frequency	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	1	MHz
00	F max(2)	Maximum frequency	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	1	MHz
00	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 50 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	83.0	ns
00	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 40 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	79.0	ns
00	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 30 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	46.0	ns
00	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 20 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	72.0	ns
00	tr /t f(3)	Output high to low level fall time and output low to high level rise time	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	C = 10 pF, 1.08 V ≤ VDDXSPIx ≤1.32 V	-	68.0	ns

Table 57 (pages 217–217)

Table 60 · 6 columns × 16 rows · p.223–223 · CSV

Symbol	Parameter		Min	Max	Unit
tw(NE)	FMC_NE low time		4Tfmc_ker_ck –1	4Tfmc_ker_ck +1	ns
tv(NWE_NE)	FMC_NEx low to FMC_NWE low		Tfmc_ker_ck –0.5	Tfmc_ker_ck +0.5	ns
tw(NWE)	FMC_NWE low time		2Tfmc_ker_ck –0.5	2Tfmc_ker_ck +0.5	ns
th(NE_NWE)	FMC_NWE high to FMC_NE high hold time	FMC_NWE high to FMC_NE high hold time	Tfmc_ker_ck +1	-	ns
tv(A_NE)	FMC_NEx low to FMC_A valid	FMC_NEx low to FMC_A valid	-	0.5	ns
tv(NADV_NE)	FMC_NEx low to FMC_NADV low	FMC_NEx low to FMC_NADV low	0	0.5	ns
tw(NADV)	FMC_NADV low time	FMC_NADV low time	Tfmc_ker_ck –0.5	Tfmc_ker_ck + 0.5	ns
th(AD_NADV)	FMC_AD(adress) valid hold time after FMC_NADV high)	FMC_AD(adress) valid hold time after FMC_NADV high)	Tfmc_ker_ck –1.5	-	ns
th(A_NWE)	Address hold time after FMC_NWE high	Address hold time after FMC_NWE high	Tfmc_ker_ck	-	ns
th(BL_NWE)	FMC_BL hold time after FMC_NWE high	FMC_BL hold time after FMC_NWE high	Tfmc_ker_c + 0.5	-	ns
tv(BL_NE)	FMC_NEx low to FMC_BL valid	FMC_NEx low to FMC_BL valid	-	1	ns
tv(Data_NADV)	FMC_NADV high to Data valid	FMC_NADV high to Data valid	-	Tfmc_ker_ck +0.5	ns
th(Data_NWE)	Data hold time after FMC_NWE high	Data hold time after FMC_NWE high	Tfmc_ker_ck + 2	-	ns
1. Guaranteed by characterization results. Table 86. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)	1. Guaranteed by characterization results. Table 86. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)	1. Guaranteed by characterization results. Table 86. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)	1. Guaranteed by characterization results. Table 86. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)	1. Guaranteed by characterization results. Table 86. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)	1. Guaranteed by characterization results. Table 86. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1)(2)
Symbol	Parameter	Min	Min	Max	Unit
tw(NE)	FMC_NE low time	9Tfmc_ker_ck –1	9Tfmc_ker_ck –1	9Tfmc_ker_ck + 1	ns
tw(NWE)	FMC_NWE low time	7Tfmc_ker_ck –1	7Tfmc_ker_ck –1	7Tfmc_ker_ck +1	ns
tsu(NWAIT_NE)	FMC_NWAIT valid before FMC_NEx high	5Tfmc_ker_ck +13	5Tfmc_ker_ck +13	-	ns
th(NE_NWAIT)	FMC_NEx hold time after FMC_NWAIT invalid	4Tfmc_ker_ck +13	4Tfmc_ker_ck +13	-	ns

Table 58 (pages 219–219)

Table 58 · 8 columns × 15 rows · p.219–219 · CSV

Symbol	Parameter		Min		Max		Unit
tw(NE)	FMC_NE low time		3Tfmc_ker_ck –1		3Tfmc_ker_ck + 1		ns
tv(NWE_NE)	FMC_NEx low to FMC_NWE low		Tfmc_ker_ck –1		Tfmc_ker_ck +0.5		ns
tw(NWE)	FMC_NWE low time		Tfmc_ker_ck –0.5		Tfmc_ker_ck +0.5		ns
th(NE_NWE)	FMC_NWE high to FMC_NE high hold time	FMC_NWE high to FMC_NE high hold time	Tfmc_ker_ck +1	Tfmc_ker_ck +1	-	-	ns
tv(A_NE)	FMC_NEx low to FMC_A valid	FMC_NEx low to FMC_A valid	-	-	0.5	0.5	ns
th(A_NWE)	Address hold time after FMC_NWE high	Address hold time after FMC_NWE high	Tfmc_ker_ck	Tfmc_ker_ck	-	-	ns
tv(BL_NE)	FMC_NEx low to FMC_BL valid	FMC_NEx low to FMC_BL valid	-	-	1	1	ns
th(BL_NWE)	FMC_BL hold time after FMC_NWE high	FMC_BL hold time after FMC_NWE high	Tfmc_ker_ck +0.5	Tfmc_ker_ck +0.5	-	-	ns
tv(Data_NE)	Data to FMC_NEx low to Data valid	Data to FMC_NEx low to Data valid	-	-	Tfmc_ker_ck + 0.5	Tfmc_ker_ck + 0.5	ns
th(Data_NWE)	Data hold time after FMC_NWE high	Data hold time after FMC_NWE high	Tfmc_ker_ck + 2	Tfmc_ker_ck + 2	-	-	ns
tv(NADV_NE)	FMC_NEx low to FMC_NADV low	FMC_NEx low to FMC_NADV low	-	-	0.5	0.5	ns
tw(NADV)	FMC_NADV low time	FMC_NADV low time	-	-	Tfmc_ker_ck + 0.5	Tfmc_ker_ck + 0.5	ns
1. Guaranteed by characterization results. Table 82. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)(2)	1. Guaranteed by characterization results. Table 82. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)(2)	1. Guaranteed by characterization results. Table 82. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)(2)	1. Guaranteed by characterization results. Table 82. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)(2)	1. Guaranteed by characterization results. Table 82. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)(2)	1. Guaranteed by characterization results. Table 82. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)(2)	1. Guaranteed by characterization results. Table 82. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)(2)	1. Guaranteed by characterization results. Table 82. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1)(2)
Symbol	Symbol	Parameter	Parameter	Min	Min	Max	Unit
tw(NE)	tw(NE)	FMC_NE low time	FMC_NE low time	8Tfmc_ker_ck –1	8Tfmc_ker_ck –1	8Tfmc_ker_ck +1	ns
tw(NWE)	tw(NWE)	FMC_NWE low time	FMC_NWE low time	6Tfmc_ker_ck –1	6Tfmc_ker_ck –1	6Tfmc_ker_ck +1	ns
tsu(NWAIT_NE)	tsu(NWAIT_NE)	FMC_NWAIT valid before FMC_NEx high	FMC_NWAIT valid before FMC_NEx high	5Tfmc_ker_ck +13	5Tfmc_ker_ck +13	-	ns
th(NE_NWAIT)	th(NE_NWAIT)	FMC_NEx hold time after FMC_NWAIT invalid	FMC_NEx hold time after FMC_NWAIT invalid	4Tfmc_ker_ck +13	4Tfmc_ker_ck +13	-	ns

Table 59 (pages 221–221)

Table 57 · 5 columns × 11 rows · p.217–217 · CSV

Symbol	Parameter	Min	Max	Unit
tw(NE)	FMC_NE low time	3Tfmc_ker_ck –1	3Tfmc_ker_ck +1	ns
tv(NOE_NE)	FMC_NEx low to FMC_NOE low	0	1	ns
tw(NOE)	FMC_NOE low time	2Tfmc_ker_ck –1	2Tfmc_ker_ck +1	ns
th(NE_NOE)	FMC_NOE high to FMC_NE high hold time	Tfmc_ker_ck	-	ns
tv(A_NE)	FMC_NEx low to FMC_A valid	-	1	ns
th(A_NOE)	Address hold time after FMC_NOE high	2Tfmc_ker_ck -1	-	ns
tsu(Data_NE)	Data to FMC_NEx high setup time	Tfmc_ker_ck +12.5	-	ns
tsu(Data_NOE)	Data to FMC_NOEx high setup time	12.5	-	ns
th(Data_NOE)	Data hold time after FMC_NOE high	0	-	ns
th(Data_NE)	Data hold time after FMC_NEx high	0	-	ns
tv(NADV_NE)	FMC_NEx low to FMC_NADV low	-	1	ns
tw(NADV)	FMC_NADV low time	-	Tfmc_ker_ck +1	ns

| th(NE_NWAIT) | th(NE_NWAIT) | FMC_NEx hold time after FMC_NWAIT invalid | 4Tfmc_ker_ck +13 | 4Tfmc_ker_ck +13 | - | - | - | ns |

Table 60 (pages 223–223)

Table 59 · 9 columns × 16 rows · p.221–221 · CSV

Symbol	Parameter			Min		Max	Unit
tw(NE)	FMC_NE low time			4Tfmc_ker_ck –1		4Tfmc_ker_ck +1	ns
tv(NOE_NE)	FMC_NEx low to FMC_NOE low			2Tfmc_ker_ck –1		2Tfmc_ker_ck +1	ns
ttw(NOE)	FMC_NOE low time			Tfmc_ker_ck –1		Tfmc_ker_ck +1	ns
th(NE_NOE)	FMC_NOE high to FMC_NE high hold time	FMC_NOE high to FMC_NE high hold time	FMC_NOE high to FMC_NE high hold time	Tfmc_ker_ck	Tfmc_ker_ck	-	ns	ns
tv(A_NE)	FMC_NEx low to FMC_A valid	FMC_NEx low to FMC_A valid	FMC_NEx low to FMC_A valid	-	-	1	ns	ns
tv(NADV_NE)	FMC_NEx low to FMC_NADV low	FMC_NEx low to FMC_NADV low	FMC_NEx low to FMC_NADV low	0	0	1	ns	ns
tw(NADV)	FMC_NADV low time	FMC_NADV low time	FMC_NADV low time	Tfmc_ker_ck –1	Tfmc_ker_ck –1	Tfmc_ker_ck +1	ns	ns
th(AD_NADV)	FMC_AD(address) valid hold time after FMC_NADV high)	FMC_AD(address) valid hold time after FMC_NADV high)	FMC_AD(address) valid hold time after FMC_NADV high)	Tfmc_ker_ckk –3	Tfmc_ker_ckk –3	-	ns	ns
th(A_NOE)	Address hold time after FMC_NOE high	Address hold time after FMC_NOE high	Address hold time after FMC_NOE high	2Tfmc_ker_ck –1	2Tfmc_ker_ck –1	-	ns	ns
tsu(Data_NE)	Data to FMC_NEx high setup time	Data to FMC_NEx high setup time	Data to FMC_NEx high setup time	Tfmc_ker_ck +12	Tfmc_ker_ck +12	-	ns	ns
tsu(Data_NOE)	Data to FMC_NOE high setup time	Data to FMC_NOE high setup time	Data to FMC_NOE high setup time	12	12	-	ns	ns
th(Data_NE)	Data hold time after FMC_NEx high	Data hold time after FMC_NEx high	Data hold time after FMC_NEx high	0	0	-	ns	ns
th(Data_NOE)	Data hold time after FMC_NOE high	Data hold time after FMC_NOE high	Data hold time after FMC_NOE high	0	0	-	ns	ns
1. Guaranteed by characterization results. Table 84. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)	1. Guaranteed by characterization results. Table 84. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)	1. Guaranteed by characterization results. Table 84. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)	1. Guaranteed by characterization results. Table 84. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)	1. Guaranteed by characterization results. Table 84. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)	1. Guaranteed by characterization results. Table 84. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)	1. Guaranteed by characterization results. Table 84. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)	1. Guaranteed by characterization results. Table 84. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)	1. Guaranteed by characterization results. Table 84. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1)
Symbol	Symbol	Parameter	Min	Min	Max	Max	Max	Unit
tw(NE)	tw(NE)	FMC_NE low time	9Tfmc_ker_ck –1	9Tfmc_ker_ck –1	9Tfmc_ker_ck +1	9Tfmc_ker_ck +1	9Tfmc_ker_ck +1	ns
tw(NOE)	tw(NOE)	FMC_NWE low time	6Tfmc_ker_ck –1	6Tfmc_ker_ck –1	6Tfmc_ker_ck +1	6Tfmc_ker_ck +1	6Tfmc_ker_ck +1	ns
tsu(NWAIT_NE)	tsu(NWAIT_NE)	FMC_NWAIT valid before FMC_NEx high	5Tfmc_ker_ck +13	5Tfmc_ker_ck +13	-	-	-	ns
th(NE_NWAIT)	th(NE_NWAIT)	FMC_NEx hold time after FMC_NWAIT invalid	4Tfmc_ker_ck +13	4Tfmc_ker_ck +13	-	-	-	ns

Table 61 (pages 224–224)

Table 63 · 5 columns × 16 rows · p.230–230 · CSV

Symbol	Parameter	Min	Max(2)	Unit
tw(CLK)	FMC_CLK period, VDD = 2.7 to 3.6 V	2Tfmc_ker_ck –0.5	-	ns
td(CLKL-NExL)	FMC_CLK low to FMC_NEx low (x =0..2)	-	2	ns
td(CLKH-NExH)	FMC_CLK high to FMC_NEx high (x = 0…2)	Tfmc_ker_ck +1	-	ns
td(CLKL-NADVL)	FMC_CLK low to FMC_NADV low	-	2	ns
td(CLKL-NADVH)	FMC_CLK low to FMC_NADV high	1	-	ns
td(CLKL-AV)	FMC_CLK low to FMC_Ax valid (x =16…25)	-	2	ns
td(CLKH-AIV)	FMC_CLK high to FMC_Ax invalid (x =16…25)	Tfmc_ker_ck	-	ns
td(CLKL-NWEL)	FMC_CLK low to FMC_NWE low	-	1	ns
t(CLKH-NWEH)	FMC_CLK high to FMC_NWE high	Tfmc_ker_ck	-	ns
td(CLKL-ADV)	FMC_CLK low to to FMC_AD[15:0] valid	-	2	ns
td(CLKL-ADIV)	FMC_CLK low to FMC_AD[15:0] invalid	0	-	ns
td(CLKL-DATA)	FMC_A/D[15:0] valid data after FMC_CLK low	-	2	ns
td(CLKL-NBLL)	FMC_CLK low to FMC_NBL low	-	2	ns
td(CLKH-NBLH)	FMC_CLK high to FMC_NBL high	Tfmc_ker_ck +0.5	-	ns
tsu(NWAIT-CLKH)	FMC_NWAIT valid before FMC_CLK high	2	-	ns
th(CLKH-NWAIT)	FMC_NWAIT valid after FMC_CLK high	2	-	ns

Table 62 (pages 226–228)

Table 61 · 5 columns × 13 rows · p.224–224 · CSV

Symbol	Parameter	Min	Max(2)	Unit
tw(CLK)	FMC_CLK period	2Tfmc_ker_ck –0.5	-	ns
t(CLKL-NExL)	FMC_CLK low to FMC_NEx low (x=0..2)	-	2	ns
td(CLKH-NExH)	FMC_CLK high to FMC_NEx high (x= 0…2)	Tfmc_ker_ck +1	-	ns
td(CLKL-NADVL)	FMC_CLK low to FMC_NADV low	-	2	ns
td(CLKL-NADVH)	FMC_CLK low to FMC_NADV high	1	-	ns
td(CLKL-AV)	FMC_CLK low to FMC_Ax valid (x=16…25)	-	2	ns
td(CLKH-AIV)	FMC_CLK high to FMC_Ax invalid (x=16…25)	Tfmc_ker_ck	-	ns
td(CLKL-NOEL)	FMC_CLK ow to FMC_NOE low	-	2	ns
td(CLKH-NOEH)	FMC_CLK high to FMC_NOE high	Tfmc_ker_ck	-	ns
tsu(DV-CLKH)	FMC_D[15:0] valid data before FMC_CLK high	2.5	-	ns
th(CLKH-DV)	FMC_D[15:0] valid data after FMC_CLK high	1.5	-	ns
t(NWAIT-CLKH)	FMC_NWAIT valid before FMC_CLK high	2.5	-	ns
th(CLKH-NWAIT)	FMC_NWAIT valid after FMC_CLK high	1	-	ns

Table 63 (pages 230–230)

Symbol	Parameter	Min	Max(2)	Unit
tw(CLK)	FMC_CLK period, VDD = 2.7 to 3.6 V	2Tfmc_ker_ck –0.5	-	ns

Table 62 · 5 columns × 29 rows · p.226–228 · CSV

Symbol	Parameter	Min	Max(2)	Unit
t(CLK)	FMC_CLK period	2Tfmc_ker_ck –0.5	-	ns
td(CLKL-NExL)	FMC_CLK low to FMC_NEx low (x=0..2)	-	2	ns
t(CLKH-NExH)	FMC_CLK high to FMC_NEx high (x= 0…2)	Tfmc_ker_ck +1	-	ns
td(CLKL-NADVL)	FMC_CLK low to FMC_NADV low	-	2	ns
td(CLKL-NADVH)	FMC_CLK low to FMC_NADV high	1	-	ns
td(CLKL-AV)	FMC_CLK low to FMC_Ax valid (x=16…25)	-	2	ns
td(CLKH-AIV)	FMC_CLK high to FMC_Ax invalid (x=16…25)	Tfmc_ker_ck	-	ns
td(CLKL-NWEL)	FMC_CLK low to FMC_NWE low	-	1	ns
td(CLKH-NWEH)	FMC_CLK high to FMC_NWE high	Tfmc_ker_ck	-	ns
td(CLKL-Data)	FMC_D[15:0] valid data after FMC_CLK low	-	2	ns
td(CLKL-NBLL)	FMC_CLK low to FMC_NBL low	-	2	ns
td(CLKH-NBLH)	FMC_CLK high to FMC_NBL high	Tfmc_ker_ck +0.5	-	ns
tsu(NWAIT-CLKH)	FMC_NWAIT valid before FMC_CLK high	2.5	-	ns
th(CLKH-NWAIT)	FMC_NWAIT valid after FMC_CLK high	1	-	ns
tw(CLK)	FMC_CLK period	2Tfmc_ker_ck –0.5	-	ns
td(CLKL-NExL)	FMC_CLK low to FMC_NEx low (x=0..2)	-	2	ns
td(CLKH_NExH)	FMC_CLK high to FMC_NEx high (x= 0…2)	Tfmc_ker_ck +1	-	ns
td(CLKL-NADVL)	FMC_CLK low to FMC_NADV low	-	2	ns
td(CLKL-NADVH)	FMC_CLK low to FMC_NADV high	1	-	ns
td(CLKL-AV)	FMC_CLK low to FMC_Ax valid (x=16…25)	-	2	ns
td(CLKH-AIV)	FMC_CLK high to FMC_Ax invalid (x=16…25)	Tfmc_ker_ck	-	ns
td(CLKL-NOEL)	FMC_CLK low to FMC_NOE low	-	2	ns
td(CLKH-NOEH)	FMC_CLK high to FMC_NOE high	Tfmc_ker_ck	-	ns
td(CLKL-ADV)	FMC_CLK low to FMC_AD[15:0] valid	-	2.5	ns
td(CLKL-ADIV)	FMC_CLK low to FMC_AD[15:0] invalid	0	-	ns
tsu(ADV-CLKH)	FMC_A/D[15:0] valid data before FMC_CLK high	2.5	-	ns
th(CLKH-ADV)	FMC_A/D[15:0] valid data after FMC_CLK high	1.5	-	ns
tsu(NWAIT-CLKH)	FMC_NWAIT valid before FMC_CLK high	2.5	-	ns
th(CLKH-NWAIT)	FMC_NWAIT valid after FMC_CLK high	1	-	ns

Table 64 (pages 232–232)

Table 64 · 5 columns × 4 rows · p.232–232 · CSV

Symbol	Parameter	Min	Max	Unit
tw(N0E)	FMC_NOE low width	4Tfmc_ker_ck – 0.5	4Tfmc_ker_ck +0.5	ns
tsu(D-NOE)	FMC_D[15-0] valid data before FMC_NOE high	12.5	-	ns
th(NOE-D)	FMC_D[15-0] valid data after FMC_NOE high	0	-	ns
td(ALE-NOE)	FMC_ALE valid before FMC_NOE low	-	3Tfmc_ker_ck +0.5	ns
th(NOE-ALE)	FMC_NWE high to FMC_ALE invalid	4Tfmc_ker_ck –1	-	ns

Table 65 (pages 235–235)

Table 65 · 7 columns × 21 rows · p.235–235 · CSV

Symbol	Parameter	Min	Max(2)		Unit
tw(SDCLK)	FMC_SDCLK period	2Tfmc_ker_ck – 0.5	2Tfmc_ker_ck +0.5		ns
tsu(SDCLKH _Data)	Data input setup time	2.5	-	-	ns	ns
th(SDCLKH_Data)	Data input hold time	0.5	-	-	ns	ns
td(SDCLKL_Add)	Address valid time	-	1.5	1.5	ns	ns
td(SDCLKL-SDNE)	Chip select valid time	-	1	1	ns	ns
th(SDCLKL_SDNE)	Chip select hold time	0	-	-	ns	ns
td(SDCLKL_SDNRAS)	SDNRAS valid time	-	1.5	1.5	ns	ns
th(SDCLKL_SDNRAS)	SDNRAS hold time	0	-	-	ns	ns
td(SDCLKL_SDNCAS)	SDNCAS valid time	-	1.5	1.5	ns	ns
th(SDCLKL_SDNCAS)	SDNCAS hold time	0	-	-	ns	ns
1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Table 94. LPSDR SDRAM read timings(1)	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Table 94. LPSDR SDRAM read timings(1)	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Table 94. LPSDR SDRAM read timings(1)	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Table 94. LPSDR SDRAM read timings(1)	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Table 94. LPSDR SDRAM read timings(1)	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Table 94. LPSDR SDRAM read timings(1)	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Table 94. LPSDR SDRAM read timings(1)
Symbol	Parameter	Min	Min	Max(2)	Max(2)	Unit
tW(SDCLK)	FMC_SDCLK period	2Tfmc_ker_ck – 0.5	2Tfmc_ker_ck – 0.5	2Tfmc_ker_ck +0.5	2Tfmc_ker_ck +0.5	ns
tsu(SDCLKH_Data)	Data input setup time	2	2	-	-	ns
th(SDCLKH_Data)	Data input hold time	1	1	-	-	ns
td(SDCLKL_Add)	Address valid time	-	-	1.5	1.5	ns
td(SDCLKL_SDNE)	Chip select valid time	-	-	1	1	ns
th(SDCLKL_SDNE)	Chip select hold time	0	0	-	-	ns
td(SDCLKL_SDNRAS	SDNRAS valid time	-	-	1.5	1.5	ns
th(SDCLKL_SDNRAS)	SDNRAS hold time	0	0	-	-	ns
td(SDCLKL_SDNCAS)	SDNCAS valid time	-	-	1.5	1.5	ns
th(SDCLKL_SDNCAS)	SDNCAS hold time	0	0	-	-	ns

Table 66 (pages 236–236)

Table 66 · 5 columns × 11 rows · p.236–236 · CSV

FMC_SDCLK td(SDCLKL_AddR) td(SDCLKL_AddC) th(SDCLKL_AddR) FMC_A[12:0] Row n Col1 Col2 Coli Coln th(SDCLKL_AddC) td(SDCLKL_SNDE) th(SDCLKL_SNDE)FMC_SDNE[1:0] td(SDCLKL_NRAS) th(SDCLKL_NRAS) FMC_SDNRAS td(SDCLKL_NCAS) th(SDCLKL_NCAS)FMC_SDNCAS FMC_SDNWE tsu(SDCLKH_Data) th(SDCLKH_Data) FMC_D[31:0] Data1 Data2 Datai Datan
Table 95. SDRAM Write timings(1)
Symbol	Parameter	Min	Max(2)	Unit
tw(SDCLK)	FMC_SDCLK period	2Tfmc_ker_ck – 0.5	2Tfmc_ker_ck +0.5	ns
td(SDCLKL _Data )	Data output valid time	-	1.5	ns
th(SDCLKL _Data)	Data output hold time	0	-	ns
td(SDCLKL_Add)	Address valid time	-	1.5	ns
td(SDCLKL_SDNWE)	SDNWE valid time	-	1.5	ns
th(SDCLKL_SDNWE)	SDNWE hold time	0.5	-	ns
td(SDCLKL_ SDNE)	Chip select valid time	-	1	ns
th(SDCLKL-_SDNE)	Chip select hold time	0	-	ns
td(SDCLKL_SDNRAS)	SDNRAS valid time	-	1	ns
th(SDCLKL_SDNRAS)	SDNRAS hold time	0	-	ns
td(SDCLKL_SDNCAS)	SDNCAS valid time	-	1	ns
td(SDCLKL_SDNCAS)	SDNCAS hold time	0	-	ns

Table 67 (pages 237–237)

Table 67 · 5 columns × 11 rows · p.237–237 · CSV

Symbol	Parameter	Min	Max(2)	Unit
tw(SDCLK)	FMC_SDCLK period	2Tfmc_ker_ck – 0.5	2Tfmc_ker_ck +0.5	ns
td(SDCLKL _Data )	Data output valid time	-	1.5	ns
th(SDCLKL _Data)	Data output hold time	0	-	ns
td(SDCLKL_Add)	Address valid time	-	1.5	ns
td(SDCLKL-SDNWE)	SDNWE valid time	-	1.5	ns
th(SDCLKL-SDNWE)	SDNWE hold time	0.5	-	ns
td(SDCLKL-SDNE)	Chip select valid time	-	1	ns
th(SDCLKL-SDNE)	Chip select hold time	0	-	ns
td(SDCLKL-SDNRAS)	SDNRAS valid time	-	1	ns
th(SDCLKL-SDNRAS)	SDNRAS hold time	0	-	ns
td(SDCLKL-SDNCAS)	SDNCAS valid time	-	1	ns
td(SDCLKL-SDNCAS)	SDNCAS hold time	0	-	ns

Table 68 (pages 239–241)

Table 68 · 7 columns × 45 rows · p.239–241 · CSV

Symbol	Parameter	Conditions	Min	Typ	Max(2)	Unit
F(CLK)	XSPI clock frequency	2.7 V < VDD < 3.6 V, 2.7 V<VDDXSPI1/2 <3.6 V, CLOAD = 15 pF	-	-	180(3)	MHz
F(CLK)	XSPI clock frequency	1.71 V < VDD < 3.6 V, 1.62 V<VDDXSPI1/2 <3.6V, CLOAD =15 pF	-	-	145(3)	MHz
tw(CLKH)	XSPI clock high and low time, even division	PRESCALER[7:0] = n =0,1,3,5	t(CLK) /2	-	t(CLK) /2+1	ns
tw(CLKL)	XSPI clock high and low time, even division	PRESCALER[7:0] = n =0,1,3,5	t(CLK) /2–1	-	t(CLK) /2	ns
tw(CLKH)	XSPI clock high and low time, odd division	PRESCALER[7:0] = n =2,4,6,8	(n/2)*t(CLK) /(n+1)	-	(n/2)*t(CLK) /(n+1)+1	ns
tw(CLKL)	XSPI clock high and low time, odd division	PRESCALER[7:0] = n =2,4,6,8	(n/2+1)*t(CLK) /(n+1)–1	-	(n/2+1)*t(CLK) /(n+1)	ns
ts(IN)	Data input setup time	-	2.0	-	-	ns
th(IN)	Data input hold time	-	2.5	-	-	ns
tv(OUT)	Data output valid time	-	-	0.5	1	ns
th(OUT)	Data output hold time	-	0	-	-	ns
F(CLK)	XSPI clock frequency	1.71 V < VDD < 3.6 V, 1.62 V<VDDXSPI1/2 <3.6V, CLOAD = 15 pF	-	-	135(3)	MHz
tw(CLKH)	XSPI clock high and low time, even division	PRESCALER[7:0] = n = 0,1,3,5	t(CLK) /2	-	t(CLK) /2+1	ns
tw(CLKL)	XSPI clock high and low time, even division	PRESCALER[7:0] = n = 0,1,3,5	t(CLK) /2–1	-	t(CLK) /2	ns
tw(CLKH)	XSPI clock high and low time, odd division	PRESCALER[7:0] = n = 2,4,6,8	(n/2)*t(CLK) /(n+1)	-	(n/2)*t(CLK) /(n+1)+1	ns
tw(CLKL)	XSPI clock high and low time, odd division	PRESCALER[7:0] = n = 2,4,6,8	(n/2+1)*t(CLK)/(n+1) – 1	-	(n/2+1)* t(CLK) /(n+1)	ns
tsr(IN) tsf(IN)	Data input setup time	-	2.0	-	-	ns
thr(IN) thf(IN)	Data input hold time	-	2.5	-	-	ns
tvr(OUT) tvf(OUT)	Data output valid time	-	-	t(CLK) /4+ 0.5	t(CLK) /4+1.5	ns
tvr(OUT) tvf(OUT)	Data output valid time	Prescaler = 0, F(CLK) <60 MHz	-	5	7	ns
thr(OUT) thf(OUT)	Data output hold time	-	t(CLK) /4 -0.5	-	-	ns
thr(OUT) thf(OUT)	Data output hold time	Prescaler = 0, F(CLK) <60 MHz	3.5	-	-	ns
F(CLK)	XSPI clock frequency	1.71 V < VDD < 3.6 V, 1.62 V<VDDXSPI1/2 <3.6 V, CLOAD = 10 pF	-	-	190	MHz
F(CLK)	XSPI clock frequency	1.71 V < VDD < 3.6 V, 1.8 V<VDDXSPI1/2 <1.98 V, CLOAD = 10 pF	-	-	200	MHz
F(CLK)	XSPI clock frequency	1.71 V < VDD < 3.6 V, 1.62 V<VDDXSPI1/2 <3.6 V, CLOAD = 15 pF	-	-	185	MHz
tw(CLKH)	XSPI clock high and low time, even division	PRESCALER[7:0] = n = 0,1,3,5	t(CLK) /2	-	t(CLK) /2+1	ns
tw(CLKL)	XSPI clock high and low time, even division	PRESCALER[7:0] = n = 0,1,3,5	t(CLK) /2–1	-	t(CLK) /2	ns
tw(CLKH)	XSPI clock high and low time, odd division	PRESCALER[7:0] = n = 2,4,6,8	(n/2)*t(CLK) /(n+1)	-	(n/2)*t(CLK) /(n+1)+1	ns
tw(CLKL)	XSPI clock high and low time, odd division	PRESCALER[7:0] = n = 2,4,6,8	(n/2+1)*t(CLK) /(n+1)–1	-	(n/2+1)*t(CLK) /(n+1)	ns
tv(CK)	Clock valid time	-	-	-	t(CLK) +1	ns
th(CK)	Clock hold time	-	t(CLK) /2	-	-	ns
VODr(CK)	CK,CK crossing level on CK rising edge	VDD =VDDXSPI1=VDDXSPI2 =1.8 V	1024	-	1353	mV
VODf(CK)	CK,CK crossing level on CK falling edge	VDD =VDDXSPI1=VDDXSPI2 =1.8 V	907	-	1229	mV
tw(CS)	Chip select high time	-	3*t(CLK)	-	-	ns
tv(DQ)	Data input vallid time	-	0	-	-	ns
tv(DS)	Data strobe input valid time	-	0	-	-	ns
th(DS)	Data strobe input hold time	-	0	-	-	ns
tv(RWDS)	Data strobe output valid time	-	-	-	3 x t(CLK)	ns
tsr(DQ), tsf(DQ)	Data input setup time	-	1.5 -t(CLK) /4	-	-	ns
tsr(DQ), tsf(DQ)	Data input setup time	F(CLK) < 60 MHz	-3	-	-	ns
thr(DQ), thf(DQ)	Data input hold time	-	1.5 + t(ClK) /4	-	-	ns
thr(DQ), thf(DQ)	Data input hold time	F(CLK) < 60 MHz	7.5	-	-	ns
tvr(OUT), tvf(OUT)	Data output valid time	-	-	t(ClK) /4+0.5	t(ClK) /4+1.5	ns
tvr(OUT), tvf(OUT)	Data output valid time	Prescaler = 0, F(CLK) < 60 MHz	-	5	7	ns
thr(OUT), thf(OUT)	Data output hold time	-	t(ClK) /4-1	-	-	ns
thr(OUT), thf(OUT)	Data output hold time	Prescaler = 0, F(CLK) < 60 MHz	3.5	-	-	ns

Table 69 (pages 243–243)

Table 69 · 7 columns × 2 rows · p.243–243 · CSV

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
tinit	Initial delay	-	2400	2500	3000	ps
tΔ	Unit Delay	-	41	48	57	ps

Table 70 (pages 244–244)

Table 70 · 12 columns × 20 rows · p.244–244 · CSV

Symbol	Parameter	Conditions						Min	Typ	Max	Unit
VDDA	Analog power supply for ADC ON	-	-	-	-	-	-	1.62	-	3.6	V
VREF+	Positive reference voltage	-	-	-	-	-	-	1.62	-	VDDA	V
VREF-	Negative reference voltage	-	-	-	-	-	-	VSSA	VSSA	VSSA	V
fADC	ADC clock frequency	1.62 V ≤ VDDA ≤ 3.6 V	1.62 V ≤ VDDA ≤ 3.6 V	1.62 V ≤ VDDA ≤ 3.6 V	1.62 V ≤ VDDA ≤ 3.6 V	1.62 V ≤ VDDA ≤ 3.6 V	1.62 V ≤ VDDA ≤ 3.6 V	1.5	-	75	MHz
f S(3) with RAIN =47Ω and CPCB =22 pF	Sampling rate for fast channels (VIN [0:5])	Resolutio n = 12 bits	Continuou s mode	1.8 V≤VDDA ≤3.6 V	-40°C ≤ TJ≤ 130°C	fADC =75 MHz	SMP=2.5	-	5.00	-	MSPS
f S(3) with RAIN =47Ω and CPCB =22 pF	Sampling rate for fast channels (VIN [0:5])	Resolutio n = 12 bits	Continuou s mode	1.6 V≤VDDA ≤3.6 V	-40°C ≤ TJ≤ 130°C	fADC =70 MHz	SMP=2.5	-	4.66		MSPS
f S(3) with RAIN =47Ω and CPCB =22 pF	Sampling rate for fast channels (VIN [0:5])	Resolutio n = 12 bits	Single or discontinu ous mode	2.4 V≤VDDA ≤3.6V	-40°C ≤ TJ≤ 130°C	fADC =60 MHz	SMP=2.5	-	4.00	-	MSPS
f S(3) with RAIN =47Ω and CPCB =22 pF	Sampling rate for fast channels (VIN [0:5])	Resolutio n = 12 bits	Single or discontinu ous mode	1.6 V≤VDDA ≤3.6 V	-40°C ≤ TJ≤ 130°C	fADC =50 MHz	SMP=2.5	-	3.33	-	MSPS
f S(3) with RAIN =47Ω and CPCB =22 pF	Sampling rate for fast channels (VIN [0:5])	Resolutio n = 10 bits	Continuou s Mode	1.6V≤VDDA≤3.6 V	-40°C ≤ TJ≤ 130°C	fADC =75 MHz	SMP=2.5	-	5.77	-	MSPS
f S(3) with RAIN =47Ω and CPCB =22 pF	Sampling rate for fast channels (VIN [0:5])	Resolutio n = 10 bits	Single or discontinu ous mode	2.4 V≤VDDA ≤3.6 V	-40°C ≤ TJ≤ 130°C	fADC =75 MHz	SMP=2.5		5.77	-	MSPS
f S(3) with RAIN =47Ω and CPCB =22 pF	Sampling rate for fast channels (VIN [0:5])	Resolutio n = 10 bits	Single or discontinu ous mode	1.6 V≤VDDA ≤3.6 V	-40°C ≤ TJ≤ 130°C	fADC =65 MHz	SMP=2.5		5.00	-	MSPS
f S(3) with RAIN =47Ω and CPCB =22 pF	Sampling rate for fast channels (VIN [0:5])	Resolutio n = 8 bits	All modes	1.6 V≤VDDA ≤3.6V	-40°C ≤ TJ≤ 130°C	fADC =75 MHz	SMP=2.5	-	6.82	-	MSPS
f S(3) with RAIN =47Ω and CPCB =22 pF	Sampling rate for fast channels (VIN [0:5])	Resolutio n = 6 bits	All modes	1.6 V≤VDDA ≤3.6V	-40°C ≤ TJ≤ 130°C	fADC =75 MHz	SMP=2.5	-	8.33	-	MSPS
f S(3) with RAIN =47Ω and CPCB =22 pF	Sampling rate for slow channels	Resolutio n = 12 bits	All modes	1.6 V≤VDDA ≤3.6 V	-40°C ≤ TJ≤ 130°C	fADC =35MHz	SMP=2.5	-	2.30	-	MSPS
f S(3) with RAIN =47Ω and CPCB =22 pF	Sampling rate for slow channels	Resolutio n = 10 bits	All modes	1.6 V≤VDDA ≤3.6 V	-40°C ≤ TJ≤ 130°C	fADC =35MHz	SMP=2.5	-	2.70	-	MSPS
f S(3) with RAIN =47Ω and CPCB =22 pF	Sampling rate for slow channels	Resolutio n = 8 bits	All modes	1.6 V≤VDDA ≤3.6 V	-40°C ≤ TJ≤ 130°C	fADC =50MHz	SMP=2.5	-	4.50	-	MSPS
f S(3) with RAIN =47Ω and CPCB =22 pF	Sampling rate for slow channels	Resolutio n = 6 bits	All modes	1.6 V≤VDDA ≤3.6 V	-40°C ≤ TJ≤ 130°C	fADC =50MHz	SMP=2.5	-	5.50	-	MSPS
tTRIG	External trigger period	Resolution = 12 bits	Resolution = 12 bits	Resolution = 12 bits	Resolution = 12 bits	Resolution = 12 bits	Resolution = 12 bits	-	-	15	1/fADC
V AIN(2)	Conversion voltage range	-	-	-	-	-	-	0	-	VREF+	V
VCMIV	Common mode input voltage	-	-	-	-	-	-	VREF /2−10%	VREF /2	VREF /2+ 10%	V

Table 71 (pages 245–246)

Table 71 · 7 columns × 31 rows · p.245–246 · CSV

Symbol	Parameter	Conditions	Min	Typ	Max	Unit
R AIN(4)	External input impedance	Resolution = 12 bits, TJ = 140°C (Tolerance 4 LSBs)	-	-	321	Ω
R AIN(4)	External input impedance	Resolution = 12 bits, TJ = 130°C	-	-	220	Ω
R AIN(4)	External input impedance	Resolution = 10 bits, TJ = 130°C	-	-	2100	Ω
R AIN(4)	External input impedance	Resolution = 8 bits, TJ = 130°C	-	-	12000	Ω
R AIN(4)	External input impedance	Resolution = 6 bits, TJ = 130°C	-	-	80000	Ω
CADC	Internal sample and hold capacitor	-	-	3	-	pF
tADCVREG_STUP	ADC LDO startup time	-	-	5	10	µs
tSTAB	ADC power-up time	LDO already started	1	-	-	Conversion cycles
tOFF_CAL	Offset calibration time	-	1335	1335	1335	fADC clock cycles
tLATR	Trigger conversion latency for regular and injected channels without aborting the conversion	CKMODE = 00	1.5	2	2.5	fADC clock cycles
tLATR	Trigger conversion latency for regular and injected channels without aborting the conversion	CKMODE = 01	-	-	2.5	fADC clock cycles
tLATR	Trigger conversion latency for regular and injected channels without aborting the conversion	CKMODE = 10			2.5	fADC clock cycles
tLATR	Trigger conversion latency for regular and injected channels without aborting the conversion	CKMODE = 11			2.25	fADC clock cycles
tLATRINJ	Trigger conversion latency for regular and injected channels when a regular conversion is aborted	CKMODE = 00	2.5	3	3.5	fADC clock cycles
tLATRINJ	Trigger conversion latency for regular and injected channels when a regular conversion is aborted	CKMODE = 01	-	-	3.5	fADC clock cycles
tLATRINJ	Trigger conversion latency for regular and injected channels when a regular conversion is aborted	CKMODE = 10	-	-	3.5	fADC clock cycles
tLATRINJ	Trigger conversion latency for regular and injected channels when a regular conversion is aborted	CKMODE = 11	-	-	3.25	fADC clock cycles
tS	Sampling time	-	2.5	-	640.5	fADC clock cycles
tCONV	Total conversion time (including sampling time)	N-bits resolution	tS +0.5 +N	-	-	fADC clock cycles
IDDA_D (ADC)	ADC consumption on VDDA and VREF, Differential mode	fs= 5 MSPS	-	600	-	µA
IDDA_D (ADC)	ADC consumption on VDDA and VREF, Differential mode	fs= 1 MSPS	-	190	-	µA
IDDA_D (ADC)	ADC consumption on VDDA and VREF, Differential mode	fs= 0.1 MSPS	-	50	-	µA
IDDA_SE(ADC)	ADC consumption on VDDA and VREF Single-ended mode	fs= 5 MSPS	-	500	-	µA
IDDA_SE(ADC)	ADC consumption on VDDA and VREF Single-ended mode	fs= 1 MSPS	-	150	-	µA
IDDA_SE(ADC)	ADC consumption on VDDA and VREF Single-ended mode	fs= 0.1 MSPS	-	50	-	µA
IDD(ADC)	ADC consumption on VDD	fADC =75 MHz	-	265	-	µA
IDD(ADC)	ADC consumption on VDD	fADC =50 MHz		175	-	µA
IDD(ADC)	ADC consumption on VDD	fADC =25 MHz	-	90	-	µA
IDD(ADC)	ADC consumption on VDD	fADC =12.5 MHz	-	45	-	µA
IDD(ADC)	ADC consumption on VDD	fADC =6.25 MHz	-	22	-	µA
IDD(ADC)	ADC consumption on VDD	fADC =3.125 MHz	-	11	-	µA

Table 72 (pages 247–248)

Table 72 · 4 columns × 52 rows · p.247–248 · CSV

Resolution	RAIN (Ω)	Minimum sampling time (s)
Resolution	RAIN (Ω)	Fast channels(3)	Slow channels(4)
12 bits	47	3.75E-08	6.12E-08
12 bits	68	3.94E-08	6.25E-08
12 bits	100	4.36E-08	6.51E-08
12 bits	150	5.11E-08	7.00E-08
12 bits	220	6.54E-08	7.86E-08
12 bits	330	8.80E-08	9.57E-08
12 bits	470	1.17E-07	1.23E-07
12 bits	680	1.60E-07	1.65E-07
10 bits	47	3.19E-08	5.17E-08
10 bits	68	3.35E-08	5.28E-08
10 bits	100	3.66E-08	5.45E-08
10 bits	150	4.35E-08	5.83E-08
10 bits	220	5.43E-08	6.50E-08
10 bits	330	7.18E-08	7.89E-08
10 bits	470	9.46E-08	1.00E-07
10 bits	680	1.28E-07	1.33E-07
10 bits	1000	1.81E-07	1.83E-07
10 bits	1500	2.63E-07	2.63E-07
10 bits	2200	3.79E-07	3.76E-07
10 bits	3300	5.57E-07	5.52E-07
8 bits	47	2.64E-08	4.17E-08
8 bits	68	2.76E-08	4.24E-08
8 bits	100	3.02E-08	4.39E-08
8 bits	150	3.51E-08	4.66E-08
8 bits	220	4.27E-08	5.13E-08
8 bits	330	5.52E-08	6.19E-08
8 bits	470	7.17E-08	7.72E-08
8 bits	680	9.68E-08	1.00E-07
8 bits	1000	1.34E-07	1.37E-07
8 bits	1500	1.93E-07	1.94E-07
8 bits	2200	2.76E-07	2.74E-07
8 bits	3300	4.06E-07	4.01E-07
8 bits	4700	5.73E-07	5.62E-07
8 bits	6800	8.21E-07	7.99E-07
8 bits	10000	1.20E-06	1.17E-06
8 bits	15000	1.79E-06	1.74E-06
6 bits	47	2.14E-08	3.16E-08
6 bits	68	2.23E-08	3.21E-08
6 bits	100	2.40E-08	3.31E-08
6 bits	150	2.68E-08	3.52E-08
6 bits	220	3.13E-08	3.87E-08
6 bits	330	3.89E-08	4.51E-08
6 bits	470	4.88E-08	5.39E-08
6 bits	680	6.38E-08	6.79E-08
6 bits	1000	8.70E-08	8.97E-08
6 bits	1500	1.23E-07	1.24E-07
6 bits	2200	1.73E-07	1.73E-07
6 bits	3300	2.53E-07	2.49E-07
6 bits	4700	3.53E-07	3.45E-07
6 bits	6800	5.04E-07	4.90E-07
6 bits	10000	7.34E-07	7.11E-07
6 bits	15000	1.09E-06	1.05E-06

Table 73 (pages 249–250)

Table 73 · 8 columns × 44 rows · p.249–250 · CSV

Symbol	Parameter	Conditions		Min	Typ	Max	Unit
ET	Total unadjusted error	Fast and slow channels	Single ended	-	±3.5	±12	LSB
ET	Total unadjusted error	Fast and slow channels	Differential	-	±2.5	±7.5	LSB
EO	Offset error	-	Single ended	-	±3	±5.5	LSB
EO	Offset error	-	Differential	-	±2	±3.5	LSB
EG	Gain error	-	Single ended	-	±3.5	±11	LSB
EG	Gain error	-	Differential	-	±2.5	±7	LSB
ED	Differential linearity error	-	Single ended		±0.75	+2/-1	LSB
ED	Differential linearity error	-	Differential	-	±0.75	+2/-1	LSB
EL	Integral linearity error	Fast and slow channels	Single ended	-	±2	±6.5	LSB
EL	Integral linearity error	Fast and slow channels	Differential	-	±1	±4	LSB
ENOB	Effective number of bits	Single ended	Single ended	-	10.8	-	bits
ENOB	Effective number of bits	Differential	Differential	-	11.5	-	bits
SINAD	Signal-to-noise and distortion ratio	Single ended	Single ended	-	68	-	dB
SINAD	Signal-to-noise and distortion ratio	Differential	Differential	-	71	-	dB
SNR	Signal-to-noise ratio	Single ended	Single ended	-	70	-	dB
SNR	Signal-to-noise ratio	Differential	Differential	-	72	-	dB
THD	Total harmonic distortion	Single ended	Single ended	-	-70	-	dB
THD	Total harmonic distortion	Differential	Differential	-	-80	-	dB
VDDA	Analog supply voltage	Normal mode, VDDA = 3.3 V	VRS = 000	2.8	3.3	3.6	V
VDDA	Analog supply voltage	Normal mode, VDDA = 3.3 V	VRS = 001	2.4	-	3.6	V
VDDA	Analog supply voltage	Normal mode, VDDA = 3.3 V	VRS = 010	2.1	-	3.6	V
VDDA	Analog supply voltage	Degraded mode(2)	VRS = 000	1.62	-	2.80	V
VDDA	Analog supply voltage	Degraded mode(2)	VRS = 001	1.62	-	2.40	V
VDDA	Analog supply voltage	Degraded mode(2)	VRS = 010	1.62	-	2.10	V
VREFBUF_OUT	Voltage reference buffer output, at 30 °C, Iload = 100 µA	Normal mode at 30 °C, Iload = 100 µA	VRS = 000	2.4980(3)	2.5000	2.5035(3)	V
VREFBUF_OUT	Voltage reference buffer output, at 30 °C, Iload = 100 µA	Normal mode at 30 °C, Iload = 100 µA	VRS = 001	2.0460	2.0490	2.0520	V
VREFBUF_OUT	Voltage reference buffer output, at 30 °C, Iload = 100 µA	Normal mode at 30 °C, Iload = 100 µA	VRS = 010	1.8010	1.8040	1.8060	V
VREFBUF_OUT	Voltage reference buffer output, at 30 °C, Iload = 100 µA	Degraded mode(2)	VRS = 000	VDDA -150 mV	-	VDDA	V
VREFBUF_OUT	Voltage reference buffer output, at 30 °C, Iload = 100 µA	Degraded mode(2)	VRS = 001	VDDA -150 mV	-	VDDA	V
VREFBUF_OUT	Voltage reference buffer output, at 30 °C, Iload = 100 µA	Degraded mode(2)	VRS = 010	VDDA -150 mV	-	VDDA	V
TRIM	Trim step resolution	-	-	-	±0.05	±0.1	%
CL	Load capacitor	-	-	0.5	1	1.50	µF
esr	Equivalent Serial Resistor of CL	-	-	-	-	2	Ω
ILOAD	Static load current	-	-	-	-	4	mA
Iline_reg	Line regulation	2.8 V ≤ VDDA ≤3.6 V	Iload = 500 µA	-	200	-	ppm/V
Iline_reg	Line regulation	2.8 V ≤ VDDA ≤3.6 V	Iload = 4 mA	-	100	-	ppm/V
Iload_reg	Load regulation	500 µA ≤ ILOAD ≤4 mA	Normal mode	-	50	-	ppm/ mA
Tcoeff	Temperature coefficient	-40 °C < TJ < +130 °C	-40 °C < TJ < +130 °C	-	-	Tcoeff VREFINT+ 100	ppm/°C
PSRR	Power supply rejection	DC	DC	-	60	-	dB
PSRR	Power supply rejection	100 KHz	100 KHz	-	40	-	dB
tSTART	Start-up time	CL =0.5 µF	CL =0.5 µF	-	300	-	µs
tSTART	Start-up time	CL =1 µF	CL =1 µF	-	500	-	µs
tSTART	Start-up time	CL =1.5 µF	CL =1.5 µF	-	650	-	µs
IINRUSH	Control of maximum DC current drive on VREFBUF_OUT during startup phase(4)	-	-	-	8	-	mA

Table 74 (pages 252–252)

Table 74 · 17 columns × 17 rows · p.252–252 · CSV

Symbol	Parameter				Condition						Min		Typ	Max		Unit
VDD	Supply voltage	Supply voltage	Supply voltage	Supply voltage	-	-	-	-	-	-	1.71	1.71	2.6	3.6	3.6	V
tSU(BOOST)	Booster startup time	Booster startup time	Booster startup time	Booster startup time	-	-	-	-	-	-	-	-	-	50	50	µs
IDD(BOOST)	Booster consumption	Booster consumption	Booster consumption	Booster consumption	1.71 V ≤ VDD ≤ 2.7 V	1.71 V ≤ VDD ≤ 2.7 V	1.71 V ≤ VDD ≤ 2.7 V	1.71 V ≤ VDD ≤ 2.7 V	1.71 V ≤ VDD ≤ 2.7 V	1.71 V ≤ VDD ≤ 2.7 V	-	-	-	125	125	µA
IDD(BOOST)	Booster consumption	Booster consumption	Booster consumption	Booster consumption	2.7 V < VDD < 3.6 V	2.7 V < VDD < 3.6 V	2.7 V < VDD < 3.6 V	2.7 V < VDD < 3.6 V	2.7 V < VDD < 3.6 V	2.7 V < VDD < 3.6 V	-	-	-	250	250	µA
1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)	1. Evaluated by characterization -Not tested in production. Digital temperature sensor characteristics Table 108. Digital temperature sensor characteristics(1)
Symbol	Symbol	Symbol	Parameter	Parameter	Parameter	Conditions	Conditions	Min	Min	Typ	Typ		Max	Max	Unit	Unit
f DTS(2)	f DTS(2)	f DTS(2)	Output clock frequency	Output clock frequency	Output clock frequency	VDD_CORE =1.19 V(3)	VDD_CORE =1.19 V(3)	500	500	750	750		1150	1150	kHz	kHz
T LC(2)	T LC(2)	T LC(2)	Temperature linearity coefficient	Temperature linearity coefficient	Temperature linearity coefficient	VDD_CORE =1.19 V(3)	VDD_CORE =1.19 V(3)	1660	1660	2100	2100		2750	2750	Hz/°C	Hz/°C
T TOTAL_ERROR(2)	T TOTAL_ERROR(2)	T TOTAL_ERROR(2)	Temperature offset measurement, all VOS	Temperature offset measurement, all VOS	Temperature offset measurement, all VOS	TJ = -40°C to 30°C	TJ = -40°C to 30°C	-13	-13	-	-		4	4	°C	°C
T TOTAL_ERROR(2)	T TOTAL_ERROR(2)	T TOTAL_ERROR(2)	Temperature offset measurement, all VOS	Temperature offset measurement, all VOS	Temperature offset measurement, all VOS	TJ = 30°C to 130°C	TJ = 30°C to 130°C	-7	-7	-	-		2	2	°C	°C
TVDD_CORE	TVDD_CORE	TVDD_CORE	Additional error due to supply variation	Additional error due to supply variation	Additional error due to supply variation	-	-	-1	-1	-	-		1	1	°C	°C
tTRIM	tTRIM	tTRIM	Calibration time	Calibration time	Calibration time	-	-	-	-	-	-		2	2	ms	ms
tWAKE_UP	tWAKE_UP	tWAKE_UP	Wake-up time from off state until DTS ready bit is set	Wake-up time from off state until DTS ready bit is set	Wake-up time from off state until DTS ready bit is set	-	-	-	-	67	67		116.00	116.00	µs	µs
IDDCORE_DTS	IDDCORE_DTS	IDDCORE_DTS	DTS consumption on VDD_CORE	DTS consumption on VDD_CORE	DTS consumption on VDD_CORE	-	-	8.5	8.5	30	30		70.0	70.0	µA	µA
1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics	1. Guaranteed by design, unless otherwise specified. 2. Evaluated by characterization -Not tested in production. 3. The characterization is done at VDD_CORE = 1.19 V for Typ/Min/Max. VCORE monitoring characteristics Table 109. VCORE monitoring characteristics
Symbol	Symbol	Parameter	Parameter	Conditions	Conditions	Conditions	Min	Min	Typ	Typ	Typ	Max	Max	Max	Unit	Unit
ts_vcore	ts_vcore	ADC sampling time when reading the VCORE voltage	ADC sampling time when reading the VCORE voltage	-	-	-	1	1	-	-	-	-	-	-	µs	µs

Table 75 (pages 253–253)

Table 75 · 16 columns × 15 rows · p.253–253 · CSV

Symbol		Parameter				Min			Typ			Max		Unit
R	R	Resistor bridge for VBAT	Resistor bridge for VBAT	Resistor bridge for VBAT	Resistor bridge for VBAT	-	-	-	4x26	4x26	4x26	-	-	kΩ	kΩ
Q	Q	Ratio on VBAT measurement	Ratio on VBAT measurement	Ratio on VBAT measurement	Ratio on VBAT measurement	-	-	-	4	4	4	-	-	-	-
Er(1)	Er(1)	Error on Q	Error on Q	Error on Q	Error on Q	-10	-10	-10	-	-	-	+10	+10	%	%
t S_vbat(1)	t S_vbat(1)	ADC sampling time when reading VBAT input	ADC sampling time when reading VBAT input	ADC sampling time when reading VBAT input	ADC sampling time when reading VBAT input	9	9	9	-	-	-	-	-	µs	µs
VBAThigh	VBAThigh	High supply monitoring	High supply monitoring	High supply monitoring	High supply monitoring	-	-	-	3.575	3.575	3.575	-	-	V	V
VBATlow	VBATlow	Low supply monitoring	Low supply monitoring	Low supply monitoring	Low supply monitoring	-	-	-	1.36	1.36	1.36	-	-	V	V
I VBATbuf(1)	I VBATbuf(1)	Sensor buffer consuption	Sensor buffer consuption	Sensor buffer consuption	Sensor buffer consuption	-	-	-	3.8	3.8	3.8	6.5	6.5	µA	µA
1. Guaranteed by design. Table 111. VBAT charging characteristics	1. Guaranteed by design. Table 111. VBAT charging characteristics	1. Guaranteed by design. Table 111. VBAT charging characteristics	1. Guaranteed by design. Table 111. VBAT charging characteristics	1. Guaranteed by design. Table 111. VBAT charging characteristics	1. Guaranteed by design. Table 111. VBAT charging characteristics	1. Guaranteed by design. Table 111. VBAT charging characteristics	1. Guaranteed by design. Table 111. VBAT charging characteristics	1. Guaranteed by design. Table 111. VBAT charging characteristics	1. Guaranteed by design. Table 111. VBAT charging characteristics	1. Guaranteed by design. Table 111. VBAT charging characteristics	1. Guaranteed by design. Table 111. VBAT charging characteristics	1. Guaranteed by design. Table 111. VBAT charging characteristics	1. Guaranteed by design. Table 111. VBAT charging characteristics	1. Guaranteed by design. Table 111. VBAT charging characteristics	1. Guaranteed by design. Table 111. VBAT charging characteristics
Symbol	Parameter	Parameter	Parameter	Condition	Condition	Condition	Min	Min	Min	Typ	Typ	Typ	Max	Max	Unit
RBC	Battery charging resistor	Battery charging resistor	Battery charging resistor	VBRS in PWR_CR3= 0	VBRS in PWR_CR3= 0	VBRS in PWR_CR3= 0	-	-	-	5	5	5	-	-	kΩ
RBC	Battery charging resistor	Battery charging resistor	Battery charging resistor	VBRS in PWR_CR3= 1	VBRS in PWR_CR3= 1	VBRS in PWR_CR3= 1	-	-	-	1.5	1.5	1.5	-	-	kΩ
Table 112. Temperature monitoring characteristics	Table 112. Temperature monitoring characteristics	Table 112. Temperature monitoring characteristics	Table 112. Temperature monitoring characteristics	Table 112. Temperature monitoring characteristics	Table 112. Temperature monitoring characteristics	Table 112. Temperature monitoring characteristics	Table 112. Temperature monitoring characteristics	Table 112. Temperature monitoring characteristics	Table 112. Temperature monitoring characteristics	Table 112. Temperature monitoring characteristics	Table 112. Temperature monitoring characteristics	Table 112. Temperature monitoring characteristics	Table 112. Temperature monitoring characteristics	Table 112. Temperature monitoring characteristics	Table 112. Temperature monitoring characteristics
Symbol	Symbol	Symbol	Parameter	Parameter	Min	Min	Min	Typ	Typ	Typ	Max	Max	Max	Unit	Unit
TEMPhigh	TEMPhigh	TEMPhigh	High temperature monitoring	High temperature monitoring	-	-	-	126	126	126	-	-	-	°C	°C
TEMPlow	TEMPlow	TEMPlow	Low temperature monitoring	Low temperature monitoring	-	-	-	-37	-37	-37	-	-	-	°C	°C

Table 76 (pages 254–254)

Table 76 · 7 columns × 13 rows · p.254–254 · CSV

Symbol	Parameter	Conditions	Min	Typ	Max	Units
FCCKI	Input clock frequency via the ADF_CCK[1:0] pin, in SLAVE_SPI mode	1.71<VDD<3.6 V	-	-	25	MHz
FCCKO	Output clock frequency in MASTER_SPI	1.71<VDD<3.6 V	-	-	25	MHz
FCCKOLF	Output clock frequency in LF_MASTER_SPI	1.71<VDD<3.6 V	-	-	5	MHz
FSYMB	Input symbol rate in MANCHESTER mode	1.71<VDD<3.6 V	-	-	20	MHz
THCCKI , TLCCKI	ADF_CCK[1:0] input clock high and low time	In SLAVE_SPI mode	2 x Tadf_proc_ck	-	-	ns
THCCKO , TLCCKO	ADF_CCK[1:0] output clock high and low time	In MASTER_SPI mode	2 x Tadf_proc_ck	-	-	ns
THCCKOLF , TLCCKOLF	ADF_CCK[1:0] output clock high and low time	In LF_MASTER_SPI mode	Tadf_proc_ck	-	-	ns
TSUCCKI	Data setup time w.r.t. ADF_CCK[1:0] input	In SLAVE_SPI mode: ADF_CCK[1:0] configured in input, measured on rising and falling edge	2.5	-	-	ns
THDCCKI	Data hold time w.r.t. ADF_CCK[1:0] input	In SLAVE_SPI mode: ADF_CCK[1:0] configured in input, measured on rising and falling edge	0.5	-	-	ns
TSUCCKO	Data setup time w.r.t. ADF_CCK[1:0] output	In MASTER_SPI mode: ADF_CCK[1:0] configured in output, measured on rising and falling edge	3	-	-	ns
THDCCKO	Data hold time w.r.t. ADF_CCK[1:0] output	In MASTER_SPI mode: ADF_CCK[1:0] configured in output, measured on rising and falling edge	1	-	-	ns
TSUCCKOLF	Data setup time w.r.t. ADF_CCK[1:0] output	In LF_MASTER_SPI mode: ADF_CCK[1:0] configured in output, measured on rising and falling edge	13	-	-	ns
THDCCKOLF	Data hold time w.r.t. ADF_CCK[1:0] output	In LF_MASTER_SPI mode: ADF_CCK[1:0] configured in output, measured on rising and falling edge	0	-	-	ns

Table 77 (pages 256–256)

Table 77 · 6 columns × 8 rows · p.256–256 · CSV

Symbol		Parameter	Min	Max(2)	Unit
DCMIPP_PIXCLK	DCMIPP_PIXCLK	Pixel Clock input	-	120	MHz
Dpixel	Dpixel	Pixel Clock input duty cycle	30	70	%
tsu( DATA)	tsu( DATA)	Data input setup time	3	-	ns
th (DATA)	th (DATA)	Data hold time	1	-	ns
tsu(HSYNC), tsu(VSYNC)	tsu(HSYNC), tsu(VSYNC)	DCMI_HSYNC/ DCMI_VSYNC input setup time	2.5	-	ns
th(HSYNC), th(VSYNC)	th(HSYNC), th(VSYNC)	DCMI_HSYNC/ DCMI_VSYNC input hold time	1	-	ns
1. Evaluated By characterization – Not tested in production. 2. At VOS low, these values are degraded by up to 7%. Figure 56. DCMIPP timing diagram 1/DCMIPP_PIXCLK DCMIPP_PIXCLK tsu(HSYNC) th(HSYNC) DCMIPP_HSYNC tsu(VSYNC) th(HSYNC) DCMIPP_VSYNC tsu(DATA) th(DATA) DATA[15:0] MSv73149V1	1. Evaluated By characterization – Not tested in production. 2. At VOS low, these values are degraded by up to 7%. Figure 56. DCMIPP timing diagram 1/DCMIPP_PIXCLK DCMIPP_PIXCLK tsu(HSYNC) th(HSYNC) DCMIPP_HSYNC tsu(VSYNC) th(HSYNC) DCMIPP_VSYNC tsu(DATA) th(DATA) DATA[15:0] MSv73149V1	1. Evaluated By characterization – Not tested in production. 2. At VOS low, these values are degraded by up to 7%. Figure 56. DCMIPP timing diagram 1/DCMIPP_PIXCLK DCMIPP_PIXCLK tsu(HSYNC) th(HSYNC) DCMIPP_HSYNC tsu(VSYNC) th(HSYNC) DCMIPP_VSYNC tsu(DATA) th(DATA) DATA[15:0] MSv73149V1	1. Evaluated By characterization – Not tested in production. 2. At VOS low, these values are degraded by up to 7%. Figure 56. DCMIPP timing diagram 1/DCMIPP_PIXCLK DCMIPP_PIXCLK tsu(HSYNC) th(HSYNC) DCMIPP_HSYNC tsu(VSYNC) th(HSYNC) DCMIPP_VSYNC tsu(DATA) th(DATA) DATA[15:0] MSv73149V1	1. Evaluated By characterization – Not tested in production. 2. At VOS low, these values are degraded by up to 7%. Figure 56. DCMIPP timing diagram 1/DCMIPP_PIXCLK DCMIPP_PIXCLK tsu(HSYNC) th(HSYNC) DCMIPP_HSYNC tsu(VSYNC) th(HSYNC) DCMIPP_VSYNC tsu(DATA) th(DATA) DATA[15:0] MSv73149V1	1. Evaluated By characterization – Not tested in production. 2. At VOS low, these values are degraded by up to 7%. Figure 56. DCMIPP timing diagram 1/DCMIPP_PIXCLK DCMIPP_PIXCLK tsu(HSYNC) th(HSYNC) DCMIPP_HSYNC tsu(VSYNC) th(HSYNC) DCMIPP_VSYNC tsu(DATA) th(DATA) DATA[15:0] MSv73149V1
1. Evaluated By characterization – Not tested in production. 2. At VOS low, these values are degraded by up to 7%. Figure 56. DCMIPP timing diagram 1/DCMIPP_PIXCLK DCMIPP_PIXCLK tsu(HSYNC) th(HSYNC) DCMIPP_HSYNC tsu(VSYNC) th(HSYNC) DCMIPP_VSYNC tsu(DATA) th(DATA) DATA[15:0] MSv73149V1	1. Evaluated By characterization – Not tested in production. 2. At VOS low, these values are degraded by up to 7%. Figure 56. DCMIPP timing diagram 1/DCMIPP_PIXCLK DCMIPP_PIXCLK tsu(HSYNC) th(HSYNC) DCMIPP_HSYNC tsu(VSYNC) th(HSYNC) DCMIPP_VSYNC tsu(DATA) th(DATA) DATA[15:0] MSv73149V1	1. Evaluated By characterization – Not tested in production. 2. At VOS low, these values are degraded by up to 7%. Figure 56. DCMIPP timing diagram 1/DCMIPP_PIXCLK DCMIPP_PIXCLK tsu(HSYNC) th(HSYNC) DCMIPP_HSYNC tsu(VSYNC) th(HSYNC) DCMIPP_VSYNC tsu(DATA) th(DATA) DATA[15:0] MSv73149V1	1. Evaluated By characterization – Not tested in production. 2. At VOS low, these values are degraded by up to 7%. Figure 56. DCMIPP timing diagram 1/DCMIPP_PIXCLK DCMIPP_PIXCLK tsu(HSYNC) th(HSYNC) DCMIPP_HSYNC tsu(VSYNC) th(HSYNC) DCMIPP_VSYNC tsu(DATA) th(DATA) DATA[15:0] MSv73149V1	1. Evaluated By characterization – Not tested in production. 2. At VOS low, these values are degraded by up to 7%. Figure 56. DCMIPP timing diagram 1/DCMIPP_PIXCLK DCMIPP_PIXCLK tsu(HSYNC) th(HSYNC) DCMIPP_HSYNC tsu(VSYNC) th(HSYNC) DCMIPP_VSYNC tsu(DATA) th(DATA) DATA[15:0] MSv73149V1	1. Evaluated By characterization – Not tested in production. 2. At VOS low, these values are degraded by up to 7%. Figure 56. DCMIPP timing diagram 1/DCMIPP_PIXCLK DCMIPP_PIXCLK tsu(HSYNC) th(HSYNC) DCMIPP_HSYNC tsu(VSYNC) th(HSYNC) DCMIPP_VSYNC tsu(DATA) th(DATA) DATA[15:0] MSv73149V1

Table 78 (pages 257–257)

Symbol	Parameter	Conditions	Min	Max(2)	Unit
-	Frequency ratio PSSI_PDCK/fHCLK	-	-	0.4	-
PSSI_PDCK	PSSI Clock input	1.71 V<VDD <3.6 V	-	80(3)	MHz
Dpixel	PSSI Clock input duty cycle	-	30	70	%
tov (DATA)	Data output valid time	1.71 V<VDD <3.6 V	-	12.5	ns
toh (DATA)	Data output hold time	1.71 V<VDD <3.6 V	5.5	-	ns
tov( (DE)	DE output valid time	1.71 V<VDD <3.6 V	-	12	ns
toh (DE)	DE output hold time	1.71 V<VDD <3.6 V	5.5	-	ns
tsu(RDY)	RDY input setup time	1.71 V<VDD <3.6 V	0	-	ns
th(RDY)	RDY input hold time	1.71 V<VDD <3.6 V	0	-	ns

Table 79 (pages 258–258)

Table 78 · 6 columns × 9 rows · p.257–257 · CSV

Symbol	Parameter	Conditions	Min	Max(2)	Unit
-	Frequency ratio PSSI_PDCK/fHCLK	-	-	0.4	-
PSSI_PDCK	PSSI Clock input	1.71 V<VDD <3.6 V	-	80(3)	MHz
Dpixel	PSSI Clock input duty cycle	-	30	70	%
tov (DATA)	Data output valid time	1.71 V<VDD <3.6 V	-	12.5	ns
toh (DATA)	Data output hold time	1.71 V<VDD <3.6 V	5.5	-	ns
tov( (DE)	DE output valid time	1.71 V<VDD <3.6 V	-	12	ns
toh (DE)	DE output hold time	1.71 V<VDD <3.6 V	5.5	-	ns
tsu(RDY)	RDY input setup time	1.71 V<VDD <3.6 V	0	-	ns
th(RDY)	RDY input hold time	1.71 V<VDD <3.6 V	0	-	ns

Table 79 · 7 columns × 11 rows · p.258–258 · CSV

Symbol	Parameter	Conditions	Min	Max(2)	Unit
-	Frequency ratio PSSI_PDCK/fHCLK	-	-	0.4	-	-
PSSI_PDCK	PSSI Clock input	1.71 V<VDD <3.6 V	-	100	MHz	MHz
Dpixel	PSSI Clock input duty cycle	-	30	70	%	%
tsu (DATA)	Data input setup time	1.71 V<VDD <3.6 V	1	-	ns	ns
th (DATA)	Data input hold time	1.71 V<VDD <3.6 V	1.5	-	ns	ns
tsu( (DE)	DE input setup time	1.71 V<VDD <3.6 V	1	-	ns	ns
th (DE)	DE input hold time	1.71 V<VDD <3.6 V	1.5	-	ns	ns
tov(RDY)	RDY output valid time	1.71 V<VDD <3.6 V	-	11.5	ns	ns
toh(RDY)	RDY output hold time	1.71 V<VDD <3.6 V	5.5	-	ns	ns
1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 57. PSSI receive timing diagram tc(PDCK) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) PSSI_PDCK (input) CKPOL=0 CKPOL=1 ts(DATA) th(DATA) PSSI D[15:0] (input) Invalid data IN Valid data IN Invalid data IN ts(DE) th(DE) PSSI_DE (input) DEPOL=0 DEPOL=1 tv(RDY) tho(RDY) PSSI_RDY (output) RDYPOL=0 RDYPOL=1 MSv63436V1	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 57. PSSI receive timing diagram tc(PDCK) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) PSSI_PDCK (input) CKPOL=0 CKPOL=1 ts(DATA) th(DATA) PSSI D[15:0] (input) Invalid data IN Valid data IN Invalid data IN ts(DE) th(DE) PSSI_DE (input) DEPOL=0 DEPOL=1 tv(RDY) tho(RDY) PSSI_RDY (output) RDYPOL=0 RDYPOL=1 MSv63436V1	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 57. PSSI receive timing diagram tc(PDCK) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) PSSI_PDCK (input) CKPOL=0 CKPOL=1 ts(DATA) th(DATA) PSSI D[15:0] (input) Invalid data IN Valid data IN Invalid data IN ts(DE) th(DE) PSSI_DE (input) DEPOL=0 DEPOL=1 tv(RDY) tho(RDY) PSSI_RDY (output) RDYPOL=0 RDYPOL=1 MSv63436V1	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 57. PSSI receive timing diagram tc(PDCK) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) PSSI_PDCK (input) CKPOL=0 CKPOL=1 ts(DATA) th(DATA) PSSI D[15:0] (input) Invalid data IN Valid data IN Invalid data IN ts(DE) th(DE) PSSI_DE (input) DEPOL=0 DEPOL=1 tv(RDY) tho(RDY) PSSI_RDY (output) RDYPOL=0 RDYPOL=1 MSv63436V1	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 57. PSSI receive timing diagram tc(PDCK) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) PSSI_PDCK (input) CKPOL=0 CKPOL=1 ts(DATA) th(DATA) PSSI D[15:0] (input) Invalid data IN Valid data IN Invalid data IN ts(DE) th(DE) PSSI_DE (input) DEPOL=0 DEPOL=1 tv(RDY) tho(RDY) PSSI_RDY (output) RDYPOL=0 RDYPOL=1 MSv63436V1	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 57. PSSI receive timing diagram tc(PDCK) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) PSSI_PDCK (input) CKPOL=0 CKPOL=1 ts(DATA) th(DATA) PSSI D[15:0] (input) Invalid data IN Valid data IN Invalid data IN ts(DE) th(DE) PSSI_DE (input) DEPOL=0 DEPOL=1 tv(RDY) tho(RDY) PSSI_RDY (output) RDYPOL=0 RDYPOL=1 MSv63436V1	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 57. PSSI receive timing diagram tc(PDCK) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) PSSI_PDCK (input) CKPOL=0 CKPOL=1 ts(DATA) th(DATA) PSSI D[15:0] (input) Invalid data IN Valid data IN Invalid data IN ts(DE) th(DE) PSSI_DE (input) DEPOL=0 DEPOL=1 tv(RDY) tho(RDY) PSSI_RDY (output) RDYPOL=0 RDYPOL=1 MSv63436V1
1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 57. PSSI receive timing diagram tc(PDCK) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) PSSI_PDCK (input) CKPOL=0 CKPOL=1 ts(DATA) th(DATA) PSSI D[15:0] (input) Invalid data IN Valid data IN Invalid data IN ts(DE) th(DE) PSSI_DE (input) DEPOL=0 DEPOL=1 tv(RDY) tho(RDY) PSSI_RDY (output) RDYPOL=0 RDYPOL=1 MSv63436V1	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 57. PSSI receive timing diagram tc(PDCK) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) PSSI_PDCK (input) CKPOL=0 CKPOL=1 ts(DATA) th(DATA) PSSI D[15:0] (input) Invalid data IN Valid data IN Invalid data IN ts(DE) th(DE) PSSI_DE (input) DEPOL=0 DEPOL=1 tv(RDY) tho(RDY) PSSI_RDY (output) RDYPOL=0 RDYPOL=1 MSv63436V1	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 57. PSSI receive timing diagram tc(PDCK) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) PSSI_PDCK (input) CKPOL=0 CKPOL=1 ts(DATA) th(DATA) PSSI D[15:0] (input) Invalid data IN Valid data IN Invalid data IN ts(DE) th(DE) PSSI_DE (input) DEPOL=0 DEPOL=1 tv(RDY) tho(RDY) PSSI_RDY (output) RDYPOL=0 RDYPOL=1 MSv63436V1	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 57. PSSI receive timing diagram tc(PDCK) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) PSSI_PDCK (input) CKPOL=0 CKPOL=1 ts(DATA) th(DATA) PSSI D[15:0] (input) Invalid data IN Valid data IN Invalid data IN ts(DE) th(DE) PSSI_DE (input) DEPOL=0 DEPOL=1 tv(RDY) tho(RDY) PSSI_RDY (output) RDYPOL=0 RDYPOL=1 MSv63436V1	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 57. PSSI receive timing diagram tc(PDCK) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) PSSI_PDCK (input) CKPOL=0 CKPOL=1 ts(DATA) th(DATA) PSSI D[15:0] (input) Invalid data IN Valid data IN Invalid data IN ts(DE) th(DE) PSSI_DE (input) DEPOL=0 DEPOL=1 tv(RDY) tho(RDY) PSSI_RDY (output) RDYPOL=0 RDYPOL=1 MSv63436V1	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 57. PSSI receive timing diagram tc(PDCK) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) PSSI_PDCK (input) CKPOL=0 CKPOL=1 ts(DATA) th(DATA) PSSI D[15:0] (input) Invalid data IN Valid data IN Invalid data IN ts(DE) th(DE) PSSI_DE (input) DEPOL=0 DEPOL=1 tv(RDY) tho(RDY) PSSI_RDY (output) RDYPOL=0 RDYPOL=1 MSv63436V1	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 57. PSSI receive timing diagram tc(PDCK) tw(PDCKH) tw(PDCKL) tf(PDCK) tr(PDCK) PSSI_PDCK (input) CKPOL=0 CKPOL=1 ts(DATA) th(DATA) PSSI D[15:0] (input) Invalid data IN Valid data IN Invalid data IN ts(DE) th(DE) PSSI_DE (input) DEPOL=0 DEPOL=1 tv(RDY) tho(RDY) PSSI_RDY (output) RDYPOL=0 RDYPOL=1 MSv63436V1

Table 80 (pages 260–260)

Table 80 · 6 columns × 7 rows · p.260–260 · CSV

Symbol	Parameter		Min	Max(2)	Unit
fCLK	LTDC clock output frequency	1.71<VD D <3. 6 V, 30 pF	-	90	MHz
DCLK	LTDC clock output duty cycle	LTDC clock output duty cycle	45	55	%
tw(CLKH), tw(CLKL)	Clock High time, low time	Clock High time, low time	tw(CLK) //2-0.5	tw(CLK) /2+0.5	ns
tv(DATA)	Data output valid time	Data output valid time	-	3.5	ns
th(DATA)	Data output hold time	Data output hold time	0.5	-	ns
tv(HSYNC), tv(VSYNC), tv(DE)	HSYNC/VSYNC/DE output valid time	HSYNC/VSYNC/DE output valid time	-	3.0	ns
th(HSYNC), th(VSYNC) , th(DE)	HSYNC/VSYNC/DE output hold time	HSYNC/VSYNC/DE output hold time	0.5	-	ns

Table 81 (pages 262–262)

Table 81 · 7 columns × 12 rows · p.262–262 · CSV

Symbol	Parameter	Conditions(3)		Min	Max	Unit
tres(TIM)	Timer resolution time	AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 300 MHz	AHB/APBx prescaler=1 or 2 or 4, fTIMxCLK = 300 MHz	1	-	tTIMxCLK
tres(TIM)	Timer resolution time	AHB/APBx prescaler>4, fTIMxCLK =150 MHz	AHB/APBx prescaler>4, fTIMxCLK =150 MHz	1	-	tTIMxCLK
fEXT	Timer external clock frequency on CH1 to CH4	fTIMxCLK = 240 MHz	fTIMxCLK = 240 MHz	0	fTIMxCLK /2	MHz
ResTIM	Timer resolution	fTIMxCLK = 240 MHz	fTIMxCLK = 240 MHz	-	16/32	bit
tMAX_COUNT	Maximum possible count with 32-bit counter	-	-	-	65536 ×65536	tTIMxCLK
1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 300 MHz, by setting the TIMPRE bit in the RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x Frcc_pclkx1 or TIMxCLK = 4x Frcc_pclkx2 . Low-power timer characteristics The parameters given in Table 119 are guaranteed by design. Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 119. LPTIMx characteristics(1)(2)	1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 300 MHz, by setting the TIMPRE bit in the RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x Frcc_pclkx1 or TIMxCLK = 4x Frcc_pclkx2 . Low-power timer characteristics The parameters given in Table 119 are guaranteed by design. Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 119. LPTIMx characteristics(1)(2)	1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 300 MHz, by setting the TIMPRE bit in the RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x Frcc_pclkx1 or TIMxCLK = 4x Frcc_pclkx2 . Low-power timer characteristics The parameters given in Table 119 are guaranteed by design. Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 119. LPTIMx characteristics(1)(2)	1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 300 MHz, by setting the TIMPRE bit in the RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x Frcc_pclkx1 or TIMxCLK = 4x Frcc_pclkx2 . Low-power timer characteristics The parameters given in Table 119 are guaranteed by design. Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 119. LPTIMx characteristics(1)(2)	1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 300 MHz, by setting the TIMPRE bit in the RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x Frcc_pclkx1 or TIMxCLK = 4x Frcc_pclkx2 . Low-power timer characteristics The parameters given in Table 119 are guaranteed by design. Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 119. LPTIMx characteristics(1)(2)	1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 300 MHz, by setting the TIMPRE bit in the RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x Frcc_pclkx1 or TIMxCLK = 4x Frcc_pclkx2 . Low-power timer characteristics The parameters given in Table 119 are guaranteed by design. Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 119. LPTIMx characteristics(1)(2)	1. TIMx is used as a general term to refer to the TIM1 to TIM17 timers. 2. Guaranteed by design. 3. The maximum timer frequency on APB1 or APB2 is up to 300 MHz, by setting the TIMPRE bit in the RCC_CFGR register, if APBx prescaler is 1 or 2 or 4, then TIMxCLK = rcc_hclk1, otherwise TIMxCLK = 4x Frcc_pclkx1 or TIMxCLK = 4x Frcc_pclkx2 . Low-power timer characteristics The parameters given in Table 119 are guaranteed by design. Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 119. LPTIMx characteristics(1)(2)
Symbol	Parameter	Parameter	Min	Min	Max	Unit
tres(TIM)	Timer resolution time	Timer resolution time	1	1	-	tTIMxCLK
fLPTIMxCLK	Timer kernel clock	Timer kernel clock	0	0	150	MHz
fEXT	Timer external clock frequency on Input1 and Input2	Timer external clock frequency on Input1 and Input2	0	0	fLPTIMxCLK /2	MHz
ResTIM	Timer resolution	Timer resolution	-	-	16	bit
tMAX_COUNT	Maximum possible count	Maximum possible count	-	-	65536	tTIMxCLK

Table 82 (pages 263–263)

Table 82 · 7 columns × 5 rows · p.263–263 · CSV

Symbol	Parameter	Conditions	I3C open drain mode (specification)		Timing measurements	Unit
Symbol	Parameter	Conditions	Min	Max	Timing measurements	Unit
tSU_OD	SDA data setup time during open drain mode	Controller 1.71 V < VDD < 3.6 V	3	-	16	ns
1. Guaranteed by characterization results. Table 121. I3 C push-pull measured timing(1)	1. Guaranteed by characterization results. Table 121. I3 C push-pull measured timing(1)	1. Guaranteed by characterization results. Table 121. I3 C push-pull measured timing(1)	1. Guaranteed by characterization results. Table 121. I3 C push-pull measured timing(1)	1. Guaranteed by characterization results. Table 121. I3 C push-pull measured timing(1)	1. Guaranteed by characterization results. Table 121. I3 C push-pull measured timing(1)	1. Guaranteed by characterization results. Table 121. I3 C push-pull measured timing(1)
Symbol	Parameter	Conditions	I3C open drain mode (specification)	I3C open drain mode (specification)	Timing measurements	Unit
Symbol	Parameter	Conditions	Min	Max	Timing measurements	Unit
tSU_PP	SDA signal data setup in push-pull mode	Controller 1.71 V < VDD < 3.6 V	3	-	14.5	ns

Table 83 (pages 265–265)

Table 83 · 7 columns × 16 rows · p.265–265 · CSV

Symbol	Parameter	Conditions	Min	Typ	Max(2)	Unit
fCK	USART clock frequency	Master mode, 1.71 V ≤ VDD ≤ 3.6 V	-	-	15.5	MHz
fCK	USART clock frequency	Slave receiver mode, 1.71 V ≤ VDD ≤ 3.6 V	-	-	41.5	MHz
fCK	USART clock frequency	Slave transmitter mode, 1.71 V ≤ VDD ≤ 3.6 V	-	-	40.0	MHz
fCK	USART clock frequency	Slave transmitter mode, 2.7 V ≤ VDD ≤ 3.6 V	-	-	41.5	MHz
tsu(NSS)	NSS setup time	Slave mode	tker +2	-	-	ns
th(NSS)	NSS hold time	Slave mode	0.5	-	-	ns
tw(CKH) , tw(CKL)	CK high and low time	Master mode	1/fCK /2-1	1/fCK /2	1/fCK /2+1	ns
tsu(RX)	Data input setup time	Master mode	11.5	-	-	ns
tsu(RX)	Data input setup time	Slave mode	1.5	-	-	ns
th(RX)	Data input hold time	Master mode	0	-	-	ns
th(RX)	Data input hold time	Slave mode	0.5	-	-	ns
tv(TX)	Data output valid time	Slave mode, , 2.7 V ≤ VDD ≤ 3.6 V	-	8.0	10.5	ns
tv(TX)	Data output valid time	Slave mode, , 1.71 V ≤ VDD ≤ 3.6 V	-	8.0	12.5	ns
tv(TX)	Data output valid time	Master mode	-	1	2	ns
th(TX)	Data output hold time	Slave mode	6	-	-	ns
th(TX)	Data output hold time	Master mode	0.5	-	-	ns

Table 84 (pages 267–267)

Table 84 · 7 columns × 10 rows · p.267–267 · CSV

Symbol	Parameter	Conditions	Min	Typ	Max(2)	Unit
fSCK	SPI clock frequency	Master mode, 1.71 V < VDD < 3.6 V	-	-	90	MHz
fSCK	SPI clock frequency	Master mode, 2.7 V < VDD < 3.6 V, SPI2, 3, 4, 5, 6	-	-	133	MHz
fSCK	SPI clock frequency	Master mode, 2.7 V < VDD < 3.6 V, SPI1	-	-	130	MHz
fSCK	SPI clock frequency	Slave receiver mode, 2.7 V < VDD < 3.6 V, SPI2, 3, 4, 5, 6	-	-	140	MHz
fSCK	SPI clock frequency	Slave receiver mode, 1.71 V < VDD < 3.6 V, SPI1	-	-	130	MHz
fSCK	SPI clock frequency	Slave mode transmitter/full duplex, 2.7 V < VDD < 3.6 V	-	-	45	MHz
fSCK	SPI clock frequency	Slave mode transmitter/full duplex, 1.71 V < VDD < 3.6 V	-	-	38	MHz
tsu(NSS)	NSS setup time	Slave mode	2.5	-	-	ns
th(NSS)	NSS hold time	Slave mode	1	-	-	ns
tw(SCKH) , tw(SCKL)	SCK high and low time	Master mode, prescaler = 2	tSCK -1	tSCK	tSCK +1	ns

Table 85 (pages 268–268)

Table 85 · 9 columns × 15 rows · p.268–268 · CSV

Symbol	Parameter		Conditions		Min	Typ	Max(2)	Unit
tsu(MI)	Data input setup time	Data input setup time	Master mode	Master mode	1.5	-	-	ns
tsu(SI)	Data input setup time	Data input setup time	Slave mode	Slave mode	2	-	-	ns
th(MI)	Data input hold time	Data input hold time	Master mode	Master mode	1.5	-	-	ns
th(SI)	Data input hold time	Data input hold time	Slave mode	Slave mode	1.5	-	-	ns
ta(SO)	Data output access time	Data output access time	Slave mode	Slave mode	10	11.5	15.5	ns
tdis(SO)	Data output disable time	Data output disable time	Slave mode	Slave mode	7.5	8	12	ns
tv(SO)	Data output valid time	Data output valid time	Slave mode, 2.7 V < VDD < 3.6 V	Slave mode, 2.7 V < VDD < 3.6 V	-	9	11	ns
tv(SO)	Data output valid time	Data output valid time	Slave mode, 1.71 V < VDD < 3.6 V	Slave mode, 1.71 V < VDD < 3.6 V	-	9	13	ns
tv(MO)	Data output valid time	Data output valid time	Master mode, 1.71 V < VDD < 3.6 V	Master mode, 1.71 V < VDD < 3.6 V	-	0.5	1	ns
th(SO)	Data output hold time	Data output hold time	Slave mode	Slave mode	6.5	-	-	ns
th(MO)	Data output hold time	Data output hold time	Master mode	Master mode	0	-	-	ns
1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 63. SPI timing diagram -slave mode and CPHA = 0	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 63. SPI timing diagram -slave mode and CPHA = 0	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 63. SPI timing diagram -slave mode and CPHA = 0	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 63. SPI timing diagram -slave mode and CPHA = 0	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 63. SPI timing diagram -slave mode and CPHA = 0	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 63. SPI timing diagram -slave mode and CPHA = 0	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 63. SPI timing diagram -slave mode and CPHA = 0	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 63. SPI timing diagram -slave mode and CPHA = 0	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 63. SPI timing diagram -slave mode and CPHA = 0
NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2
NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2
NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2	NSS input tc(SCK) th(NSS) tsu(NSS) tw(SCKH) CPHA=0 input CPOL=0 SCK CPHA=0 CPOL=1 ta(SO) tw(SCKL) tv(SO) th(SO) tdis(SO) MISO output First bit OUT Next bits OUT Last bit OUT tsu(SI) th(SI) MOSI input First bit IN Next bits IN Last bit IN MSv41658V2

Table 86 (pages 270–272)

Table 86 · 6 columns × 35 rows · p.270–272 · CSV

Symbol	Parameter	Conditions	Min	Max(2)	Unit
fMCK	I2 S main clock output	-	-	50	MHz
fMCK	I2 S main clock output	Master transmitter	-	50	MHz
fMCK	I2 S main clock output	Master receiver	-	28	MHz
fMCK	I2 S main clock output	Slave transmitter	-	23	MHz
fMCK	I2 S main clock output	Slave receiver	-	50	MHz
tv(WS)	WS valid time	Master mode	-	1.5	ns
th(WS)	WS hold time	Master mode	0.5	-	ns
tsu(WS)	WS setup time	Slave mode	3	-	ns
th(WS)	WS hold time	Slave mode	1	-	ns
tsu(SD_MR)	Data input setup time	Master receiver	1.5	-	ns
tsu(SD_SR)	Data input setup time	Slave receiver	1.5	-	ns
th(SD_MR)	Data input hold time	Master receiver	2	-	ns
th(SD_SR)	Data input hold time	Slave receiver	1	-	ns
tv(SD_ST)	Data output valid time	Slave transmitter (after enable edge)	-	13	ns
tv(SD_MT)	Data output valid time	Master transmitter (after enable edge)	-	2	ns
th(SD_ST)	Data output hold time	Slave transmitter (after enable edge)	7.5	-	ns
th(SD_MT)	Data output hold time	Master transmitter (after enable edge)	0.5	-	ns
fMCK	SAI Main clock output	-	-	50	MHz
fCK	SAI clock frequency(3)	Master transmitter	-	34	MHz
fCK	SAI clock frequency(3)	Master receiver	-	38	MHz
fCK	SAI clock frequency(3)	Slave transmitter	-	35	MHz
fCK	SAI clock frequency(3)	Slave receiver	-	50	MHz
tv(FS)	FS valid time	Master mode, 2.7 V ≤ VDD ≤ 3.6 V	-	12	ns
tv(FS)	FS valid time	Master mode, 1.71 V ≤ VDD ≤ 3.6 V	-	13	ns
tsu(FS)	FS setup time	Slave mode	3	-	ns
th(FS)	FS hold time	Master mode	7	-	ns
th(FS)	FS hold time	Slave mode	1	-	ns
tsu(SD_A_MR)	Data input setup time	Master receiver	2.5	-	ns
tsu(SD_B_SR)	Data input setup time	Slave receiver	1.5	-	ns
th(SD_A_MR)	Data input hold time	Master receiver	2	-	ns
th(SD_B_SR)	Data input hold time	Slave receiver	1	-	ns
tv(SD_B_ST)	Data output valid time	Slave transmitter (after enable edge)	-	14	ns
th(SD_B_ST)	Data output hold time	Slave transmitter (after enable edge)	7.5	-	ns
tv(SD_A_MT)	Data output valid time	Master transmitter (after enable edge)	-	14.5	ns
th(SD_A_MT)	Data output hold time	Master transmitter (after enable edge)	7	-	ns

Table 87 (pages 274–274)

Table 87 · 6 columns × 6 rows · p.274–274 · CSV

Symbol	Parameter	Min	Typ	Max(2)	Unit
FMDC	Management Data Clock	-	-	30	MHz
td(MDIO)	Management Data Iput/output output valid time	6	8.5	13	ns
tsu(MDIO)	Management Data Iput/output setup time	2.5	-	-	ns
th(MDIO)	Management Data Iput/output hold time	0.5	-	-	ns
1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 70. MDIO slave timing diagram	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 70. MDIO slave timing diagram	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 70. MDIO slave timing diagram	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 70. MDIO slave timing diagram	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 70. MDIO slave timing diagram	1. Guaranteed by characterization results. 2. At VOS Low, these values are degraded by up to 7%. Figure 70. MDIO slave timing diagram
tMDC) td(MDIO) tsu(MDIO) th(MDIO) MSv40460V1	tMDC) td(MDIO) tsu(MDIO) th(MDIO) MSv40460V1	tMDC) td(MDIO) tsu(MDIO) th(MDIO) MSv40460V1	tMDC) td(MDIO) tsu(MDIO) th(MDIO) MSv40460V1	tMDC) td(MDIO) tsu(MDIO) th(MDIO) MSv40460V1	tMDC) td(MDIO) tsu(MDIO) th(MDIO) MSv40460V1

Table 88 (pages 275–276)

Table 88 · 7 columns × 29 rows · p.275–276 · CSV

Symbol	Parameter	Conditions	Min	Typ	Max(2)	Unit
fPP	Clock frequency in data transfer mode	-	0	-	120(3)	MHz
tW(CKL)	Clock low time	fPP =52MHz	8.5	9.5	-	ns
tW(CKH)	Clock high time	fPP =52MHz	8.5	9.5	-	ns
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4) /DDR(4) mode	CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4) /DDR(4) mode	CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4) /DDR(4) mode	CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4) /DDR(4) mode	CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4) /DDR(4) mode	CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4) /DDR(4) mode	CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(4) /DDR(4) mode
tISU	Input setup time HS	-	2.5	-	-	ns
tIH	Input hold time HS	-	1.5	-	-	ns
tIDW (4)	Input valid window (variable window)	-	3.5	-	-	ns
CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(5) /DDR(5) mode	CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(5) /DDR(5) mode	CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(5) /DDR(5) mode	CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(5) /DDR(5) mode	CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(5) /DDR(5) mode	CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(5) /DDR(5) mode	CMD, D outputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR(5) /DDR(5) mode
tOV	Output valid time HS	-	-	6	6.5	ns
tOH	Output hold time HS	-	4	-	-	ns
CMD, D inputs (referenced to CK) in SD default mode	CMD, D inputs (referenced to CK) in SD default mode	CMD, D inputs (referenced to CK) in SD default mode	CMD, D inputs (referenced to CK) in SD default mode	CMD, D inputs (referenced to CK) in SD default mode	CMD, D inputs (referenced to CK) in SD default mode	CMD, D inputs (referenced to CK) in SD default mode
tISUD	Input setup time SD	-	2.5		-	ns
tIHD	Input hold time SD	-	1.5		-	ns
CMD, D outputs (referenced to CK) in SD default mode	CMD, D outputs (referenced to CK) in SD default mode	CMD, D outputs (referenced to CK) in SD default mode	CMD, D outputs (referenced to CK) in SD default mode	CMD, D outputs (referenced to CK) in SD default mode	CMD, D outputs (referenced to CK) in SD default mode	CMD, D outputs (referenced to CK) in SD default mode
tOVD	Output valid default time SD	-	-	1	1.5	ns
tOHD	Output hold default time SD	-	0	-	-	ns
fPP	Clock frequency in data transfer mode	-	-	-	130(3)	MHz
tW(CKL)	Clock low time	fPP =52 MHz	8.5	9.5	-	ns
tW(CKH)	Clock high time	fPP =52 MHz	8.5	9.5	-	ns
CMD, D inputs (referenced to CK) in eMMC mode	CMD, D inputs (referenced to CK) in eMMC mode	CMD, D inputs (referenced to CK) in eMMC mode	CMD, D inputs (referenced to CK) in eMMC mode	CMD, D inputs (referenced to CK) in eMMC mode	CMD, D inputs (referenced to CK) in eMMC mode	CMD, D inputs (referenced to CK) in eMMC mode
tISU	Input setup time HS	-	2	-	-	ns
tIH	Input hold time HS	-	1.5	-	-	ns
t IDW(4)	Input valid window (variable window)	-	3	-	-	ns
CMD, D outputs (referenced to CK) in eMMC mode	CMD, D outputs (referenced to CK) in eMMC mode	CMD, D outputs (referenced to CK) in eMMC mode	CMD, D outputs (referenced to CK) in eMMC mode	CMD, D outputs (referenced to CK) in eMMC mode	CMD, D outputs (referenced to CK) in eMMC mode	CMD, D outputs (referenced to CK) in eMMC mode
tOVD	Output valid time HS	-	-	6	6.5	ns
tOHD	Output hold time HS	-	4	-	-	ns
1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. 3. CL = 20 pF. 4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. Figure 71. SD high-speed mode	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. 3. CL = 20 pF. 4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. Figure 71. SD high-speed mode	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. 3. CL = 20 pF. 4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. Figure 71. SD high-speed mode	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. 3. CL = 20 pF. 4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. Figure 71. SD high-speed mode	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. 3. CL = 20 pF. 4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. Figure 71. SD high-speed mode	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. 3. CL = 20 pF. 4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. Figure 71. SD high-speed mode	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. 3. CL = 20 pF. 4. The minimum window of time where the data needs to be stable for proper sampling in tuning mode. Figure 71. SD high-speed mode
Figure 72. SD default mode	Figure 72. SD default mode	Figure 72. SD default mode	Figure 72. SD default mode	Figure 72. SD default mode	Figure 72. SD default mode	Figure 72. SD default mode
CK tOVD tOHD D, CMD (output) ai14888	CK tOVD tOHD D, CMD (output) ai14888	CK tOVD tOHD D, CMD (output) ai14888	CK tOVD tOHD D, CMD (output) ai14888	CK tOVD tOHD D, CMD (output) ai14888	CK tOVD tOHD D, CMD (output) ai14888	CK tOVD tOHD D, CMD (output) ai14888

Table 89 (pages 278–278)

Table 89 · 7 columns × 9 rows · p.278–278 · CSV

Symbol	Parameter	Condition	Min	Typ	Max	Unit
VDDUSB	USB transceiver operating voltage	-	3.12(2)	-	3.6	V
fHCLK	fHCLK value to guarantee proper operation of the OTG_HS interface	-	30(3)	-	-	MHz
RPUI	Embedded USB_DP pull-up value during idle	-	900	1250	1575	Ω
RPUR	Embedded USB_DP pull-up value during reception	-	1425(3)	2250	3090(3)	Ω
RPD	Embedded USB_DP and USB_DM pull-down value	-	14250	-	24800	Ω
ZDRV	Output driver impedance(4)	Driving high or low	40.5(3)	45	49.5(3)	Ω
tlr	Rise time	CL < 5 pF	0.5(3)	-	-	ns
tlf	Fall time	CL < 5 pF	0.5(3)	-	-	ns
tlrfm	Rise/fall time matching	-	80(3)	-	125(3)	%

Table 90 (pages 279–279)

Table 90 · 12 columns × 9 rows · p.279–279 · CSV

Symbol		Parameter		Condition			Min	Typ	Max		Unit
IDD(OTG_HS)	IDD(OTG_HS)	USB (PLL and PHY) current consumption at V DDUSB(2)	USB (PLL and PHY) current consumption at V DDUSB(2)	Full Speed Transmit(3)	Full Speed Transmit(3)	Full Speed Transmit(3)	-	5.65	6.02	6.02	mA
IDD(OTG_HS)	IDD(OTG_HS)	USB (PLL and PHY) current consumption at V DDUSB(2)	USB (PLL and PHY) current consumption at V DDUSB(2)	High Speed Idle(3)	High Speed Idle(3)	High Speed Idle(3)	-	5.66	6.00	6.00	mA
IDD(OTG_HS)	IDD(OTG_HS)	USB (PLL and PHY) current consumption at V DDUSB(2)	USB (PLL and PHY) current consumption at V DDUSB(2)	High Speed Transmit(3)	High Speed Transmit(3)	High Speed Transmit(3)	-	14.6	14.92	14.92	mA
IDD_DVDD(OTG_HS)	IDD_DVDD(OTG_HS)	USB (PLL and PHY) current consumption at D VDD(4)	USB (PLL and PHY) current consumption at D VDD(4)	Full Speed Transmit(3)	Full Speed Transmit(3)	Full Speed Transmit(3)	-	6.00	10.59	10.59	mA
IDD_DVDD(OTG_HS)	IDD_DVDD(OTG_HS)	USB (PLL and PHY) current consumption at D VDD(4)	USB (PLL and PHY) current consumption at D VDD(4)	High Speed Idle(3)	High Speed Idle(3)	High Speed Idle(3)	-	5.93	10.51	10.51	mA
IDD_DVDD(OTG_HS)	IDD_DVDD(OTG_HS)	USB (PLL and PHY) current consumption at D VDD(4)	USB (PLL and PHY) current consumption at D VDD(4)	High Speed Transmit(3)	High Speed Transmit(3)	High Speed Transmit(3)	-	6.87	11.98	11.98	mA
1. Evaluated by characterization. Not tested in production. 2. Measured on VDD33USB. See Table 131: USB OTG_HS DC electrical characteristics. 3. Suspend when operating in Device mode with no far-side host termination on DP/DM during measurements. 4. Measured on DVDD. See Table 24: General operating conditions. UCPD characteristics The UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0 specifications. Table 133. UCPD electrical characteristics	1. Evaluated by characterization. Not tested in production. 2. Measured on VDD33USB. See Table 131: USB OTG_HS DC electrical characteristics. 3. Suspend when operating in Device mode with no far-side host termination on DP/DM during measurements. 4. Measured on DVDD. See Table 24: General operating conditions. UCPD characteristics The UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0 specifications. Table 133. UCPD electrical characteristics	1. Evaluated by characterization. Not tested in production. 2. Measured on VDD33USB. See Table 131: USB OTG_HS DC electrical characteristics. 3. Suspend when operating in Device mode with no far-side host termination on DP/DM during measurements. 4. Measured on DVDD. See Table 24: General operating conditions. UCPD characteristics The UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0 specifications. Table 133. UCPD electrical characteristics	1. Evaluated by characterization. Not tested in production. 2. Measured on VDD33USB. See Table 131: USB OTG_HS DC electrical characteristics. 3. Suspend when operating in Device mode with no far-side host termination on DP/DM during measurements. 4. Measured on DVDD. See Table 24: General operating conditions. UCPD characteristics The UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0 specifications. Table 133. UCPD electrical characteristics	1. Evaluated by characterization. Not tested in production. 2. Measured on VDD33USB. See Table 131: USB OTG_HS DC electrical characteristics. 3. Suspend when operating in Device mode with no far-side host termination on DP/DM during measurements. 4. Measured on DVDD. See Table 24: General operating conditions. UCPD characteristics The UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0 specifications. Table 133. UCPD electrical characteristics	1. Evaluated by characterization. Not tested in production. 2. Measured on VDD33USB. See Table 131: USB OTG_HS DC electrical characteristics. 3. Suspend when operating in Device mode with no far-side host termination on DP/DM during measurements. 4. Measured on DVDD. See Table 24: General operating conditions. UCPD characteristics The UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0 specifications. Table 133. UCPD electrical characteristics	1. Evaluated by characterization. Not tested in production. 2. Measured on VDD33USB. See Table 131: USB OTG_HS DC electrical characteristics. 3. Suspend when operating in Device mode with no far-side host termination on DP/DM during measurements. 4. Measured on DVDD. See Table 24: General operating conditions. UCPD characteristics The UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0 specifications. Table 133. UCPD electrical characteristics	1. Evaluated by characterization. Not tested in production. 2. Measured on VDD33USB. See Table 131: USB OTG_HS DC electrical characteristics. 3. Suspend when operating in Device mode with no far-side host termination on DP/DM during measurements. 4. Measured on DVDD. See Table 24: General operating conditions. UCPD characteristics The UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0 specifications. Table 133. UCPD electrical characteristics	1. Evaluated by characterization. Not tested in production. 2. Measured on VDD33USB. See Table 131: USB OTG_HS DC electrical characteristics. 3. Suspend when operating in Device mode with no far-side host termination on DP/DM during measurements. 4. Measured on DVDD. See Table 24: General operating conditions. UCPD characteristics The UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0 specifications. Table 133. UCPD electrical characteristics	1. Evaluated by characterization. Not tested in production. 2. Measured on VDD33USB. See Table 131: USB OTG_HS DC electrical characteristics. 3. Suspend when operating in Device mode with no far-side host termination on DP/DM during measurements. 4. Measured on DVDD. See Table 24: General operating conditions. UCPD characteristics The UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0 specifications. Table 133. UCPD electrical characteristics	1. Evaluated by characterization. Not tested in production. 2. Measured on VDD33USB. See Table 131: USB OTG_HS DC electrical characteristics. 3. Suspend when operating in Device mode with no far-side host termination on DP/DM during measurements. 4. Measured on DVDD. See Table 24: General operating conditions. UCPD characteristics The UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0 specifications. Table 133. UCPD electrical characteristics	1. Evaluated by characterization. Not tested in production. 2. Measured on VDD33USB. See Table 131: USB OTG_HS DC electrical characteristics. 3. Suspend when operating in Device mode with no far-side host termination on DP/DM during measurements. 4. Measured on DVDD. See Table 24: General operating conditions. UCPD characteristics The UCPD controller complies with USB Type-C Rev 1.2 and USB Power Delivery Rev 3.0 specifications. Table 133. UCPD electrical characteristics
Symbol	Parameter	Parameter	Condition	Condition	Min	Typ	Typ	Max	Max	Unit	Unit
VDD33USB	UCPD operating supply voltage	UCPD operating supply voltage	-	-	3.0	3.3	3.3	3.6	3.6	V	V

Table 91 (pages 281–281)

Table 91 · 7 columns × 18 rows · p.281–281 · CSV

Symbol	Parameter	Min		Typ	Max(2)	Unit
tsu(RXD)	Receive data setup time	2.5	2.5	-	-	ns
tih(RXD)	Receive data hold time	1	1	-	-	ns
tsu(CRS)	Carrier sense setup time	1.5	1.5	-	-	ns
tih(CRS)	Carrier sense hold time	0.5	0.5	-	-	ns
td(TXEN)	Transmit enable valid delay time	7	7	9.5	14	ns
td(TXD)	Transmit data valid delay time	7	7	10.5	14.5	ns
1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 75. Ethernet RMII timing diagram	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 75. Ethernet RMII timing diagram	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 75. Ethernet RMII timing diagram	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 75. Ethernet RMII timing diagram	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 75. Ethernet RMII timing diagram	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 75. Ethernet RMII timing diagram	1. Guaranteed by characterization results. 2. At VOS low, these values are degraded by up to 7%. Figure 75. Ethernet RMII timing diagram
RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tih(RXD) tsu(CRS) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667b	RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tih(RXD) tsu(CRS) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667b	RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tih(RXD) tsu(CRS) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667b	RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tih(RXD) tsu(CRS) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667b	RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tih(RXD) tsu(CRS) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667b	RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tih(RXD) tsu(CRS) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667b	RMII_REF_CLK td(TXEN) td(TXD) RMII_TX_EN RMII_TXD[1:0] tsu(RXD) tih(RXD) tsu(CRS) tih(CRS) RMII_RXD[1:0] RMII_CRS_DV ai15667b
Table 136. Dynamic characteristics: Ethernet MAC signals for MII(1)	Table 136. Dynamic characteristics: Ethernet MAC signals for MII(1)	Table 136. Dynamic characteristics: Ethernet MAC signals for MII(1)	Table 136. Dynamic characteristics: Ethernet MAC signals for MII(1)	Table 136. Dynamic characteristics: Ethernet MAC signals for MII(1)	Table 136. Dynamic characteristics: Ethernet MAC signals for MII(1)	Table 136. Dynamic characteristics: Ethernet MAC signals for MII(1)
Symbol	Parameter	Parameter	Min	Typ	Max(2)	Unit
tsu(RXD)	Receive data setup time	Receive data setup time	2.5	-	-	ns
tih(RXD)	Receive data hold time	Receive data hold time	1	-	-	ns
tsu(DV)	Data valid setup time	Data valid setup time	1	-	-	ns
tih(DV)	Data valid hold time	Data valid hold time	0.5	-	-	ns
tsu(ER)	Error setup time	Error setup time	2	-	-	ns
tih(ER)	Error hold time	Error hold time	0.5	-	-	ns
td(TXEN)	Transmit enable valid delay time	Transmit enable valid delay time	6.5	9	13	ns
td(TXD)	Transmit data valid delay time	Transmit data valid delay time	6.5	10	14.5	ns

Table 92 (pages 282–282)

Table 92 · 7 columns × 9 rows · p.282–282 · CSV

MII_RX_CLK tsu(RXD) tih(RXD) tsu(ER) tih(ER) tsu(DV) tih(DV) MII_RXD[3:0] MII_RX_DV MII_RX_ER MII_TX_CLK td(TXEN) td(TXD) MII_TX_EN MII_TXD[3:0] ai15668b
JTAG/SWD interface characteristics Unless otherwise specified, the parameters given in Table 137 and Table 138 for JTAG/SWD are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 24: General operating conditions, with the following configuration: • Output speed is set to OSPEEDRy[1:0] = 11 • Capacitive load CL =30 pF • Measurement points are done at CMOS levels: 0.5VDD • VOS level set to VOS high Refer to Section 6.3.15: I/O port characteristics for more details on the input/output characteristics: Table 137. Dynamic JTAG characteristics(1)
Symbol	Parameter	Conditions	Min	Typ	Max(2)	Unit
FTCK	TCK clock frequency	2.7 V ≤ VDD ≤ 3.6 V	-	-	50	MHz
FTCK	TCK clock frequency	1.71 ≤ VDD ≤ 3.6 V	-	-	40	MHz
tisu(TMS)	TMS input setup time	-	3	-	-	ns
tih(TMS)	TMS input hold time	-	1	-	-	ns
tisu(TDI)	TDI input setup time	-	2	-	-	ns
tih(TDI)	TDI input hold time	-	1	-	-	ns
tov(TDO)	TDO output valid time	2.7 V <VDD < 3.6 V	-	9	10	ns
tov(TDO)	TDO output valid time	1.71 <VDD < 3.6 V	-	10	12.5	ns
toh(TDO)	TDO output hold time	-	8	-	-	ns

Table 93 (pages 286–286)

Table 93 · 9 columns × 15 rows · p.286–286 · CSV

Symbol	millimeters			inches(1)
Symbol	Min	Typ	Max	Min			Typ	Max
A	0.80	0.90	1.00	0.0315	0.0315	0.0315	0.0354	0.0394
A1	0	0.02	0.05	0	0	0	0.0008	0.0020
A3	-	0.20	-	-	-	-	0.0008	-
b	0.15	0.20	0.25	0.0059	0.0059	0.0059	0.0079	0.0098
D	7.85	8.00	8.15	0.3091	0.3091	0.3091	0.3150	0.3209
D2	6.30	6.40	6.50	0.2480	0.2480	0.2480	0.2520	0.2559
E	7.85	8.00	8.15	0.3091	0.3091	0.3091	0.3150	0.3209
E2	6.30	6.40	6.50	0.2480	0.2480	0.2480	0.2520	0.2559
e	-	0.40	-	-	-	-	0.0157	-
L	0.40	0.50	0.60	0.0157	0.0157	0.0157	0.0197	0.0236
ddd	-	-	0.08	-	-	-	-	0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 80. VFQFPN68 -Recommended footprint	1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 80. VFQFPN68 -Recommended footprint	1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 80. VFQFPN68 -Recommended footprint	1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 80. VFQFPN68 -Recommended footprint	1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 80. VFQFPN68 -Recommended footprint	1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 80. VFQFPN68 -Recommended footprint	1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 80. VFQFPN68 -Recommended footprint	1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 80. VFQFPN68 -Recommended footprint	1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 80. VFQFPN68 -Recommended footprint
8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2
8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2
8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2	8.30 7.00 6.65 0.15 6.40 6.40 6.65 7.00 8.300.25 0.820.65 0.40 B029_VFQFPN68_FP_V2

Table 94 (pages 288–288)

Table 94 · 7 columns × 26 rows · p.288–288 · CSV

Symbol	millimeters			inches(14)
Symbol	Min	Typ	Max	Min	Typ	Max
A	-	1.50	1.60	-	0.0590	0.0630
A1(12)	0.05	-	0.15	0.0019	-	0.0059
A2	1.35	1.40	1.45	0.0531	0.0551	0.0570
b(9)(11)	0.17	0.22	0.27	0.0067	0.0087	0.0106
b1(11)	0.17	0.20	0.23	0.0067	0.0079	0.0090
c(11)	0.09	-	0.20	0.0035	-	0.0079
c1(11)	0.09	-	0.16	0.0035	-	0.0063
D(4)	16.00 BSC	16.00 BSC	16.00 BSC	0.6299 BSC	0.6299 BSC	0.6299 BSC
D1(2)(5)	14.00 BSC	14.00 BSC	14.00 BSC	0.5512 BSC	0.5512 BSC	0.5512 BSC
E(4)	16.00 BSC	16.00 BSC	16.00 BSC	0.6299 BSC	0.6299 BSC	0.6299 BSC
E1(2)(5)	14.00 BSC	14.00 BSC	14.00 BSC	0.5512 BSC	0.5512 BSC	0.5512 BSC
e	0.50 BSC	0.50 BSC	0.50 BSC	0.0197 BSC	0.0197 BSC	0.0197 BSC
L	0.45	0.60	0.75	0.177	0.0236	0.0295
L1(1)(11)	1.00	1.00	1.00	-	0.0394	-
N(13)	100	100	100	100	100	100
θ	0°	3.5°	7°	0°	3.5°	7°
θ1	0°	-	-	0°	-	-
θ2	10°	12°	14°	10°	12°	14°
θ3	10°	12°	14°	10°	12°	14°
R1	0.08	-	-	0.0031	-	-
R2	0.08	-	0.20	0.0031	-	0.0079
S	0.20	-	-	0.0079	-	-
aaa(1)	0.20	0.20	0.20	0.0079	0.0079	0.0079
bbb(1)	0.20	0.20	0.20	0.0079	0.0079	0.0079
ccc(1)	0.08	0.08	0.08	0.0031	0.0031	0.0031
ddd(1)	0.08	0.08	0.08	0.0031	0.0031	0.0031

Table 95 (pages 291–291)

Table 95 · 7 columns × 14 rows · p.291–291 · CSV

Symbol	millimeters			inches(1)
Symbol	Min	Typ	Max	Min	Typ	Max
A(2)	-	-	1.100	-	-	0.0433
A1(3)	0.150	-	-	0.0059	-	-
A2	-	0.760	-	-	0.0299	-
b(4)	0.350	0.400	0.450	0.0138	0.0157	0.0177
D	7.850	8.000	8.150	0.3091	0.3150	0.3209
D1	-	7.200		-	0.2835	-
E	7.850	8.000	8.150	0.3091	0.3150	0.3209
E1	-	7.200	-	-	0.2835	-
e	-	0.800	-	-	0.0315	-
F	-	0.400	-	-	0.0157	-
G	-	0.400	-	-	0.0157	-
ddd	-	-	0.100	-	-	0.0039
eee(5)	-	-	0.150	-	-	0.0059
fff(6)	-	-	0.080	-	-	0.0031

Table 96 (pages 292–292)

Table 96 · 2 columns × 6 rows · p.292–292 · CSV

Dpad Dsm BGA_WLCSP_FT_V1
Table 142. TFBGA100 -Recommended PCB design rules (0.8 mm pitch BGA)
Dimension	Recommended values
Pitch	0.8
Dpad	0.400 mm
Dsm	0.470 mm typ. (depends on the soldermask registration tolerance)
Stencil opening	0.400 mm
Stencil thickness	Between 0.100 mm and 0.125 mm
Pad trace width	0.120 mm

Table 97 (pages 294–294)

Table 97 · 7 columns × 26 rows · p.294–294 · CSV

Symbol	millimeters			inches(14)
Symbol	Min	Typ	Max	Min	Typ	Max
A	-	-	1.60	-	-	0.0630
A1(12)	0.05	-	0.15	0.0020	-	0.0059
A2	1.35	1.40	1.45	0.0531	0.0551	0.0571
b(9)(11)	0.17	0.22	0.27	0.0067	0.0087	0.0106
b1(11)	0.17	0.20	0.23	0.0067	0.0079	0.0090
c(11)	0.09	-	0.20	0.0035	-	0.0079
c1(11)	0.09	-	0.16	0.0035	-	0.0063
D(4)	22.00 BSC	22.00 BSC	22.00 BSC	0.8661 BSC	0.8661 BSC	0.8661 BSC
D1(2)(5)	20.00 BSC	20.00 BSC	20.00 BSC	0.7874 BSC	0.7874 BSC	0.7874 BSC
E(4)	22.00 BSC	22.00 BSC	22.00 BSC	0.8661 BSC	0.8661 BSC	0.8661 BSC
E1(2)(5)	20.00 BSC	20.00 BSC	20.00 BSC	0.7874 BSC	0.7874 BSC	0.7874 BSC
e	0.50 BSC	0.50 BSC	0.50 BSC	0.0197 BSC	0.0197 BSC	0.0197 BSC
L	0.45	0.60	0.75	0.0177	0.0236	0.0295
L1	1.00 REF	1.00 REF	1.00 REF	0.0394 REF	0.0394 REF	0.0394 REF
N(13)	144	144	144	144	144	144
θ	0°	3.5°	7°	0°	3.5°	7°
θ1	0°	-	-	0°	-	-
θ2	10°	12°	14°	10°	12°	14°
θ3	10°	12°	14°	10°	12°	14°
R1	0.08	-	-	0.0031	-	-
R2	0.08	-	0.20	0.0031	-	0.0079
S	0.20	-	-	0.0079	-	-
aaa	0.20	0.20	0.20	0.0079	0.0079	0.0079
bbb	0.20	0.20	0.20	0.0079	0.0079	0.0079
ccc	0.08	0.08	0.08	0.0031	0.0031	0.0031
ddd	0.08	0.08	0.08	0.0031	0.0031	0.0031

Table 98 (pages 296–296)

108	73 1.35
0.35	72
0.50

Table 99 (pages 300–300)

Table 99 · 7 columns × 17 rows · p.300–300 · CSV

Symbol	millimeters			inches(1)
Symbol	Min.	Typ.	Max.	Min.	Typ.	Max.
A(2)	-	-	0.60	-	-	0.0236
A1(3)	0.05	-	-	0.0020	-	-
A2	-	0.43	-	-	0.0169	-
b(4)	0.23	0.28	0.33	0.0091	0.0110	0.0130
D(5)	7.00 BSC	7.00 BSC	7.00 BSC	0.2756 BSC	0.2756 BSC	0.2756 BSC
D1(5)	6.00 BSC	6.00 BSC	6.00 BSC	0.2362 BSC	0.2362 BSC	0.2362 BSC
E(5)	7.00 BSC	7.00 BSC	7.00 BSC	0.2756 BSC	0.2756 BSC	0.2756 BSC
E1(5)	6.00 BSC	6.00 BSC	6.00 BSC	0.2362 BSC	0.2362 BSC	0.2362 BSC
e(5)(6)	0.50 BSC	0.50 BSC	0.50 BSC	0.0197 BSC	0.0197 BSC	0.0197 BSC
N(7)	169	169	169	169	169	169
SD(5)(8)	0.50 BSC	0.50 BSC	0.50 BSC	0.0197 BSC	0.0197 BSC	0.0197 BSC
SE(5)(8)	0.50 BSC	0.50 BSC	0.50 BSC	0.0197 BSC	0.0197 BSC	0.0197 BSC
aaa(9)	0.15	0.15	0.15	0.0059	0.0059	0.0059
ccc(9)	0.20	0.20	0.20	0.0079	0.0079	0.0079
ddd(9)	0.08	0.08	0.08	0.0031	0.0031	0.0031
eee(9)	0.15	0.15	0.15	0.0059	0.0059	0.0059
fff(9)	0.05	0.05	0.05	0.0020	0.0020	0.0020

Table 100 (pages 303–303)

Table 100 · 7 columns × 26 rows · p.303–303 · CSV

Symbol	millimeters			inches(14)
Symbol	Min	Typ	Max	Min	Typ	Max
A	-	-	1.600	-	-	0.0630
A1(12)	0.050	-	0.150	0.0020	-	0.0059
A2	1.350	1.400	1.450	0.0531	0.0551	0.0571
b(9)(11)	0.170	0.220	0.270	0.0067	0.0087	0.0106
b1(11)	0.170	0.200	0.230	0.0067	0.0079	0.0091
c(11)	0.090	-	0.200	0.0035	-	0.0079
c1(11)	0.090	-	0.160	0.0035	-	0.063
D(4)	26.000	26.000	26.000	1.0236	1.0236	1.0236
D1(2)(5)	24.000	24.000	24.000	0.9449	0.9449	0.9449
E(4)	26.000	26.000	26.000	0.0197	0.0197	0.0197
E1(2)(5)	24.000	24.000	24.000	0.9449	0.9449	0.9449
e	0.500	0.500	0.500	0.1970	0.1970	0.1970
L	0.450	0.600	0.750	0.0177	0.0236	0.0295
L1(1)(11)	1	1	1	0.0394 REF	0.0394 REF	0.0394 REF
N(13)	176	176	176	176	176	176
θ	0°	3.5°	7°	0°	3.5°	7°
θ1	0°	-	-	0°	-	-
θ2	10°	12°	14°	10°	12°	14°
θ3	10°	12°	14°	10°	12°	14°
R1	0.080	-	-	0.0031	-	-
R2	0.080	-	0.200	0.0031	-	0.0079
S	0.200	-	-	0.0079	-	-
aaa(1)	0.200	0.200	0.200	0.0079	0.0079	0.0079
bbb(1)	0.200	0.200	0.200	0.0079	0.0079	0.0079
ccc(1)	0.080	0.080	0.080	0.0031	0.0031	0.0031
ddd(1)	0.080	0.080	0.080	0.0031	0.0031	0.0031

Table 101 (pages 307–307)

Table 101 · 7 columns × 19 rows · p.307–307 · CSV

Symbol	millimeters			inches(1)
Symbol	Min	Typ	Max	Min	Typ	Max
A(2)	-	-	0.58	-	-	0.0228
A1	-	0.17		-	0.0065	-
A2	-	0.38	-	-	0.0150	-
A3(3)	-	0.025	-	-	0.0010	-
Øb(4)	0.21	0.24	0.27	0.0083	0.0094	0.0106
D	3.84	3.86	3.88	0.1512	0.1519	0.1527
E	3.77	3.79	3.81	0.1482	0.1490	0.1498
e	-	0.35	-	-	0.0138	-
e1	-	3.03	-	-	0.1193	-
e2	-	3.15	-	-	0.1240	-
F(5)	-	0.414	-	-	0.0163	-
G(5)	-	0.320	-	-	0.0125	-
N(6)	101	101	101	101	101	101
Tolerance of form and position	Tolerance of form and position	Tolerance of form and position	Tolerance of form and position	Tolerance of form and position	Tolerance of form and position	Tolerance of form and position
aaa	-	-	0.10	-	-	0.004
bbb	-	-	0.10	-	-	0.004
ccc(7)	-	-	0.10	-	-	0.004
ddd(8)	-	-	0.05	-	-	0.002
eee	-	-	0.05	-	-	0.002

Table 102 (pages 308–308)

Table 102 · 2 columns × 4 rows · p.308–308 · CSV

Dpad Dsm BGA_WLCSP_FT_V1
1. Dimensions are expressed in millimeters. Table 150. WLCSP101 -recommended PCB design rules
Dimension	Recommended values
Pitch	0.35 mm
Dpad	0.210 mm
Dsm	0.275 mm typ. (depends on the soldermask registration tolerance)
Stencil opening	0.235 mm
Stencil thickness	0.100 mm

Table 103 (pages 313–313)

Table 103 · 7 columns × 17 rows · p.313–313 · CSV

Symbol	millimeters(1)			inches(12)
Symbol	Min	Typ	Max	Min	Typ	Max
A(2)(3)	-	-	1.20	-	-	0.0472
A1(4)	0.15	-	-	0.0059	-	-
A2	-	0.78	-	-	0.0307	-
b(5)	0.35	0.40	0.45	0.0138	0.0157	0.0177
D(6)	13.00 BSC	13.00 BSC	13.00 BSC	0.5118 BSC	0.5118 BSC	0.5118 BSC
D1	11.20 BSC	11.20 BSC	11.20 BSC	0.4409 BSC	0.4409 BSC	0.4409 BSC
E	13.00 BSC	13.00 BSC	13.00 BSC	0.5118 BSC	0.5118 BSC	0.5118 BSC
E1	11.20 BSC	11.20 BSC	11.20 BSC	0.4409 BSC	0.4409 BSC	0.4409 BSC
e(9)	0.80 BSC	0.80 BSC	0.80 BSC	0.0315 BSC	0.0315 BSC	0.0315 BSC
N(11)	225	225	225	225	225	225
SD(12)	0.80 BSC	0.80 BSC	0.80 BSC	0.0315 BSC	0.0315 BSC	0.0315 BSC
SE(12)	0.80 BSC	0.80 BSC	0.80 BSC	0.0315 BSC	0.0315 BSC	0.0315 BSC
aaa	0.15	0.15	0.15	0.0059	0.0059	0.0059
ccc	0.20	0.20	0.20	0.0079	0.0079	0.0079
ddd	0.10	0.10	0.10	0.0039	0.0039	0.0039
eee	0.15	0.15	0.15	0.0059	0.0059	0.0059
fff	0.08	0.08	0.08	0.0031	0.0031	0.0031

Table 104 (pages 314–314)

Table 104 · 2 columns × 4 rows · p.314–314 · CSV

Dpad Dsm BGA_WLCSP_FT_V1
Table 154. TFBGA225 -Recommended PCB design rules (0.8 mm pitch BGA)
Dimension	Recommended values
Pitch	0.8 mm
Dpad	0.400 mm
Dsm	0.550 mm
Stencil opening	0.400 mm
Stencil thickness	0.125 to 0.100 mm

Table 105 (pages 315–316)

Table 105 · 5 columns × 30 rows · p.315–316 · CSV

Table 106 (pages 319–320)

Table 106 · 3 columns × 5 rows · p.319–320 · CSV

Date	Revision	Changes
03-Nov-2023	1	Initial release.
15-Mar-2024	2	Corrected maximum CPU frequency in Table 3: STM32H7Rxx8 features and peripheral counts. Added: – Section 3.3.2: Secure access mode – Section 6: Electrical characteristics.
28-Nov-2024	3	Updated: – Cover page features – Figure 1: STM32H7Rxx8 block diagram – Table 2: Security and graphics IP availability per product line (replaced TIL by HDP) – Table 3: STM32H7Rxx8 features and peripheral counts: junction maximum temperature, display interface (bits), and SMPS step-down converter – Section 3.5.1: Power supply scheme – Table 19: STM32H7Rxx8 pin and ball descriptions (indicated pins with fm+ capable I/O structure ‘FT_fh’) – Figure 12: UFBGA176 SMPS GFx pinout – Table 20: STM32H7Rxx8 pin alternate functions (added PG12 to PG15) – Table 24: General operating conditions – Junction maximum temperature in Section 6: Electrical characteristics – Table 41: Typical and maximum current consumption in System Stop mode through Table 49: Typical and maximum current consumption: data write 6.25% toggle on 16-bit memory – Table 62: PLL1/2/3 characteristics (wide VCO frequency range) (title) – Table 63: PLL1/2/3 characteristics (low VCO frequency range) (title and content). – Removed previous document revision Table 66 and Table 67. – Table 99: XSPI characteristics in DTR mode (with DQS)/Hyperbus – Section 7.7: UFBGA169 package information (A0YV) – Section 7.11: TFBGA225 package information (B04V) – Table 155: Package thermal characteristics (typo corrected)
15-Dec-2025	4	Updates: – Core description on cover page. – Table 19: STM32H7Rxx8 pin and ball descriptions. – Introduction text removed in Output buffer timing characteristics (HSLV option disabled). – Table 24: General operating conditions – Table 115: PSSI transmit characteristics. – Table 58: PSSI transmit timing diagram – Table 132: OTG_HS current consumption characteristics – Table 133: UCPD electrical characteristics
02-Feb-2026	5	Updated: – Table 2: Security and graphics IP availability per product line – Table 3: STM32H7Rxx8 features and peripheral counts

Symbol	Definition	Parameter	Value	Unit
ΘJA	Thermal resistance junction-ambient	Thermal resistance junction-ambient VFQFPN68 -8 x 8 mm / 0.35 mm pitch	23.8	°C/W
ΘJA	Thermal resistance junction-ambient	Thermal resistance junction-ambient LQFP100 -14 x 14 mm / 0.5 mm pitch	34.9	°C/W
ΘJA	Thermal resistance junction-ambient	Thermal resistance junction-ambient LQFP144 -20 x 20 mm / 0.5 mm pitch	36.4	°C/W
ΘJA	Thermal resistance junction-ambient	Thermal resistance junction-ambient LQFP176 -24 x 24 mm / 0.5 mm pitch	35.9	°C/W
ΘJA	Thermal resistance junction-ambient	Thermal resistance junction-ambient WLCSP101 -3.86 x 3.79 mm / 0.35 mm pitch	43.2	°C/W
ΘJA	Thermal resistance junction-ambient	Thermal resistance junction-ambient TFBGA100 -8 x 8 mm / 0.8 mm pitch	35.0	°C/W
ΘJA	Thermal resistance junction-ambient	Thermal resistance junction-ambient UFBGA144 -10 x 10 mm / 0.8 mm pitch	35.0	°C/W
ΘJA	Thermal resistance junction-ambient	Thermal resistance junction-ambient UFBGA169 -7 x 7 mm / 0.5 mm pitch	37.1	°C/W
ΘJA	Thermal resistance junction-ambient	Thermal resistance junction-ambient UFBGA176 -10 x 10 mm / 0.65 mm pitch	35.7	°C/W
ΘJA	Thermal resistance junction-ambient	Thermal resistance junction-ambient TFBGA225 -13 x 13 mm / 0.8 mm pitch	32.8	°C/W
ΘJB	Thermal resistance junction-board	Thermal resistance junction-board VQFN68 -8 x 8 mm / 0.35 mm pitch	9.0	°C/W
ΘJB	Thermal resistance junction-board	Thermal resistance junction-board LQFP100 -14 x 14 mm / 0.5 mm pitch	20.8	°C/W
ΘJB	Thermal resistance junction-board	Thermal resistance junction-board LQFP144 -20 x 20 mm / 0.5 mm pitch	25.3	°C/W
ΘJB	Thermal resistance junction-board	Thermal resistance junction-board LQFP176 -24 x 24 mm / 0.5 mm pitch	25.9	°C/W
ΘJB	Thermal resistance junction-board	Thermal resistance junction-board WLCSP101 -3.86 mm / 0.35 mm pitch	21.1	°C/W
ΘJB	Thermal resistance junction-board	Thermal resistance junction-board TFBGA100 -8 x 8 mm / 0.8 mm pitch	22.0	°C/W
ΘJB	Thermal resistance junction-board	Thermal resistance junction-board UFBGA144 -10 x 10 mm / 0.8 mm pitch	22.9	°C/W
ΘJB	Thermal resistance junction-board	Thermal resistance junction-board UFBGA169 -7 x 7 mm / 0.5 mm pitch	22.8	°C/W
ΘJB	Thermal resistance junction-board	Thermal resistance junction-board UFBGA176 -10 x 10 mm / 0.65 mm pitch	23.6	°C/W
ΘJB	Thermal resistance junction-board	Thermal resistance junction-board TFBGA225 -13 x 13 mm / 0.8 mm pitch	22.3	°C/W
ΘJC	Thermal resistance junction-case	Thermal resistance junction-case VQFN68 -8 x 8 mm / 0.35 mm pitch	10.7	°C/W
ΘJC	Thermal resistance junction-case	Thermal resistance junction-case LQFP100 -14 x 14 mm / 0.5 mm pitch	7.7	°C/W
ΘJC	Thermal resistance junction-case	Thermal resistance junction-case LQFP144 -20 x 20 mm / 0.5 mm pitch	7.9	°C/W
ΘJC	Thermal resistance junction-case	Thermal resistance junction-case LQFP176 -24 x 24 mm / 0.5 mm pitch	9.2	°C/W
ΘJC	Thermal resistance junction-case	Thermal resistance junction-case WLCSP101 -3.86 mm / 0.35 mm pitch	1.8	°C/W
ΘJC	Thermal resistance junction-case	Thermal resistance junction-case TFBGA100 -8 x 8 mm / 0.8 mm pitch	12.6	°C/W
ΘJC	Thermal resistance junction-case	Thermal resistance junction-case UFBGA144 -10 x 10 mm / 0.8 mm pitch	9.0	°C/W
ΘJC	Thermal resistance junction-case	Thermal resistance junction-case UFBGA169 -7 x 7 mm / 0.5 mm pitch	9.4	°C/W
ΘJC	Thermal resistance junction-case	Thermal resistance junction-case UFBGA176 -10 x 10 mm / 0.65 mm pitch	9.0	°C/W
ΘJC	Thermal resistance junction-case	Thermal resistance junction-case TFBGA225 -13 x 13 mm / 0.8 mm pitch	12.0	°C/W