infineon-psoc-edge-e8x-consumer-datasheet-datasheet-en

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Table 1 (pages 8–8)

Table 1 · 4 columns × 9 rows · p.8–8 · CSV

System Resources		Autonomous Analog
Power Clock		1x SAR ADC 4x Opamp/PGA/
OVD Clock Control POR BOD PILO IHO REF LVD WCO ECO		(12-20 bit, 5 Msps) TIA/Buffer/Comp512-entry FIFO, 2x FIR 2x PTComp, 2x 12-bit DAC 2x 4b Prog. Ref.,
Buck Cvtr. HP, 2x LP DPLL Retention LDOs WDT 2x MCWDT		512-entry waveform AAD (Acoustic Activity Detection)	I/O
Active LDO RTC Reset 16x Backup registers		Autonomous Controller State Machine	Smart I/O
Reset Control		1x SCB (Deep Sleep) I2C, SPI	2x USB
Lock-Step Secure Enclave	(AHB), IPC0	LOW POWER DOMAIN “VIRTUAL” ALWAYS-ON	I/O DSI I/O, 2x
Low Power CPU Subsystem Cortex®-M33 200 MHz 16 KB I-Cache	Interconnect	GPIO 32x TCPWM 11x SCB (UART, I 2 C, SPI)	Scan, Smart 6x SMIF I/O, 7x
Debug and trace RRAM 512 KB		1x I3C Crypto	Boundary V HSIO,
SRAM 1 MB (granular) 2x 16-channel DMA		10/100 Ethernet RMII/MII 15882x CAN FD NNLite	I/O Matrix, GPIO, 16x 1.8

Table 2 (pages 8–8)

System SRAM		HIGH PERFORMANCE DOMAIN	1.8 to
(“SoCMEM”) 5120 KB (granular)		2x SD Host Controller (SD 6.0 / SDIO 4.10 / eMMC 5.1)	GPIO, 16x
High Performance CPU Subsystem 4-channel HPDMA Cortex®-M55 400 MHz	(AXI, AHB), IPC1	2x Serial Memory Interface (SMIF) 32 KB Cache USB 2.0 HS/FS PHY Audio Interfaces 2x 8-channel TDM/2x 2-channel I2S (2x RX, 2x TX)	100x 1.8 V
32 KB I-& D-Caches Debug and trace Ethos-U55	Interconnect	1x 6-channel PDM/PCM (6 mics)
400 MHz		Graphics Subsystem
		2.5D Rendering MIPI DSI
		Multi-plane Composition MIPI DBI

Table 3 (pages 14–14)

Table 3 · 4 columns × 5 rows · p.14–14 · CSV

1 µF 0.1 µF	VDDD; A7, B8, F7, G4, P10		2.2 µH
4.7 µF 0.1 µF	VDDQ; A11	VOUT.1P8; C13	4.7 µF
4.7 µF	VDD.1P8; A9, C12	VFB.1P8; B13
0.1 µF	VDD.DSI ## ; D6	VCCD; B1, B9, E9, F11, H4, M8	0.1 µF
1 µF 0.1 µF*	VDDIO0*; R3; I/O ports P6, P7
1 µF 0.1 µF*	VDDIO1*; E6; I/O port P8	VLDO.SRAM; A8
1 µF 0.1 µF*	VDDIO2*; N14; I/O ports P9, P20	VCC.SRAM; F12, K3

Table 4 (pages 14–14)

Table 4 · 4 columns × 0 rows · p.14–14 · CSV

1 µF	0.1 µF*	VDDIO3*; E13; I/O ports P10, P11
1 µF	0.1 µF*	VDDIO4*; B2; I/O ports P12, P21	VLDO.DSI # ; B7
1 µF	0.1 µF*	VDDIO5*; A6; I/O ports P18, P19	VCCA.DSI # ; C6, C7

Table 5 (pages 14–14)

Table 5 · 3 columns × 6 rows · p.14–14 · CSV

1 µF*	VDDIO8; L12; I/O port P15**
1 µF 0.1 µF*	VDDIO.SMIF0*; J3, M3; I/O ports P1, P2, P3, P5
1 µF 0.1 µF*	VDDIO.SMIF1*; E3, G3; I/O ports P0, P4
1 µF 0.1 µF	VDDA; H4, J11, J12
3.3 V 1 µF 0.1 µF	VDD.USB; M7
	VDD.VBAT; A10, B10	VOUT.VBAT; A12
	VBAT; B11, D10	VFB.VBAT; B12

Table 6 (pages 16–16)

Table 6 · 4 columns × 5 rows · p.16–16 · CSV

1 µF 0.1 µF	VDDD; E11, J6, L10, M10, R11		2.2 µH
4.7 µF 0.1 µF	VDDQ; m13	VOUT.1P8; R16	4.7 µF
4.7 µF	VDD.1P8; M12, R15, T15	VFB.1P8; N15
0.1 µF	VDD.DSI ## ; N7	VCCD; D8, J5, J11, M11, N4, U11	0.1 µF
1 µF 0.1 µF*	VDDIO0*; C3; I/O ports P6, P7
1 µF 0.1 µF*	VDDIO1*; L9; I/O port P8	VLDO.SRAM; N11
1 µF 0.1 µF*	VDDIO2*; B16; I/O ports P9, P20	VCC.SRAM; F4, J12

Table 7 (pages 16–16)

Table 7 · 4 columns × 0 rows · p.16–16 · CSV

1 µF	0.1 µF*	VDDIO3*; L14; I/O ports P10, P11
1 µF	0.1 µF*	VDDIO4*; P5; I/O ports P12, P21	VLDO.DSI # ; N10
1 µF	0.1 µF*	VDDIO5*; M9; I/O ports P18, P19	VCCA.DSI # ; M6, M7

Table 8 (pages 16–16)

Table 8 · 2 columns × 0 rows · p.16–16 · CSV

1 µF*	VDDIO8; F16; I/O port P15**
1 µF 0.1 µF*	VDDIO.SMIF0*; E2, G5, H6; I/O ports P1, P2, P3, P5
1 µF 0.1 µF*	VDDIO.SMIF1*; K4, L5, N2; I/O ports P0, P4
1 µF 0.1 µF	VDDA; F13, F14, H13

Table 9 (pages 17–17)

Table 9 · 2 columns × 12 rows · p.17–17 · CSV

1 µF 0.1 µF	VDDD; E11, J6, L10, M10, R11
4.7 µF 0.1 µF	VDDQ; M13 VOUT.VBAT; M14
0.1 µF	VDD.VBAT; T12, T13, U12, U13 VFB.VBAT; R14
0.1 µF	VDD.DSI ## ; N7 VCCD; D8, J5, J11, M11, N4, U11
1 µF 0.1 µF*	VDDIO0*; C3; I/O ports P6, P7
1 µF 0.1 µF*	VDDIO1*; L9; I/O port P8 VLDO.SRAM; N11
1 µF 0.1 µF*	VDDIO2*; B16; I/O ports P9, P20 VCC.SRAM; F4, J12
1 µF 0.1 µF*	VDDIO3*; L14; I/O ports P10, P11
1 µF 0.1 µF*	VDDIO4*; P5; I/O ports P12, P21 VLDO.DSI # ; N10
1 µF 0.1 µF*	VDDIO5*; M9; I/O ports P18, P19 VCCA.DSI # ; M6, M7
1 µF 0.1 µF*	VDDIO6; E10; I/O ports P16, P17*
1 µF*	VDDIO7; J14; I/O port P13, P14* VLDO.RET; N12
1 µF*	VDDIO8; F16; I/O port P15**
1 µF 0.1 µF*	VDDIO.SMIF0*; E2, G5, H6; I/O ports P1, P2, P3, P5
1 µF 0.1 µF*	VDDIO.SMIF1*; K4, L5, N2; I/O ports P0, P4
1 µF 0.1 µF	VDDA; F13, F14, H13

Table 10 (pages 18–18)

Table 10 · 4 columns × 5 rows · p.18–18 · CSV

1 µF 0.1 µF	VDDD; C11, G3, L7, L8, L9		2.2 µH
4.7 µF 0.1 µF	VDDQ; K11	VOUT.1P8; L13	4.7 µF
4.7 µF	VDD.1P8; L11, L12	VFB.1P8; K12
0.1 µF	VDD.DSI ## ; K6	VCCD; A4, F3, H14, J9, L1, L10	0.1 µF
1 µF 0.1 µF*	VDDIO0*; A1; I/O ports P6, P7
1 µF 0.1 µF*	VDDIO1*; L6; I/O port P8	VLDO.SRAM; H10
1 µF 0.1 µF*	VDDIO2*; B12; I/O port P9	VCC.SRAM; C4, H12

Table 11 (pages 18–18)

Table 11 · 4 columns × 0 rows · p.18–18 · CSV

1 µF	0.1 µF*	VDDIO3*; F13
1 µF	0.1 µF*	VDDIO4*; L3; I/O ports P12, P21	VLDO.DSI # ; K9
1 µF	0.1 µF*	VDDIO5*; J8; I/O ports P18, P19	VCCA.DSI # ; K5

Table 12 (pages 18–18)

Table 12 · 2 columns × 0 rows · p.18–18 · CSV

1 µF*	VDDIO8; D12; I/O port P15**
1 µF 0.1 µF*	VDDIO.SMIF0*; C3, D4; I/O ports P1, P2, P3, P5
1 µF 0.1 µF*	VDDIO.SMIF1*; H3, K3; I/O port P4
1 µF 0.1 µF	VDDA; F12

Table 13 (pages 19–19)

Table 13 · 4 columns × 5 rows · p.19–19 · CSV

		VBAT Domain
	VBAT	POR BOR
		LVD	SRSS
			OVD
1.8 V	VDDQ	1.8 V Domain	POR BOR
	4.7 µF	HPBG Reference Buffer PMU	XRES Deepsleep_ref Deep Sleep Reference pmu_en PMU Control

Table 14 (pages 19–19)

VDDD	VFB.VBAT
1 µF
	VOUT.1P8	2.2 µH	VCCD

Table 15 (pages 19–19)

Table 15 · 4 columns × 2 rows · p.19–19 · CSV

3.3 V	VDD.USB USBPHY
1 µF	0.1 µF
		VSS	VSSA

Table 16 (pages 20–20)

Table 16 · 4 columns × 1 rows · p.20–20 · CSV

	10 µF	LVD	SRSSOVD
1.8 V	VDDQ	1.8 V Domain	POR BOR
	4.7 µF	HPBG Reference Buffer PMU	XRES Deepsleep_ref Deep Sleep Reference pmu_en PMU Control

Table 17 (pages 23–24)

Table 17 · 3 columns × 30 rows · p.23–24 · CSV

CPU Active	CPU Sleep	System Deep Sleep
Y	N
Y		N
Y		N
Y	Y	Y
Y	Y	N
Y	Y	Programmable
Y	Y	N
Y	Y	Y
Y	Y	N
Y	Y	N, SCB0 is supported in System Deep Sleep power mode
Y	Y	N
Y	Y	N
Y	Y	N
Y	Y	N
Y	Y	N
Y	Y	N
Y	Y	N
Y	Y	N
Y	Y	N
Y	Y	N
Y	Y	N
Y	Y	Y
Y	Y	Y (duty cycled)
Y	Y	Y
Y	Y	Y
Y	Y	Y
Y	Y	Y
Y	Y	Y
Y	Y	Y
Y	Y	Y
Y	Y	Y
Y	Y	N
Y	Y	N

Table 18 (pages 25–25)

Table 18 · 5 columns × 2 rows · p.25–25 · CSV

		Secure Firmware		API
Basic Run-Time Services			calls	PSA
Boot	calls	Extended Boot	IPC

Table 19 (pages 34–34)

Table 19 · 5 columns × 2 rows · p.34–34 · CSV

aanalog.ctb0.7 PIN[7]
			Voltage Sources PRB_OUT0	Always-On Autonomous Control
CTB1Port aanalog.ctb1.0 PIN[0] aanalog.ctb1.1 PIN[1] aanalog.ctb1.2 PIN[2]	Muxes, Routing	OA0	Programmable Reference Block PRB_OUT1 (PRB) (4-bit)	Finite State Machine (FSM) Controller State Transition Table SAR Sequencer Table

Table 20 (pages 34–34)

Table 20 · 3 columns × 6 rows · p.34–34 · CSV

aanalog.ctb1.3 PIN[3]		Static Configs Dynamic Configs
aanalog.ctb1.4 PIN[4] aanalog.ctb1.5 PIN[5]	OA1 CTB1 VBGR Bandgap Reference (0.9V)	Trigger and Interrupt Logic
aanalog.ctb1.6 PIN[6]		16-bit Wake Up Timer
aanalog.ctb1.7 PIN[7]	Voltage Sources
		4.096MHz Clock HS/PERI Clocks
	CTB Pins and Outputs
	Voltage Sources Programmable Comparator (PTComp) Threshold 0
	CTB Pins and Outputs COMPMUX	Comparator Post-Processing Edge Detect 16-bit Counter Logic (LUT) Limit Detect

Table 21 (pages 37–38)

Table 21 · 4 columns × 9 rows · p.37–38 · CSV

Protocol speed	I/O (V)	Max Freq. (MHz)	Data width (bits)
Default speed (DS)	3.3	25	1, 4
High speed (HS)	3.3	50	1, 4
SDR12	1.8	25	1, 4
SDR25	1.8	50	1, 4
SDR50	1.8	100	1, 4
DDR50	1.8	50	1, 4
Legacy/Backward compatible (BWC)	1.8/3.3	26	1, 4, 8
SDR	1.8/3.3	52	1, 4, 8
DDR	1.8/3.3	52	1, 4, 8

Table 22 (pages 45–50)

Table 22 · 2 columns × 179 rows · p.45–50 · CSV

BGA-220	eWLB-235
A7 B8 F7 G4 P10	E11 J6 L10 M10 R11
H14 J11 J12	F13 F14 H13
A9 C12	M12 R15 T15
D6	N7
M7	C5
A10 B10	T12 T13 U12 U13
J3 M3	E2 G5 H6
E3 G3	K4 L5 N2
R3	C3
E6	L9
N14	B16
E13	L14
B2	P5
A6	M9
R10	E10
G12	J14
L12	F16
A11	M13
B1 B9 E9 F11 H4 M8	D8 J5 J11 M11 N4 U11
C6 C7	M6 M7
F12 K3	F4 J12
G13 H12 J13 K12 L13	D16 F15 H14 J13
D13 B5 E8 C8 E12 C10 N10 F3 D3 R7 H3 D7 L3 D9 L8 D11 N3	A1 A17 C2 C4 C11 C15 D9 G4G6 J4 K5 K14 L4 L15 M16 N5N8 N9 R7 R12 T11 T14 U1U10 U14 U15 U16 U17
D12	N16
C11	N14
B11 D10	N13 R13
B13	N15
B12	R14
B7	N10
C9	N12
A8	N11
C13	R16
A12	M14
K14	F17
A4	U4
A5	U5
B4	R6
B3	R5
A3	T5
A2	T4
J6	N6
L1	E1
M1	D1
J1	H5
F1	M1
E1	N1
H1	K6
P7	A6
N7	B6
D8	R10
K5	K7
C4	L6
N2	F2
P1	G2
N1	D2
M2	C1
L2	H2
K2	G1
K1	F1
J2	H4
K4	J7
M4	H7
L6	H8
C2	M2
C1	P2
D2	L2
D1	R1
F2	K1
E2	J1
G2	K2
H2	J2
J4	J8
M6	C6
N6	B4
P6	A4
R6	A3
R5	A2
R2	B3
P5	B2
P2	B1
P3	D5
N5	D6
R4	E5
M5	E4
P4	E6
L4	F7
N4	F6
L5	F5
H7	K10
J8	T8
J7	R8
K8	U6
F6	T6
E7	T7
G6	M8
H6	K9
L14	F10
M13	F11
M14	E12
N13	G9
B15	T16
A13	L12
C15	M15
A14	P16
D14	T17
B14	L13
D15	P17
C14	M17
E14	L16
E11	K16
E15	L11
E10	K11
F14	K12
F9	J10
F13	K13
F10	K15
H5	P4
D5	R4
G5	T3
E5	U3
F4	U2
F5	R3
G8	H10
G9	J15
G10	K17
F15	H17
G11	H11
G14	H12
H11	H16
H15	H15
H10	G12
H13	G13
H9	G14
K15	G16
J9	G15
J15	J9
J10	H9
J14	F12
L15	G11
K13	G10
M15	E13
K9	E15
N15	E14
K10	D17
P15	B17
K11	C16
M11	B11
R13	A10
N11	B10
L11	C10
P11	F9
L10	G8
R11	F8
M10	E9
M9	E8
R9	G7
R8	E7
P9	B8
P8	C8
N9	A8
N8	C7
L9	D7
G7	R9
H8	T9
B6	U8
F8	T10
P14	B15
M12	A16
R15	B14
N12	C14
R14	A14
P12	A12
P13	B12
R12	C12
J5	T2
E4	T1
K7	R2
D4	L8
K6	K8
C5	M5
L7	M4
C3	L7

Table 23 (pages 52–52)

Table 23 · 4 columns × 23 rows · p.52–52 · CSV

Pins available in the port		Functions
0, 1		SMIF1 select, TCPWM, SCB
0 -7		SMIF0 data, TCPWM
0	0	SMIF0 select, TCPWM	SMIF0 select, TCPWM
0, 1	0, 1	I3C, SD Host, TCPWM	I3C, SD Host, TCPWM
0 -7	0 -7	SMIF1 data, trace, TCPWM	SMIF1 data, trace, TCPWM
0	0	SMIF0 select, TCPWM	SMIF0 select, TCPWM
0 -7	0 -7	SMIF0 select, SCB, SD host, SWJ, TCPWM	SMIF0 select, SCB, SD host, SWJ, TCPWM
0 -7	0 -7	SMIF0 select, fault, external clock, SWJ, TCPWM	SMIF0 select, fault, external clock, SWJ, TCPWM
0 -7	0 -7	Hibernate wakeup, SWD, cal wave, TCPWM	Hibernate wakeup, SWD, cal wave, TCPWM
0 -3	0 -3	SCB, PDM, TCPWM	SCB, PDM, TCPWM
0 -7	0 -7	LPComp input, fault, SCB, Ethernet,	LPComp input, fault, SCB, Ethernet,
0 -7	0 -7	Smart I/O, SCB, TDM, trigger input,	Smart I/O, SCB, TDM, trigger input,
0 -5	0 -5	SMIF1 select, SD host, TDM, TCPWM	SMIF1 select, SD host, TDM, TCPWM
0 -7	0 -7	CTBL, Opamp output, DAC, SCB, PDM,	CTBL, Opamp output, DAC, SCB, PDM,
0 -7	0 -7	CTBL, Opamp output, DAC, SCB, PDM,	CTBL, Opamp output, DAC, SCB, PDM,
0 -7	0 -7	SARMUX, PTC, SCB, TCPWM	SARMUX, PTC, SCB, TCPWM
0 -7	0 -7	CAN, SCB, Graphics, TCPWM	CAN, SCB, Graphics, TCPWM
0 -7	0 -7	Smart I/O, SCB, Graphics, Auto-analog	Smart I/O, SCB, Graphics, Auto-analog
0, 1	0, 1	WCO	WCO
0, 1	0, 1	ECO	ECO
0 -7	0 -7	CAN, SCB, trace, Auto-analog output	CAN, SCB, trace, Auto-analog output
0 -7	0 -7	SCB, TDM, SD host, TCPWM	SCB, TDM, SD host, TCPWM
availability varies across packages. Refer to Table 9 for details. how the HSIOM bitfield settings relate to the alternate function groups modes, for each GPIO. HSIOM settings, functions, and ports	availability varies across packages. Refer to Table 9 for details. how the HSIOM bitfield settings relate to the alternate function groups modes, for each GPIO. HSIOM settings, functions, and ports	availability varies across packages. Refer to Table 9 for details. how the HSIOM bitfield settings relate to the alternate function groups modes, for each GPIO. HSIOM settings, functions, and ports	availability varies across packages. Refer to Table 9 for details. how the HSIOM bitfield settings relate to the alternate function groups modes, for each GPIO. HSIOM settings, functions, and ports
setting	Function group	Function group	Functions
	GPIO	GPIO	None, basic GPIO

Table 24 (pages 53–53)

Table 24 · 2 columns × 33 rows · p.53–53 · CSV

Function group	Functions
not used	-
ACT #0	SMIF select
ACT #1	TCPWM
ACT #2	TCPWM
ACT #3	fault
not used	-
DS #2	SCB 0 (SPI only)
DS #3	SCB 0 (I2 C only)
ACT #4	SCB
ACT #4	External clock
ACT #4	CAN
ACT #5	TDM
ACT #5	SCB
ACT #6	SCB
ACT #7	SCB
ACT #7	TDM
ACT #8	SCB
ACT #9	PDM
ACT #10	Trigger IO
ACT #11	Trigger IO
not used	-
ACT #13	Graphics
ACT #14	SD host
ACT #14	Graphics
ACT #15	I3C
ACT #15	Trace
ACT #15	SD host
ACT #15	Graphics
ACT #15	Ethernet
DS #4	Auto-analog data out
DS #5	SWJ
DS #5	Auto-analog observe
not used	-

Table 25 (pages 54–54)

Table 25 · 3 columns × 28 rows · p.54–54 · CSV

smif[1].smif0_spihb_select1	ACT #0	tcpwm.line0+
tcpwm.line256+	ACT #2	scb3.spi.select0
smif[1].smif0_spihb_select2	ACT #0	tcpwm.line0-
tcpwm.line256-	ACT #2
tcpwm.line1+	ACT #1	tcpwm.line257+
tcpwm.line1-	ACT #1	tcpwm.line257-
tcpwm.line2+	ACT #1	tcpwm.line258+
tcpwm.line2-	ACT #1	tcpwm.line258-
tcpwm.line3+	ACT #1	tcpwm.line259+
tcpwm.line3-	ACT #1	tcpwm.line259-
tcpwm.line4+	ACT #1	tcpwm.line260+
tcpwm.line4-	ACT #1	tcpwm.line260-
smif[0].smif0_spihb_select1	ACT #0	tcpwm.line5+
tcpwm.line261+	ACT #2	ACT #2
tcpwm.line5-	ACT #1	tcpwm.line261-
sdhost1.card_mech_write_prot: 1	ACT #14	i3c.scl
tcpwm.line6+	ACT #1	tcpwm.line262+
i3c.sda	ACT #15	ACT #15
tcpwm.line6-	ACT #1	tcpwm.line262-
tcpwm.line7+	ACT #1	tcpwm.line263+
tcpwm.line7-	ACT #1	tcpwm.line263-
tcpwm.line0+	ACT #1	tcpwm.line264+
trace.clock	ACT #15	ACT #15
tcpwm.line0-	ACT #1	tcpwm.line264-
trace.data0	ACT #15	ACT #15
tcpwm.line1+	ACT #1	tcpwm.line265+
trace.data1	ACT #15	ACT #15
tcpwm.line1-	ACT #1	tcpwm.line265-
trace.data2	ACT #15	ACT #15
tcpwm.line2+	ACT #1	tcpwm.line266+
trace.data3	ACT #15	ACT #15
smif[0].smif0_spihb_select0	ACT #0	tcpwm.line2-

Table 26 (pages 55–55)

Table 26 · 3 columns × 29 rows · p.55–55 · CSV

tcpwm.line266-	ACT #2
tcpwm.line3+	ACT #1	tcpwm.line267+
sdhost1.card_mech_write_prot: 0	ACT #14	swj.tdo
tcpwm.line3-	ACT #1	tcpwm.line267-
sdhost1.led_ctrl	ACT #15	swj.tdi
tcpwm.line4+	ACT #1	tcpwm.line268+
sdhost1.card_if_pwr_en	ACT #15	swj.swdio/tms
tcpwm.line4-	ACT #1	tcpwm.line268-
scb2.spi.select1	ACT #6	sdhost1.io_volt_sel
swj.swclk/tclk	DS #5	DS #5
tcpwm.line5+	ACT #1	tcpwm.line269+
scb2.spi.miso	ACT #6	scb2.uart.cts
sdhost1.card_dat_7to4_0	ACT #15	ACT #15
tcpwm.line5-	ACT #1	tcpwm.line269-
scb2.spi.clk	ACT #6	scb2.i2c.scl
scb2.uart.rx	ACT #8	sdhost1.card_dat_7to4_1
tcpwm.line6+	ACT #1	tcpwm.line270+
scb2.spi.select0	ACT #6	scb2.uart.rts
sdhost1.card_dat_7to4_2	ACT #15	ACT #15
smif[0].smif0_spihb_select2	ACT #0	tcpwm.line6-
tcpwm.line270-	ACT #2	scb2.spi.mosi
scb2.i2c.sda	ACT #7	scb2.uart.tx
sdhost1.card_dat_7to4_3	ACT #15	ACT #15
smif[0].smif0_spihb_select3	ACT #0	tcpwm.line7+
tcpwm.line271+	ACT #2	m33syscpuss.fault0
trig0.out0	ACT #10	trig1.out0
sdhost1.card_cmd	ACT #15	ACT #15
tcpwm.line7-	ACT #1	tcpwm.line271-
m33syscpuss.fault1	ACT #3	trig0.out1
trig1.out1	ACT #11	sdhost1.clk_card
tcpwm.line0+	ACT #1	tcpwm.line272+
sdhost1.card_emmc_reset_n	ACT #15	swj.trstn
tcpwm.line0-	ACT #1	tcpwm.line272-

Table 27 (pages 56–56)

Table 27 · 3 columns × 29 rows · p.56–56 · CSV

sdhost1.card_dat_3to0_0	ACT #15
tcpwm.line1+	ACT #1	tcpwm.line273+
ext_clk	ACT #4	sdhost1.card_detect_n
tcpwm.line1-	ACT #1	tcpwm.line273-
trig0.in4	ACT #10	trig1.in4
sdhost1.card_dat_3to0_1	ACT #15	ACT #15
tcpwm.line2+	ACT #1	tcpwm.line274+
trig0.in5	ACT #10	trig1.in5
sdhost1.card_dat_3to0_2	ACT #15	ACT #15
tcpwm.line2-	ACT #1	tcpwm.line274-
trig0.in6	ACT #10	trig1.in6
sdhost1.card_dat_3to0_3	ACT #15	ACT #15
tcpwm.line3+	ACT #1	tcpwm.line275+
scb0.spi.clk	DS #2	scb0.i2c.scl
trig0.in7	ACT #10	trig1.in7
m0seccpuss.m0sec_swd	DS #5	DS #5
tcpwm.line3-	ACT #1	tcpwm.line275-
scb0.spi.mosi	DS #2	scb0.i2c.sda
m0seccpuss.clk_m0sec_swd	DS #5	DS #5
tcpwm.line4+	ACT #1	tcpwm.line276+
scb0.spi.select0	DS #2	pdm2.clk
hibernate_wakeup	fixed	tcpwm.line4-
tcpwm.line276-	ACT #2	scb0.spi.select1
tcpwm.line5+	ACT #1	tcpwm.line277+
scb0.spi.miso	DS #2	cal_wave
pdm2.data	ACT #9	ACT #9
tcpwm.line5-	ACT #1	tcpwm.line277-
pdm3.clk	ACT #9	ACT #9
tcpwm.line6+	ACT #1	tcpwm.line278+
pdm3.data	ACT #9	ACT #9
hibernate_wakeup	fixed	tcpwm.line6-
tcpwm.line278-	ACT #2	ACT #2
tcpwm.line7+	ACT #1	tcpwm.line279-

Table 28 (pages 57–57)

Table 28 · 3 columns × 29 rows · p.57–57 · CSV

scb1.spi.select0	ACT #6	scb1.uart.rts
pdm5.clk	ACT #9
tcpwm.line0+	ACT #1	tcpwm.line256-
scb1.spi.miso	ACT #6	scb1.uart.cts
pdm5.data	ACT #9	ACT #9
tcpwm.line7-	ACT #1	tcpwm.line279+
scb1.spi.mosi	ACT #6	scb1.i2c.sda
scb1.uart.tx	ACT #8	pdm4.clk
tcpwm.line0-	ACT #1	tcpwm.line256+
scb1.spi.clk	ACT #6	scb1.i2c.scl
scb1.uart.rx	ACT #8	pdm4.data
tcpwm.line1+	ACT #1	tcpwm.line257+
m33syscpuss.fault0	ACT #3	scb4.i2c.scl
scb4.uart.rx	ACT #8	eth.txd3
tcpwm.line1-	ACT #1	tcpwm.line257-
m33syscpuss.fault1	ACT #3	scb4.spi.clk
scb4.i2c.sda	ACT #7	scb4.uart.tx
eth.rx.clk	ACT #15	ACT #15
tcpwm.line2+	ACT #1	tcpwm.line258+
lpcomp.dsi_comp1	DS #3	scb4.spi.mosi
scb4.uart.cts	ACT #8	eth.tx.er
tcpwm.line2-	ACT #1	tcpwm.line258-
lpcomp.dsi_comp0	DS #3	scb4.spi.miso
scb4.uart.rts	ACT #8	eth.tsu_timer_cmp_val
lpcomp0.in+	fixed	tcpwm.line3+
tcpwm.line259+	ACT #2	scb4.spi.select0
eth.rxd3	ACT #15	ACT #15
lpcomp0.in-	fixed	tcpwm.line3-
tcpwm.line259-	ACT #2	scb4.spi.select1
eth.rx.ctl	ACT #15	ACT #15
lpcomp1.in+	fixed	tcpwm.line4+
tcpwm.line260+	ACT #2	eth.rxd0
lpcomp1.in-	fixed	tcpwm.line4-

Table 29 (pages 58–58)

Table 29 · 3 columns × 29 rows · p.58–58 · CSV

tcpwm.line260-	ACT #2	eth.rxd1
smartio.io0	fixed	tcpwm.line5+
tcpwm.line261+	ACT #2	tdm1.tx.sck
scb6.spi.clk	ACT #6	scb6.i2c.scl
scb6.uart.rx	ACT #8	trig0.in0
trig1.in0	ACT #11	eth.rxd2
smartio.io1	fixed	tcpwm.line5-
tcpwm.line261-	ACT #2	tdm1.tx.fsync
scb6.spi.mosi	ACT #6	scb6.i2c.sda
scb6.uart.tx	ACT #8	trig0.in1
trig1.in1	ACT #11	eth.rx.er
smartio.io2	fixed	tcpwm.line6+
tcpwm.line262+	ACT #2	tdm1.tx.sd
scb6.spi.miso	ACT #6	scb6.uart.cts
trig0.in2	ACT #10	trig1.in2
eth.txd0	ACT #15	ACT #15
smartio.io3	fixed	tcpwm.line6-
tcpwm.line262-	ACT #2	tdm1.rx.mck
scb6.spi.select0	ACT #6	scb6.uart.rts
trig0.in3	ACT #10	trig1.in3
eth.txd1	ACT #15	ACT #15
smartio.io4	fixed	tcpwm.line7+
tcpwm.line263+	ACT #2	tdm1.rx.sck
scb6.spi.select1	ACT #6	eth.tx.ctl
smartio.io5	fixed	tcpwm.line7-
tcpwm.line263-	ACT #2	tdm1.rx.fsync
eth.tx.clk	ACT #15	ACT #15
smartio.io6	fixed	tcpwm.line0+
tcpwm.line264+	ACT #2	tdm1.rx.sd
eth.txd2	ACT #15	ACT #15
smartio.io7	fixed	tcpwm.line0-
tcpwm.line264-	ACT #2	tdm1.tx.mck
eth.ref.clk	ACT #15	ACT #15

Table 30 (pages 59–59)

Table 30 · 3 columns × 29 rows · p.59–59 · CSV

tcpwm.line1+	ACT #1	tcpwm.line265+
sdhost0.clk_card	ACT #15
tcpwm.line1-	ACT #1	tcpwm.line265-
sdhost0.card_dat_3to0_0	ACT #15
tcpwm.line2+	ACT #1	tcpwm.line266+
sdhost0.card_dat_3to0_1	ACT #15	ACT #15
smif[1].smif0_spihb_select3	ACT #0	tcpwm.line2-
tcpwm.line266-	ACT #2	tdm0.tx.fsync
tcpwm.line3+	ACT #1	tcpwm.line267+
sdhost0.card_dat_3to0_2	ACT #15	ACT #15
tcpwm.line3-	ACT #1	tcpwm.line267-
sdhost0.card_dat_3to0_3	ACT #15	ACT #15
aanalog.ctb1.0	fixed	fixed
aanalog.ctb1.1	fixed	tcpwm.line4+
tcpwm.line268+	ACT #2	scb7.spi.clk
scb7.i2c.scl	ACT #7	scb7.uart.rx
eth.mdc	ACT #15	ACT #15
aanalog.ctb1.2	fixed	aanalog.ctb1.opamp0.out
tcpwm.line4-	ACT #1	tcpwm.line268-
scb7.spi.mosi	ACT #6	scb7.i2c.sda
scb7.uart.tx	ACT #8	pdm1.clk
aanalog.ctb1.3	fixed	aanalog.ctb1.opamp1.out
tcpwm.line5+	ACT #1	tcpwm.line269+
scb7.spi.miso	ACT #6	scb7.uart.cts
pdm1.data	ACT #9	ACT #9
aanalog.ctb1.4	fixed	tcpwm.line5-
tcpwm.line269-	ACT #2	scb7.spi.select0
scb7.uart.rts	ACT #8	ACT #8
aanalog.ctb1.5	fixed	fixed
aanalog.ctb1.6	fixed	aanalog.dac1
tcpwm.line6+	ACT #1	tcpwm.line270+
scb7.spi.select1	ACT #6	eth.mdio
aanalog.ctb1.7	fixed	tcpwm.line6-

Table 31 (pages 60–60)

Table 31 · 3 columns × 29 rows · p.60–60 · CSV

tcpwm.line270-	ACT #2	scb8.spi.miso
scb8.uart.cts	ACT #8
aanalog.ctb0.0	fixed
aanalog.ctb0.1	fixed	tcpwm.line7+
tcpwm.line271+	ACT #2	pdm0.clk
aanalog.ctb0.2	fixed	aanalog.ctb0.opamp0.out
tcpwm.line7-	ACT #1	tcpwm.line271-
aanalog.ctb0.3	fixed	aanalog.ctb0.opamp1.out
tcpwm.line0+	ACT #1	tcpwm.line272+
scb8.spi.mosi	ACT #6	scb8.i2c.sda
scb8.uart.tx	ACT #8	ACT #8
aanalog.ctb0.4	fixed	tcpwm.line0-
tcpwm.line272-	ACT #2	scb8.spi.clk
scb8.i2c.scl	ACT #7	scb8.uart.rx
pdm0.data	ACT #9	ACT #9
aanalog.ctb0.5	fixed	fixed
aanalog.ctb0.6	fixed	aanalog.dac0
tcpwm.line1+	ACT #1	tcpwm.line273+
scb8.spi.select1	ACT #6	ACT #6
aanalog.ctb0.7	fixed	tcpwm.line1-
tcpwm.line273-	ACT #2	scb8.spi.select0
scb8.uart.rts	ACT #8	ACT #8
aanalog.ptcomp0	fixed	aanalog.sar0
tcpwm.line2+	ACT #1	tcpwm.line274+
scb9.spi.clk	ACT #6	scb9.i2c.scl
scb9.uart.rx	ACT #8	ACT #8
aanalog.ptcomp1	fixed	aanalog.sar1
tcpwm.line2-	ACT #1	tcpwm.line274-
scb9.spi.mosi	ACT #6	scb9.i2c.sda
scb9.uart.tx	ACT #8	ACT #8
aanalog.sar2	fixed	aanalog.ptcomp2
tcpwm.line3+	ACT #1	tcpwm.line275+
scb9.spi.miso	ACT #6	scb9.uart.cts

Table 32 (pages 61–61)

Table 32 · 3 columns × 29 rows · p.61–61 · CSV

aanalog.sar3	fixed	aanalog.ptcomp3
tcpwm.line3-	ACT #1	tcpwm.line275-
scb9.spi.select0	ACT #6	scb9.uart.rts
aanalog.sar4	fixed	aanalog.ptcomp4
tcpwm.line4+	ACT #1	tcpwm.line276+
scb9.spi.select1	ACT #6	ACT #6
aanalog.sar5	fixed	aanalog.ptcomp5
tcpwm.line4-	ACT #1	tcpwm.line276-
aanalog.sar6	fixed	aanalog.ptcomp6
tcpwm.line5+	ACT #1	tcpwm.line277+
aanalog.sar7	fixed	aanalog.ptcomp7
tcpwm.line5-	ACT #1	tcpwm.line277-
tcpwm.line0+	ACT #1	tcpwm.line256+
can0.rx	ACT #4	scb10.spi.clk
scb10.i2c.scl	ACT #7	scb10.uart.rx
gfx.dbi.csx	ACT #14	gfx.spi.csx
tcpwm.line1+	ACT #1	tcpwm.line257+
can0.tx	ACT #4	scb10.spi.mosi
scb10.i2c.sda	ACT #7	scb10.uart.tx
gfx.dbi.wrx	ACT #13	gfx.dbi.e
gfx.spi.scl	ACT #15	ACT #15
tcpwm.line2+	ACT #1	tcpwm.line258+
can1.rx	ACT #4	scb10.spi.miso
scb10.uart.cts	ACT #8	gfx.dbi.dcx
gfx.spi.dout	ACT #15	ACT #15
tcpwm.line3+	ACT #1	tcpwm.line259+
can1.tx	ACT #4	scb10.spi.select0
scb10.uart.rts	ACT #8	gfx.dbi.d0
gfx.spi.dcx	ACT #15	ACT #15
tcpwm.line4+	ACT #1	tcpwm.line260+
scb10.spi.select1	ACT #6	gfx.dbi.d1
tcpwm.line5+	ACT #1	tcpwm.line261+
scb5.spi.miso	ACT #6	scb5.uart.cts

Table 33 (pages 62–62)

Table 33 · 3 columns × 29 rows · p.62–62 · CSV

gfx.dbi.d2	ACT #14
tcpwm.line6+	ACT #1	tcpwm.line278+
scb5.spi.select0	ACT #6	scb5.uart.rts
gfx.dbi.d3	ACT #14
tcpwm.line7+	ACT #1	tcpwm.line279+
scb5.spi.select1	ACT #6	gfx.dbi.d4
smartio.io0	fixed	tcpwm.line0-
tcpwm.line256-	ACT #2	scb5.spi.clk
scb5.i2c.scl	ACT #7	scb5.uart.rx
gfx.dbi.d5	ACT #14	ACT #14
smartio.io1	fixed	tcpwm.line1-
tcpwm.line257-	ACT #2	scb5.spi.mosi
scb5.i2c.sda	ACT #7	scb5.uart.tx
gfx.dbi.d6	ACT #14	ACT #14
smartio.io2	fixed	tcpwm.line2-
tcpwm.line258-	ACT #2	scb11.spi.clk
scb11.i2c.scl	ACT #7	scb11.uart.rx
gfx.dbi.d7	ACT #14	ACT #14
smartio.io3	fixed	tcpwm.line3-
tcpwm.line259-	ACT #2	scb11.spi.mosi
scb11.i2c.sda	ACT #7	scb11.uart.tx
smartio.io4	fixed	tcpwm.line4-
tcpwm.line260-	ACT #2	aanalog.gpio_out0
smartio.io5	fixed	tcpwm.line5-
tcpwm.line261-	ACT #2	scb11.spi.miso
scb11.uart.cts	ACT #8	aanalog.gpio_out1
smartio.io6	fixed	tcpwm.line6-
tcpwm.line278-	ACT #2	scb11.spi.select0
scb11.uart.rts	ACT #8	aanalog.gpio_out2
smartio.io7	fixed	tcpwm.line7-
tcpwm.line279-	ACT #2	scb11.spi.select1
aanalog.gpio_out3	DS #4	DS #4
wco_out	fixed	fixed

Table 34 (pages 63–63)

Table 34 · 3 columns × 29 rows · p.63–63 · CSV

wco_in	fixed
eco_in	fixed
eco_out	fixed
tcpwm.line7+	ACT #1	tcpwm.line263-
scb1.spi.select1	ACT #6	trace.clock
tcpwm.line0+	ACT #1	tcpwm.line264-
trace.data3	ACT #15	ACT #15
tcpwm.line1+	ACT #1	tcpwm.line265-
trace.data2	ACT #15	ACT #15
tcpwm.line2+	ACT #1	tcpwm.line266-
trace.data1	ACT #15	ACT #15
tcpwm.line7-	ACT #1	tcpwm.line263+
can0.rx	ACT #4	trace.data0
aanalog.gpio_out0	DS #4	DS #4
tcpwm.line0-	ACT #1	tcpwm.line264+
can0.tx	ACT #4	aanalog.gpio_out1
tcpwm.line1-	ACT #1	tcpwm.line265+
can1.rx	ACT #4	aanalog.gpio_out2
tcpwm.line2-	ACT #1	tcpwm.line266+
can1.tx	ACT #4	aanalog.gpio_out3
tcpwm.line3+	ACT #1	tcpwm.line267+
sdhost0.card_cmd	ACT #15	ACT #15
tcpwm.line3-	ACT #1	tcpwm.line267-
tdm0.tx.sd	ACT #7	sdhost0.card_detect_n
tcpwm.line4+	ACT #1	tcpwm.line268+
tdm0.tx.sck	ACT #7	sdhost0.card_mech_write_prot
tcpwm.line4-	ACT #1	tcpwm.line268-
tdm0.tx.mck	ACT #7	sdhost0.io_volt_sel
tcpwm.line5+	ACT #1	tcpwm.line269+
scb3.spi.miso	ACT #4	scb3.uart.cts
tdm0.rx.sd	ACT #7	sdhost0.card_if_pwr_en
tcpwm.line5-	ACT #1	tcpwm.line269-
scb3.spi.mosi	ACT #4	scb3.i2c.sda

Table 35 (pages 64–64)

Table 35 · 8 columns × 25 rows · p.64–64 · CSV

scb3.uart.tx			ACT #6		tdm0.rx.fsync
tcpwm.line6+			ACT #1		tcpwm.line270+
scb3.spi.clk			ACT #4		scb3.i2c.scl
scb3.uart.rx			ACT #6		tdm0.rx.sck
smif[1].smif0_spihb_select0	smif[1].smif0_spihb_select0	smif[1].smif0_spihb_select0	ACT #0	ACT #0	tcpwm.line6-	tcpwm.line6-	tcpwm.line6-
tcpwm.line270-	tcpwm.line270-	tcpwm.line270-	ACT #2	ACT #2	scb3.spi.select1	scb3.spi.select1	scb3.spi.select1
scb3.uart.rts	scb3.uart.rts	scb3.uart.rts	ACT #6	ACT #6	tdm0.rx.mck	tdm0.rx.mck	tdm0.rx.mck
GPIO alternate functions	GPIO alternate functions	GPIO alternate functions	GPIO alternate functions	GPIO alternate functions	GPIO alternate functions	GPIO alternate functions	GPIO alternate functions
	GPIOs	Function	Function	GPIOs	GPIOs	Function
	P14.0	aanalog.ctb0.1	aanalog.ctb0.1	P14.1	P14.1	aanalog.ctb0.2
	P14.3	aanalog.ctb0.4	aanalog.ctb0.4	P14.4	P14.4	aanalog.ctb0.5
	P14.6	aanalog.ctb0.7	aanalog.ctb0.7	P14.7	P14.7	aanalog.ctb0.opamp0.out
	P14.3	aanalog.ctb1.0	aanalog.ctb1.0	P13.0	P13.0	aanalog.ctb1.1
	P13.2	aanalog.ctb1.3	aanalog.ctb1.3	P13.3	P13.3	aanalog.ctb1.4
	P13.5	aanalog.ctb1.6	aanalog.ctb1.6	P13.6	P13.6	aanalog.ctb1.7
	P13.2	aanalog.ctb1.opamp1.out	aanalog.ctb1.opamp1.out	P13.3	P13.3	aanalog.dac0
	P13.6	aanalog.gpio_out0	aanalog.gpio_out0	P17.4, P20.4	P17.4, P20.4	aanalog.gpio_out1
	P17.6, P20.6	aanalog.gpio_out3	aanalog.gpio_out3	P17.7, P20.7	P17.7, P20.7	aanalog.ptcomp0
	P15.1	aanalog.ptcomp2	aanalog.ptcomp2	P15.2	P15.2	aanalog.ptcomp3
	P15.4	aanalog.ptcomp5	aanalog.ptcomp5	P15.5	P15.5	aanalog.ptcomp6
	P15.7	aanalog.sar0	aanalog.sar0	P15.0	P15.0	aanalog.sar1
	P15.2	aanalog.sar3	aanalog.sar3	P15.3	P15.3	aanalog.sar4
	P15.5	aanalog.sar6	aanalog.sar6	P15.6	P15.6	aanalog.sar7
	P8.4	can0.rx	can0.rx	P16.0, P20.4	P16.0, P20.4	can0.tx
	P16.2, P20.6	can1.tx	can1.tx	P16.3, P20.7	P16.3, P20.7	eco_in
	P19.1	eth.mdc	eth.mdc	P13.1	P13.1	eth.mdio
	P11.7	eth.rx.clk	eth.rx.clk	P10.1	P10.1	eth.rx.ctl
	P11.1	eth.rxd0	eth.rxd0	P10.6	P10.6	eth.rxd1
	P11.0	eth.rxd3	eth.rxd3	P10.4	P10.4	eth.tsu_timer_cmp_val

Table 36 (pages 65–69)

Table 36 · 4 columns × 108 rows · p.65–69 · CSV

GPIOs	Function	GPIOs	Function
P11.5	eth.tx.ctl	P11.4	eth.tx.er
P11.2	eth.txd1	P11.3	eth.txd2
P10.0	ext_clk	P7.4	gfx.dbi.csx
P16.3	gfx.dbi.d1	P16.4	gfx.dbi.d2
P16.6	gfx.dbi.d4	P16.7	gfx.dbi.d5
P17.1	gfx.dbi.d7	P17.2	gfx.dbi.dcx
P16.1	gfx.dbi.wrx	P16.1	gfx.spi.csx
P16.3	gfx.spi.dout	P16.2	gfx.spi.scl
P8.3, P8.7	i3c.scl	P3.0	i3c.sda
P10.3	lpcomp.dsi_comp1	P10.2	lpcomp0.in+
P10.5	lpcomp1.in+	P10.6	lpcomp1.in-
P8.1	m0seccpuss.m0sec_swd	P8.0	m33syscpuss.fault0
P7.1, P10.1	pdm0.clk	P14.1	pdm0.data
P13.2	pdm1.data	P13.3	pdm2.clk
P8.4	pdm3.clk	P8.5	pdm3.data
P9.2	pdm4.data	P9.3	pdm5.clk
P9.1	scb0.i2c.scl	P8.0	scb0.i2c.sda
P8.0	scb0.spi.miso	P8.4	scb0.spi.mosi
P8.2	scb0.spi.select1	P8.3	scb1.i2c.scl
P9.2	scb1.spi.clk	P9.3	scb1.spi.miso
P9.2	scb1.spi.select0	P9.0	scb1.spi.select1
P9.1	scb1.uart.rts	P9.0	scb1.uart.rx
P9.2	scb10.i2c.scl	P16.0	scb10.i2c.sda
P16.0	scb10.spi.miso	P16.2	scb10.spi.mosi
P16.3	scb10.spi.select1	P16.4	scb10.uart.cts
P16.3	scb10.uart.rx	P16.0	scb10.uart.tx
P17.2	scb11.i2c.sda	P17.3	scb11.spi.clk
P17.5	scb11.spi.mosi	P17.3	scb11.spi.select0
P17.7	scb11.uart.cts	P17.5	scb11.uart.rts
P17.2	scb11.uart.tx	P17.3	scb2.i2c.scl
P6.7	scb2.spi.clk	P6.5	scb2.spi.miso
P6.7	scb2.spi.select0	P6.6	scb2.spi.select1
P6.4	scb2.uart.rts	P6.6	scb2.uart.rx
P6.7	scb3.i2c.scl	P21.6	scb3.i2c.sda
P21.6	scb3.spi.miso	P21.4	scb3.spi.mosi
P0.0	scb3.spi.select1	P21.7	scb3.uart.cts
P21.7	scb3.uart.rx	P21.6	scb3.uart.tx
P10.0	scb4.i2c.sda	P10.1	scb4.spi.clk
P10.3	scb4.spi.mosi	P10.2	scb4.spi.select0
P10.5	scb4.uart.cts	P10.2	scb4.uart.rts
P10.0	scb4.uart.tx	P10.1	scb5.i2c.scl
P17.1	scb5.spi.clk	P17.0	scb5.spi.miso
P17.1	scb5.spi.select0	P16.6	scb5.spi.select1
P16.5	scb5.uart.rts	P16.6	scb5.uart.rx
P17.1	scb6.i2c.scl	P11.0	scb6.i2c.sda
P11.0	scb6.spi.miso	P11.2	scb6.spi.mosi
P11.3	scb6.spi.select1	P11.4	scb6.uart.cts
P11.3	scb6.uart.rx	P11.0	scb6.uart.tx
P13.1	scb7.i2c.sda	P13.2	scb7.spi.clk
P13.3	scb7.spi.mosi	P13.2	scb7.spi.select0
P13.6	scb7.uart.cts	P13.3	scb7.uart.rts
P13.1	scb7.uart.tx	P13.2	scb8.i2c.scl
P14.3	scb8.spi.clk	P14.4	scb8.spi.miso
P14.3	scb8.spi.select0	P14.7	scb8.spi.select1
P13.7	scb8.uart.rts	P14.7	scb8.uart.rx
P14.3	scb9.i2c.scl	P15.0	scb9.i2c.sda
P15.0	scb9.spi.miso	P15.2	scb9.spi.mosi
P15.3	scb9.spi.select1	P15.4	scb9.uart.cts
P15.3	scb9.uart.rx	P15.0	scb9.uart.tx
P21.0	sdhost0.card_dat_3to0_0	P12.1	sdhost0.card_dat_3to0_1
P12.4	sdhost0.card_dat_3to0_3	P12.5	sdhost0.card_detect_n
P21.4	sdhost0.card_mech_write_prot	P21.2	sdhost0.clk_card
P21.3	sdhost1.card_cm d	P7.0	sdhost1.card_dat_3to0_0
P7.5	sdhost1.card_dat_3to0_2	P7.6	sdhost1.card_dat_3to0_3
P6.4	sdhost1.card_dat_7to4_1	P6.5	sdhost1.card_dat_7to4_2
P6.7	sdhost1.card_detect_n	P7.4	sdhost1.card_emmc_reset_n
P6.2	sdhost1.card_mech_write_prot:0	P6.0	sdhost1.card_mech_write_prot:1
P7.1	sdhost1.io_volt_s el	P6.3	sdhost1.led_ctrl
P11.0, P17.0	smartio.io1	P11.1, P17.1	smartio.io2
P11.3, P17.3	smartio.io4	P11.4, P17.4	smartio.io5
P11.6, P17.6	smartio.io7	P11.7, P17.7	smif[0].smif0_spihb_select0
P2.0	smif[0].smif0_spihb_select2	P6.7	smif[0].smif0_spihb_select3
P21.7	smif[1].smif0_spihb_select1	P0.0	smif[1].smif0_spihb_select2
P12.3	swj.swclk/tclk	P6.3	swj.swdio/tms
P6.1	swj.tdo	P6.0	swj.trstn
P0.0, P4.3/ SMIF1.3, P7.2, P9.1, P11.6, P14.3, P16.0, P20.1	tcpwm.line0-	P0.1, P4.4/ SMIF1.4, P7.3, P9.3, P11.7, P14.4, P17.0, P20.5	tcpwm.line1+
P1.1/SMIF0.1, P4.6/SMIF1.6, P7.5, P10.1, P12.1, P14.7, P17.1, P20.6	tcpwm.line2+	P1.2/SMIF0.2, P4.7/SMIF1.7, P7.6, P10.2, P12.2, P15.0, P16.2, P20.3	tcpwm.line2-
P0.0, P9.3, P16.0	tcpwm.line256-	P0.1, P9.1, P17.0	tcpwm.line257+
P1.1/SMIF0.1, P10.1, P17.1	tcpwm.line258+	P1.2/SMIF0.2, P10.2, P16.2	tcpwm.line258-
P1.4/SMIF0.4, P10.4, P16.3	tcpwm.line259-	P1.5/SMIF0.5, P10.5, P17.3	tcpwm.line260+
P1.7/SMIF0.7, P10.7, P17.4	tcpwm.line261+	P2.0, P11.0, P16.5	tcpwm.line261-
P3.1, P11.2	tcpwm.line262-	P4.0/SMIF1.0, P11.3	tcpwm.line263+
P4.2/SMIF1.2, P11.5, P20.0	tcpwm.line264+	P4.3/SMIF1.3, P11.6, P20.5	tcpwm.line264-
P4.5/SMIF1.5, P12.0, P20.6	tcpwm.line265-	P4.6/SMIF1.6, P12.1, P20.2	tcpwm.line266+
P5.0, P12.3, P20.3	tcpwm.line267+	P6.0, P12.4, P21.0	tcpwm.line267-
P6.2, P13.1, P21.2	tcpwm.line268-	P6.3, P13.2, P21.3	tcpwm.line269+
P6.5, P13.4, P21.5	tcpwm.line270+	P6.6, P13.6, P21.6	tcpwm.line270-
P7.0, P14.1	tcpwm.line271-	P7.1, P14.2	tcpwm.line272+
P7.3, P14.4	tcpwm.line273+	P7.4, P14.6	tcpwm.line273-
P7.6, P15.0	tcpwm.line274-	P7.7, P15.1	tcpwm.line275+
P8.1, P15.3	tcpwm.line276+	P8.2, P15.4	tcpwm.line276-
P8.4, P15.6	tcpwm.line277-	P8.5, P15.7	tcpwm.line278+
P8.7, P17.6	tcpwm.line279+	P9.2, P16.7	tcpwm.line279-
P1.4/SMIF0.4, P6.0, P8.0, P10.4, P12.4, P15.2, P16.3, P21.0	tcpwm.line3-	P1.5/SMIF0.5, P6.1, P8.1, P10.5, P12.5, P15.3, P17.3, P21.1	tcpwm.line4+
P1.7/SMIF0.7, P6.3, P8.3, P10.7, P13.2, P15.5, P17.4, P21.3	tcpwm.line5+	P2.0, P6.4, P8.4, P11.0, P13.3, P15.6, P16.5, P21.4	tcpwm.line5-
P3.1, P6.6, P8.6, P11.2, P13.6, P16.6, P21.6	tcpwm.line6-	P4.0/SMIF1.0, P6.7, P8.7, P11.3, P13.7, P17.6, P21.7	tcpwm.line7+
P4.2/SMIF1.2, P7.1, P9.2, P11.5, P14.2, P17.7, P20.4	tdm0.rx.fsync	P21.5	tdm0.rx.mck
P21.6	tdm0.rx.sd	P21.4	tdm0.tx.fsync
P21.3	tdm0.tx.sck	P21.2	tdm0.tx.sd
P11.5	tdm1.rx.mck	P11.3	tdm1.rx.sck
P11.6	tdm1.tx.fsync	P11.1	tdm1.tx.mck
P11.0	tdm1.tx.sd	P11.2	trace.clock
P4.4/SMIF1.4, P20.4	trace.data1	P4.5/SMIF1.5, P20.3	trace.data2
P4.7/SMIF1.7, P20.1	trig0.in0	P11.0	trig0.in1
P11.2	trig0.in3	P11.3	trig0.in4
P7.6	trig0.in6	P7.7	trig0.in7
P7.0	trig0.out1	P7.1	trig1.in0
P11.1	trig1.in2	P11.2	trig1.in3
P7.5	trig1.in5	P7.6	trig1.in6
P8.0	trig1.out0	P7.0	trig1.out1
P18.1	wco_out	P18.0

Table 37 (pages 70–70)

Table 37 · 6 columns × 13 rows · p.70–70 · CSV

Parameter	Symbol	Values			Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
Supply for SRSS	VDDD	-0.5	-	2.4	V
Current per GPIO	IGPIO_ABS	-25	-	25	mA
GPIO injection current per pin	IGPlO_injecti on	-0.5	-	0.5	mA
Electrostatic discharge Human Body Model	ESD_HBM	2000	-	-	V
Electrostatic discharge Charged Device Model	ESD_CDM	500	-	-	V
Pin current for latchup free operation	LU	-100	-	100	mA
DC supply for the VBAT supply	VBAT	-0.5	-	5.5	V
DC supply voltage for digital I/O	VDDIO	-0.5	-	2.4	V
DC supply voltage for high voltage digital I/O	VDDIO6	-0.5	-	4.1	V
DC supply voltage for core	VCCD	-0.5	-	1.2	V
Maximum undershoot voltage for I/O	Vundershoot	-	-	-0.5	V
Maximum overshoot voltage for I/O	Vovershoot	-	-	VDDIO+0.5	V
Maximum junction temperature	Tj	-	-	125	°C

Table 38 (pages 72–72)

Table 38 · 2 columns × 27 rows · p.72–72 · CSV

State
Disabled	DMA
Off
RRAM	All
Sleep	RRAM
Off
Default state	See
Quad SPI
VCCD core = 0.9 V:	VCCD core = 0.9 V:
State	State
System HP	System HP
= 0.8 V:	= 0.8 V:
State	State
System LP	System LP
VCCD core = 0.7 V:	VCCD core = 0.7 V:
State	State
System ULP	System ULP
Disabled	Disabled
CLK_PATH3	CLK_PATH3
State	State
On	On
Off	Off
1	1
Disabled	Disabled
Disabled	Disabled
All disabled	All disabled
All disabled	All disabled
Off	Off
Off	Off

Table 39 (pages 74–74)

Description	Description	Symbol	Symbol	Values	Values	Values	Values	Values	Values	Unit	Unit	Note or test	Note or test
Description	Description	Symbol	Symbol	Min.	Min.	Typ.	Typ.	Max.	Max.	Unit	Unit	Note or test	Note or test
Analog Supply Voltage	Analog Supply Voltage	VDDA	VDDA	1.71	1.71	1.8	1.8	1.89	1.89	V	V
USB Supply Voltage	USB Supply Voltage	VDDUSB	VDDUSB	3.07	3.07	3.3	3.3	3.63	3.63	V	V
CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8
	Description	Description	CM33 (MHz)	CM33 (MHz)	CM55 (MHz)	CM55 (MHz)	IBAT	IBAT	IBAT	IBAT	IDDD	IDDD	IDDD
	Description	Description	CM33 (MHz)	CM33 (MHz)	CM55 (MHz)	CM55 (MHz)	Typical	Typical	Max 70°C	Max 70°C	Typical	Typical	Max 70°C
Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)
			200	200	-	-	1.9	1.9	5.5	5.5	0.8	0.8	1.2
			70	70	-	-	1.2	1.2	4.7	4.7	0.8	0.8	1.2
execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled
			200	200	-	-	4.0	4.0	7.7	7.7	0.8	0.8	1.2
			70	70	-	-	1.9	1.9	5.5	5.5	0.8	0.8	1.2
execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]
			3.1	3.1	-	-	0.9	0.9	4.2	4.2	0.2	0.2	0.3
execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM
			200	200	-	-	4.4	4.4	8.0	8.0	0.6	0.6	0.8
			70	70	-	-	2.1	2.1	5.5	5.5	0.6	0.6	0.8
Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off
			200	200	400	400	7.9	7.9	21.3	21.3	0.9	0.9	1.5
			70	70	140	140	4.1	4.1	17.2	17.2	0.9	0.9	1.4
execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM
			200	200	400	400	12.3	12.3	22.6	22.6	2.3	2.3	3.5
			70	70	140	140	5.7	5.7	15.7	15.7	1.8	1.8	2.6
(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off
			200	200	400	400	9.1	9.1	25.9	25.9	1.0	1.0	1.4
			70	70	140	140	4.8	4.8	21.2	21.2	0.9	0.9	1.3

Table 40 (pages 75–78)

Table 39 · 14 columns × 25 rows · p.74–74 · CSV

Description		Symbol		Values						Unit		Note or test
Description		Symbol		Min.		Typ.		Max.		Unit		Note or test
Analog Supply Voltage	Analog Supply Voltage	VDDA	VDDA	1.71	1.71	1.8	1.8	1.89	1.89	V	V
USB Supply Voltage	USB Supply Voltage	VDDUSB	VDDUSB	3.07	3.07	3.3	3.3	3.63	3.63	V	V
CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8	CPU currents, active modes, battery powered configuration, VBAT=3.3 V, VDDD=1.8
	Description	Description	CM33 (MHz)	CM33 (MHz)	CM55 (MHz)	CM55 (MHz)	IBAT	IBAT	IBAT	IBAT	IDDD	IDDD	IDDD
	Description	Description	CM33 (MHz)	CM33 (MHz)	CM55 (MHz)	CM55 (MHz)	Typical	Typical	Max 70°C	Max 70°C	Typical	Typical	Max 70°C
Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)	Performance) mode (See condition details above), VCCD = 0.9 V Power Domain), PD1 = Off (High Performance Domain) (See condition details above) (RRAM)
			200	200	-	-	1.9	1.9	5.5	5.5	0.8	0.8	1.2
			70	70	-	-	1.2	1.2	4.7	4.7	0.8	0.8	1.2
execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled	execute from RRAM, RRAM enabled
			200	200	-	-	4.0	4.0	7.7	7.7	0.8	0.8	1.2
			70	70	-	-	1.9	1.9	5.5	5.5	0.8	0.8	1.2
execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	execute while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]
			3.1	3.1	-	-	0.9	0.9	4.2	4.2	0.2	0.2	0.3
execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM	execute from SRAM
			200	200	-	-	4.4	4.4	8.0	8.0	0.6	0.6	0.8
			70	70	-	-	2.1	2.1	5.5	5.5	0.6	0.6	0.8
Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (See condition details above) (RRAM), CM55 + U55 Off
			200	200	400	400	7.9	7.9	21.3	21.3	0.9	0.9	1.5
			70	70	140	140	4.1	4.1	17.2	17.2	0.9	0.9	1.4
execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	execute external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]APP_MMIO1 = Only SMIF enabled, APP_MMIO2 = Disable SOCMEM
			200	200	400	400	12.3	12.3	22.6	22.6	2.3	2.3	3.5
			70	70	140	140	5.7	5.7	15.7	15.7	1.8	1.8	2.6
(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off
			200	200	400	400	9.1	9.1	25.9	25.9	1.0	1.0	1.4
			70	70	140	140	4.8	4.8	21.2	21.2	0.9	0.9	1.3

Table 42 · 5 columns × 131 rows · p.80–84 · CSV

Description	CM33 (MHz)	CM55 (MHz)	IDDD
Description	CM33 (MHz)	CM55 (MHz)	Typical	Max 70°C
Performance) mode (See condition details above), VCCD = 0.9 V Domain), PD1 = Off (High Performance Domain) (See condition details above)
	200	-	4.3	10.3
	70	-	3.0	8.8
	50	-	2.7	8.6
from RRAM, RRAM enabled	from RRAM, RRAM enabled	from RRAM, RRAM enabled	from RRAM, RRAM enabled	from RRAM, RRAM enabled
	200	-	8.2	14.4
	70	-	4.3	10.2
	50	-	3.7	9.6
while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]
	3.1	-	1.8	8.2
from SRAM	from SRAM	from SRAM	from SRAM	from SRAM
	200	-	8.8	14.6
	70	-	4.4	11.0
	50	-	3.7	9.8
Domain), PD1 = On (High Performance Domain) (See condition details above) + U55 Off	Domain), PD1 = On (High Performance Domain) (See condition details above) + U55 Off	Domain), PD1 = On (High Performance Domain) (See condition details above) + U55 Off	Domain), PD1 = On (High Performance Domain) (See condition details above) + U55 Off	Domain), PD1 = On (High Performance Domain) (See condition details above) + U55 Off
	200	400	5.9	32.4
	70	140	16.2	44.2
	50	140	8.6	36.2
external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM
	200	400	25.5	47.2
	70	140	12.5	33.5
CPU Sleep, U55 Off	CPU Sleep, U55 Off	CPU Sleep, U55 Off	CPU Sleep, U55 Off	CPU Sleep, U55 Off
	200	400	19.2	51.4
	70	140	9.8	46.6
+ U55 CPU Sleep, U55 = Enabled, APP_MMIO2 = Enable SOCMEM and U55	+ U55 CPU Sleep, U55 = Enabled, APP_MMIO2 = Enable SOCMEM and U55	+ U55 CPU Sleep, U55 = Enabled, APP_MMIO2 = Enable SOCMEM and U55	+ U55 CPU Sleep, U55 = Enabled, APP_MMIO2 = Enable SOCMEM and U55	+ U55 CPU Sleep, U55 = Enabled, APP_MMIO2 = Enable SOCMEM and U55
	200	400	18.6	53.3
	70	140	10.0	44.2
Active execute from RRAM, U55 Off, RRAM enabled	Active execute from RRAM, U55 Off, RRAM enabled	Active execute from RRAM, U55 Off, RRAM enabled	Active execute from RRAM, U55 Off, RRAM enabled	Active execute from RRAM, U55 Off, RRAM enabled
	200	400	30.0	64.9
	70	140	13.9	36.1
Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, clk_hf[0,1,2] divider = 16	Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, clk_hf[0,1,2] divider = 16	Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, clk_hf[0,1,2] divider = 16	Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, clk_hf[0,1,2] divider = 16	Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, clk_hf[0,1,2] divider = 16
	3.1	3.1	5.2	25.8
Active execute from System SRAM, U55 Off	Active execute from System SRAM, U55 Off	Active execute from System SRAM, U55 Off	Active execute from System SRAM, U55 Off	Active execute from System SRAM, U55 Off
	200	400	32.9	78.7
	70	140	14.5	46.4
Active execute from System SRAM, System SRAM = 300 MHz, U55 Off, DPLL_LP1 = MHz, clk_hf[2] source = DPLL_LP1	Active execute from System SRAM, System SRAM = 300 MHz, U55 Off, DPLL_LP1 = MHz, clk_hf[2] source = DPLL_LP1	Active execute from System SRAM, System SRAM = 300 MHz, U55 Off, DPLL_LP1 = MHz, clk_hf[2] source = DPLL_LP1	Active execute from System SRAM, System SRAM = 300 MHz, U55 Off, DPLL_LP1 = MHz, clk_hf[2] source = DPLL_LP1	Active execute from System SRAM, System SRAM = 300 MHz, U55 Off, DPLL_LP1 = MHz, clk_hf[2] source = DPLL_LP1
	200	400	29.4	68.6
Active execute from TCM, U55 Off	Active execute from TCM, U55 Off	Active execute from TCM, U55 Off	Active execute from TCM, U55 Off	Active execute from TCM, U55 Off
	200	400	31.6	69.4
	70	140	14.2	46.7
Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache disabled, APP_MMIO1 = Only SMIF enabled	Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache disabled, APP_MMIO1 = Only SMIF enabled	Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache disabled, APP_MMIO1 = Only SMIF enabled	Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache disabled, APP_MMIO1 = Only SMIF enabled	Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache disabled, APP_MMIO1 = Only SMIF enabled
	200	400	36.4	63.3
	70	140	16.9	40.7
from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off
	200	400	32.5	63.7
	70	140	14.7	41.6
CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, APP_MMIO2U55	CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, APP_MMIO2U55	CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, APP_MMIO2U55	CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, APP_MMIO2U55	CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, APP_MMIO2U55
	200	400	47.5	73.5
	70	140	21.6	47.1
Power) mode, VCCD = 0.8 V Domain), PD1 = Off (High Performance Domain)	Power) mode, VCCD = 0.8 V Domain), PD1 = Off (High Performance Domain)	Power) mode, VCCD = 0.8 V Domain), PD1 = Off (High Performance Domain)	Power) mode, VCCD = 0.8 V Domain), PD1 = Off (High Performance Domain)	Power) mode, VCCD = 0.8 V Domain), PD1 = Off (High Performance Domain)
	70	-	2.2	5.7
	50	-	2.0	5.6
	70	-	3.2	6.8
	50	-	2.7	6.3
while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]
	3.1	-	1.1	4.5
from SRAM	from SRAM	from SRAM	from SRAM	from SRAM
	70	-	3.1	6.7
DPLL=70 MHz, clk_hf[0] divider = 2	35	-	2.2	5.8
	50	-	2.6	6.1
Domain), PD1 = On (High Performance Domain) + U55 Off	Domain), PD1 = On (High Performance Domain) + U55 Off	Domain), PD1 = On (High Performance Domain) + U55 Off	Domain), PD1 = On (High Performance Domain) + U55 Off	Domain), PD1 = On (High Performance Domain) + U55 Off
	70	140	5.6	19.8
	50	50	3.9	17.9
external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM
	70	140	8.8	28.5
clk_hf[0] divider = 1	50	50	7.4	28.5
CPU Sleep, U55 Off	CPU Sleep, U55 Off	CPU Sleep, U55 Off	CPU Sleep, U55 Off	CPU Sleep, U55 Off
	70	140	6.4	21.0
clk_hf[0] divider = 1	50	50	4.4	18.7
+ U55 CPU Sleep, U55 = Enabled, APP_MMIO2 = Enable SOCMEM and U55	+ U55 CPU Sleep, U55 = Enabled, APP_MMIO2 = Enable SOCMEM and U55	+ U55 CPU Sleep, U55 = Enabled, APP_MMIO2 = Enable SOCMEM and U55	+ U55 CPU Sleep, U55 = Enabled, APP_MMIO2 = Enable SOCMEM and U55	+ U55 CPU Sleep, U55 = Enabled, APP_MMIO2 = Enable SOCMEM and U55
	70	140	6.6	24.9
clk_hf[0] divider = 1	50	50	4.5	22.8
Active execute from RRAM, U55 Off, RRAM enabled	Active execute from RRAM, U55 Off, RRAM enabled	Active execute from RRAM, U55 Off, RRAM enabled	Active execute from RRAM, U55 Off, RRAM enabled	Active execute from RRAM, U55 Off, RRAM enabled
	70	140	9.2	28.1
clk_hf[0] divider = 1	50	50	5.4	24.0
Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, clk_hf[0,1,2] divider = 16	Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, clk_hf[0,1,2] divider = 16	Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, clk_hf[0,1,2] divider = 16	Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, clk_hf[0,1,2] divider = 16	Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, clk_hf[0,1,2] divider = 16
	3.1	3.1	2.9	18.6
Active execute from System SRAM, U55 Off	Active execute from System SRAM, U55 Off	Active execute from System SRAM, U55 Off	Active execute from System SRAM, U55 Off	Active execute from System SRAM, U55 Off
	70	140	9.5	27.5
clk_hf[0] divider = 1	50	50	5.4	21.8
Active execute from TCM, U55 Off	Active execute from TCM, U55 Off	Active execute from TCM, U55 Off	Active execute from TCM, U55 Off	Active execute from TCM, U55 Off
	70	140	9.2	27.4
clk_hf[0] divider = 1	50	50	5.3	23.2
Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache disabled, APP_MMIO1 = Only SMIF enabled	Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache disabled, APP_MMIO1 = Only SMIF enabled	Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache disabled, APP_MMIO1 = Only SMIF enabled	Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache disabled, APP_MMIO1 = Only SMIF enabled	Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache disabled, APP_MMIO1 = Only SMIF enabled
	70	140	11.8	32.5
clk_hf[0] divider = 1	50	50	6.8	32.5
from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off
	70	140	13.1	30.7
clk_hf[0] divider = 1	50	50	5.9	21.9
CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, APP_MMIO2U55	CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, APP_MMIO2U55	CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, APP_MMIO2U55	CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, APP_MMIO2U55	CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, APP_MMIO2U55
	70	140	16.2	33.7
clk_hf[0] divider = 1	50	50	8.8	26.4
Low Power) mode, VCCD = 0.7 V Domain), PD1 = Off (High Performance Domain)	Low Power) mode, VCCD = 0.7 V Domain), PD1 = Off (High Performance Domain)	Low Power) mode, VCCD = 0.7 V Domain), PD1 = Off (High Performance Domain)	Low Power) mode, VCCD = 0.7 V Domain), PD1 = Off (High Performance Domain)	Low Power) mode, VCCD = 0.7 V Domain), PD1 = Off (High Performance Domain)
	50	-	1.3	3.9
clk_hf[0] divider = 2	25	-	1.3	3.9
from RRAM. RRAM enabled	from RRAM. RRAM enabled	from RRAM. RRAM enabled	from RRAM. RRAM enabled	from RRAM. RRAM enabled
	50	-	2.0	4.7
clk_hf[0] divider = 2	25	-	1.6	4.2
while(1) from SRAM, CM33=3.1 MHz, DPLL_LP0 = Disabled, clk_hf[0,1,2] source =	while(1) from SRAM, CM33=3.1 MHz, DPLL_LP0 = Disabled, clk_hf[0,1,2] source =	while(1) from SRAM, CM33=3.1 MHz, DPLL_LP0 = Disabled, clk_hf[0,1,2] source =	while(1) from SRAM, CM33=3.1 MHz, DPLL_LP0 = Disabled, clk_hf[0,1,2] source =	while(1) from SRAM, CM33=3.1 MHz, DPLL_LP0 = Disabled, clk_hf[0,1,2] source =
	3.1	-	1.0	3.6
from SRAM	from SRAM	from SRAM	from SRAM	from SRAM
	50	-	2.3	5.0
clk_hf[0] divider = 2	25	-	1.8	4.5
Domain), PD1 = On (High Performance Domain) + U55 Off	Domain), PD1 = On (High Performance Domain) + U55 Off	Domain), PD1 = On (High Performance Domain) + U55 Off	Domain), PD1 = On (High Performance Domain) + U55 Off	Domain), PD1 = On (High Performance Domain) + U55 Off
clk_hf[0] divider = 1	50	50	2.7	12.9
clk_hf[0,1,2] divider = 2	25	25	3.1	13.3
external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM
clk_hf[0] divider = 1	50	50	6.4	28.5
clk_hf[0,1,2] divider = 2	25	25	4.8	16.4
CPU Sleep, U55 Off	CPU Sleep, U55 Off	CPU Sleep, U55 Off	CPU Sleep, U55 Off	CPU Sleep, U55 Off
clk_hf[0] divider = 1	50	50	3.5	16.2
clk_hf[0,1,2] divider = 2	25	25	3.0	15.8
+ U55 CPU Sleep, U55 = Enabled, APP_MMIO2 = Enable SOCMEM and U55	+ U55 CPU Sleep, U55 = Enabled, APP_MMIO2 = Enable SOCMEM and U55	+ U55 CPU Sleep, U55 = Enabled, APP_MMIO2 = Enable SOCMEM and U55	+ U55 CPU Sleep, U55 = Enabled, APP_MMIO2 = Enable SOCMEM and U55	+ U55 CPU Sleep, U55 = Enabled, APP_MMIO2 = Enable SOCMEM and U55
clk_hf[0] divider = 1	50	50	3.6	16.8
clk_hf[0,1,2] divider = 2	25	25	3.1	16.2
Active execute from RRAM, U55 Off, RRAM enabled	Active execute from RRAM, U55 Off, RRAM enabled	Active execute from RRAM, U55 Off, RRAM enabled	Active execute from RRAM, U55 Off, RRAM enabled	Active execute from RRAM, U55 Off, RRAM enabled
clk_hf[0] divider = 1	50	50	4.1	16.8
clk_hf[0,1,2] divider = 2	25	25	3.4	16.2
Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, clk_hf[0,1,2] divider = 16	Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, clk_hf[0,1,2] divider = 16	Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, clk_hf[0,1,2] divider = 16	Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, clk_hf[0,1,2] divider = 16	Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, clk_hf[0,1,2] divider = 16
	3.1	3.1	2.4	15.0
Active execute from System SRAM, U55 Off	Active execute from System SRAM, U55 Off	Active execute from System SRAM, U55 Off	Active execute from System SRAM, U55 Off	Active execute from System SRAM, U55 Off
clk_hf[0,1,2] divider = 1	50	50	4.4	17.3
clk_hf[0,1,2] divider = 2	25	25	3.3	16.0
Active execute from TCM, U55 Off	Active execute from TCM, U55 Off	Active execute from TCM, U55 Off	Active execute from TCM, U55 Off	Active execute from TCM, U55 Off
clk_hf[0] divider = 1	50	50	4.3	16.5
clk_hf[0,1,2] divider = 2	25	25	3.3	15.4
Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache disabled, APP_MMIO1 = Only SMIF enabled	Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache disabled, APP_MMIO1 = Only SMIF enabled	Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache disabled, APP_MMIO1 = Only SMIF enabled	Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache disabled, APP_MMIO1 = Only SMIF enabled	Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache disabled, APP_MMIO1 = Only SMIF enabled
clk_hf[0] divider = 1	50	50	5.8	17.7
clk_hf[0,1,2] divider = 2	25	25	4.5	17.7
from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off
clk_hf[0] divider = 1	50	50	4.6	17.1
clk_hf[0,1,2] divider = 2	25	25	3.5	15.9

Table 41 (pages 79–79)

Table 41 · 5 columns × 17 rows · p.79–79 · CSV

Description	IBAT		IDDD
Description	Typical	Max 70°C	Typical	Max 70°C
Core buck regulator enabled, VDDIO currents not included, VCCD = 0.7 V
System Deep Sleep, 64 KB SRAM retention, PD1 Disabled	26.1	194.2	4.2	11.8
System Deep Sleep, 512 KB SRAM retention, PD1 Disabled	28.2	230.3	4.1	15.1
System Deep Sleep, 1 M SRAM retention, PD1 Disabled	30.6	225.0	4.0	11.6
System Deep Sleep, 64 KB SRAM retention, PD1 Enabled, CM55 Disabled	29.5	264.9	4.0	15.2
System Deep Sleep, 64 KB SRAM + 512 kB System SRAM retention, PD1 Enabled, CM55 Disabled	31.9	282.1	4.0	15.6
System Deep Sleep, 64 kB SRAM + 1024 kB System SRAM+TCM retention, PD1 and CM55 Enabled	41.6	367.1	4.0	15.5
System Deep Sleep, 64 KB SRAM + 5.5MB System SRAM+TCM retention, PD1 and CM55 Enabled	60.8	493.6	4.0	15.8
System Deep Sleep, 1 MB SRAM + 5.5 MB System SRAM+TCM retention, PD1 and CM55 Enabled	65.3	508.9	4.0	12.0
System Deep Sleep-RAM, 64 KB SRAM retention, PD1 Disabled	21.7	158.2	3.9	19.2
System Deep Sleep-RAM, 1M SRAM retention, PD1 Disabled	26.3	186.8	3.9	19.2
System Deep Sleep-RAM, 64 kB SRAM +512 kB System SRAM, PD1 Enabled	26.7	188.3	3.9	72.4
System Deep Sleep-RAM, 64 kB SRAM+ 5.0 MB System SRAM retention, PD1 Enabled	45.9	382.2	4.0	18.2
System Deep Sleep-OFF, PD1 Disabled	20.7	152.7	3.9	18.7
VDDIO currents not included	VDDIO currents not included	VDDIO currents not included	VDDIO currents not included	VDDIO currents not included
No Clocks	0.3	0.9	1.6	16.5
PILO+WDT	0.3	0.7	2.6	9.6
WCO+RTC	0.3	0.7	1.9	8.7

Table 42 (pages 80–84)

Table 40 · 7 columns × 106 rows · p.75–78 · CSV

Description	CM33 (MHz)	CM55 (MHz)	IBAT		IDDD
Description	CM33 (MHz)	CM55 (MHz)	Typical	Max 70°C	Typical	Max 70°C
	200	400	9.4	26.8	1.0	1.5
	70	140	4.9	21.8	0.9	1.4
(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled
	200	400	15.4	32.7	1.0	1.5
	70	140	7.0	23.5	0.9	1.4
(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16
	3.1	3.1	2.6	14.8	0.3	0.7
(RRAM), CM55 Active execute from System SRAM, U55 Off	(RRAM), CM55 Active execute from System SRAM, U55 Off	(RRAM), CM55 Active execute from System SRAM, U55 Off	(RRAM), CM55 Active execute from System SRAM, U55 Off	(RRAM), CM55 Active execute from System SRAM, U55 Off	(RRAM), CM55 Active execute from System SRAM, U55 Off	(RRAM), CM55 Active execute from System SRAM, U55 Off
	200	400	15.8	29.7	0.8	1.2
	70	140	7.0	20.8	0.7	1.1
(RRAM), CM55 Active execute from System SRAM, System SRAM = 300 MHz, U55 Off, DPLL_LP1 freq = 300 MHz, clk_hf[2] source = DPLL_LP1	(RRAM), CM55 Active execute from System SRAM, System SRAM = 300 MHz, U55 Off, DPLL_LP1 freq = 300 MHz, clk_hf[2] source = DPLL_LP1	(RRAM), CM55 Active execute from System SRAM, System SRAM = 300 MHz, U55 Off, DPLL_LP1 freq = 300 MHz, clk_hf[2] source = DPLL_LP1	(RRAM), CM55 Active execute from System SRAM, System SRAM = 300 MHz, U55 Off, DPLL_LP1 freq = 300 MHz, clk_hf[2] source = DPLL_LP1	(RRAM), CM55 Active execute from System SRAM, System SRAM = 300 MHz, U55 Off, DPLL_LP1 freq = 300 MHz, clk_hf[2] source = DPLL_LP1	(RRAM), CM55 Active execute from System SRAM, System SRAM = 300 MHz, U55 Off, DPLL_LP1 freq = 300 MHz, clk_hf[2] source = DPLL_LP1	(RRAM), CM55 Active execute from System SRAM, System SRAM = 300 MHz, U55 Off, DPLL_LP1 freq = 300 MHz, clk_hf[2] source = DPLL_LP1
	200	400	16.4	31.6	1.2	1.8
(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off
	200	400	15.8	29.7	0.8	1.3
	70	140	7.1	20.6	0.7	1.2
(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled
	200	400	17.9	31.3	2.4	3.6
	70	140	7.9	20.5	1.9	2.7
from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off
	200	400	15.9	29.7	0.8	1.2
	70	140	7.1	20.6	0.7	1.0
(RRAM), CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, Enable SOCMEM and U55	(RRAM), CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, Enable SOCMEM and U55	(RRAM), CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, Enable SOCMEM and U55	(RRAM), CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, Enable SOCMEM and U55	(RRAM), CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, Enable SOCMEM and U55	(RRAM), CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, Enable SOCMEM and U55	(RRAM), CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, Enable SOCMEM and U55
	200	400	24.1	36.3	2.5	3.5
	70	140	10.2	21.7	2.1	2.6
Power) mode, VCCD = 0.8 V Power Domain), PD1 = Off (High Performance Domain) (RRAM)	Power) mode, VCCD = 0.8 V Power Domain), PD1 = Off (High Performance Domain) (RRAM)	Power) mode, VCCD = 0.8 V Power Domain), PD1 = Off (High Performance Domain) (RRAM)	Power) mode, VCCD = 0.8 V Power Domain), PD1 = Off (High Performance Domain) (RRAM)	Power) mode, VCCD = 0.8 V Power Domain), PD1 = Off (High Performance Domain) (RRAM)	Power) mode, VCCD = 0.8 V Power Domain), PD1 = Off (High Performance Domain) (RRAM)	Power) mode, VCCD = 0.8 V Power Domain), PD1 = Off (High Performance Domain) (RRAM)
	70	-	0.9	3.8	0.7	1.1
	50	-	0.8	3.7	0.7	1.1
from RRAM, RRAM enabled	from RRAM, RRAM enabled	from RRAM, RRAM enabled	from RRAM, RRAM enabled	from RRAM, RRAM enabled	from RRAM, RRAM enabled	from RRAM, RRAM enabled
	70	-	1.5	4.6	0.7	1.1
	50	-	1.3	4.3	0.7	1.1
while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]	while(1) from SRAM, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, clk_hf[0]
	3.1	-	0.6	3.6	0.2	0.3
from SRAM	from SRAM	from SRAM	from SRAM	from SRAM	from SRAM	from SRAM
	70	-	1.6	4.1	0.4	0.6
	50	-	1.3	3.7	0.4	0.6
Power Domain), PD1 = On (High Performance Domain) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (RRAM), CM55 + U55 Off	Power Domain), PD1 = On (High Performance Domain) (RRAM), CM55 + U55 Off
	70	140	3.7	16.4	0.7	1.1
	50	50	2.4	15.1	0.6	0.9
external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM
	70	140	4.6	13.9	1.7	2.3
clk_hf[0] divider = 1	50	50	3.8	14.8	1.5	2.0
(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off
	70	140	3.7	16.4	0.7	1.1
clk_hf[0] divider = 1	50	50	2.4	15.1	0.6	0.9
(RRAM), CM55 + U55 CPU Sleep (RRAM), U55 = Enabled, APP_MMIO2 = Enable SOCMEM and	(RRAM), CM55 + U55 CPU Sleep (RRAM), U55 = Enabled, APP_MMIO2 = Enable SOCMEM and	(RRAM), CM55 + U55 CPU Sleep (RRAM), U55 = Enabled, APP_MMIO2 = Enable SOCMEM and	(RRAM), CM55 + U55 CPU Sleep (RRAM), U55 = Enabled, APP_MMIO2 = Enable SOCMEM and	(RRAM), CM55 + U55 CPU Sleep (RRAM), U55 = Enabled, APP_MMIO2 = Enable SOCMEM and	(RRAM), CM55 + U55 CPU Sleep (RRAM), U55 = Enabled, APP_MMIO2 = Enable SOCMEM and	(RRAM), CM55 + U55 CPU Sleep (RRAM), U55 = Enabled, APP_MMIO2 = Enable SOCMEM and
	70	140	3.9	17.0	0.7	3.3
clk_hf[0] divider = 1	50	50	2.6	15.6	0.6	0.9
(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled
	70	140	5.7	18.6	0.7	1.0
clk_hf[0] divider = 1	50	50	3.1	15.9	0.6	1.0
(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16
	3.1	3.1	1.7	12.3	0.2	0.3
	70	140	5.9	18.0	0.5	0.8
clk_hf[0] divider = 1	50	50	3.3	13.9	0.4	0.7
(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off
	70	140	5.8	15.8	0.5	0.7
clk_hf[0] divider = 1	50	50	3.1	12.9	0.4	1.2
(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled
	70	140	6.5	18.1	1.7	2.4
clk_hf[0] divider = 1	50	50	3.3	14.0	1.6	2.0
from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off
	70	140	5.7	16.5	0.6	0.8
clk_hf[0] divider = 1	50	50	3.2	13.7	0.5	0.8
(RRAM), CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, Enable SOCMEM and U55	(RRAM), CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, Enable SOCMEM and U55	(RRAM), CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, Enable SOCMEM and U55	(RRAM), CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, Enable SOCMEM and U55	(RRAM), CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, Enable SOCMEM and U55	(RRAM), CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, Enable SOCMEM and U55	(RRAM), CM55+U55 Active execute EMBCC AudioMark from System SRAM, U55 = Enabled, Enable SOCMEM and U55
	70	140	7.3	14.4	2.1	2.5
clk_hf[0] divider = 1	50	50	3.7	10.8	1.5	1.9
Low Power) mode, VCCD = 0.7 V Power Domain), PD1 = Off (High Performance Domain) (RRAM)	Low Power) mode, VCCD = 0.7 V Power Domain), PD1 = Off (High Performance Domain) (RRAM)	Low Power) mode, VCCD = 0.7 V Power Domain), PD1 = Off (High Performance Domain) (RRAM)	Low Power) mode, VCCD = 0.7 V Power Domain), PD1 = Off (High Performance Domain) (RRAM)	Low Power) mode, VCCD = 0.7 V Power Domain), PD1 = Off (High Performance Domain) (RRAM)	Low Power) mode, VCCD = 0.7 V Power Domain), PD1 = Off (High Performance Domain) (RRAM)	Low Power) mode, VCCD = 0.7 V Power Domain), PD1 = Off (High Performance Domain) (RRAM)
	50	-	0.6	2.8	0.4	0.7
clk_hf[0] divider = 2	25	-	0.6	2.8	0.4	0.7
from RRAM. RRAM enabled	from RRAM. RRAM enabled	from RRAM. RRAM enabled	from RRAM. RRAM enabled	from RRAM. RRAM enabled	from RRAM. RRAM enabled	from RRAM. RRAM enabled
	50	-	1.0	3.4	0.4	0.7
clk_hf[0] divider = 2	25	-	0.8	3.0	0.4	0.7
while(1) from SRAM, CM33=3.1 MHz, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, 16	while(1) from SRAM, CM33=3.1 MHz, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, 16	while(1) from SRAM, CM33=3.1 MHz, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, 16	while(1) from SRAM, CM33=3.1 MHz, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, 16	while(1) from SRAM, CM33=3.1 MHz, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, 16	while(1) from SRAM, CM33=3.1 MHz, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, 16	while(1) from SRAM, CM33=3.1 MHz, DPLL_LP0 = Disabled, clk_hf[0,1,2] source = CLK_PATH3, 16
	3.1	-	0.5	2.5	0.2	0.2
from SRAM	from SRAM	from SRAM	from SRAM	from SRAM	from SRAM	from SRAM
	50	-	1.1	2.9	0.4	0.6
clk_hf[0] divider = 2	25	-	0.8	2.4	0.4	0.6
(RRAM), CM55 + U55 Off	(RRAM), CM55 + U55 Off	(RRAM), CM55 + U55 Off	(RRAM), CM55 + U55 Off	(RRAM), CM55 + U55 Off	(RRAM), CM55 + U55 Off	(RRAM), CM55 + U55 Off
clk_hf[0] divider = 1	50	50	1.7	8.6	0.4	0.7
clk_hf[0,1,2] divider = 2	25	25	1.4	8.3	0.4	0.7
external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM	external Flash octal SPI, SMIF = enabled, SMIF cache disabled, CM55 + U55 Off, clk_hf[3]= Only SMIF enabled, APP_MMIO2 = Disable SOCMEM
clk_hf[0] divider = 1	50	50	3.0	11.9	1.5	2.0
clk_hf[0,1,2] divider = 2	25	25	2.2	10.8	1.2	1.6
(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off	(RRAM), CM55 CPU Sleep (RRAM), U55 Off
clk_hf[0] divider = 1	50	50	1.9	10.6	0.4	0.7
clk_hf[0,1,2] divider = 2	25	25	1.6	10.3	0.4	0.7
(RRAM), CM55 + U55 CPU Sleep (RRAM), U55 = Enabled, APP_MMIO2 = Enable SOCMEM and	(RRAM), CM55 + U55 CPU Sleep (RRAM), U55 = Enabled, APP_MMIO2 = Enable SOCMEM and	(RRAM), CM55 + U55 CPU Sleep (RRAM), U55 = Enabled, APP_MMIO2 = Enable SOCMEM and	(RRAM), CM55 + U55 CPU Sleep (RRAM), U55 = Enabled, APP_MMIO2 = Enable SOCMEM and	(RRAM), CM55 + U55 CPU Sleep (RRAM), U55 = Enabled, APP_MMIO2 = Enable SOCMEM and	(RRAM), CM55 + U55 CPU Sleep (RRAM), U55 = Enabled, APP_MMIO2 = Enable SOCMEM and	(RRAM), CM55 + U55 CPU Sleep (RRAM), U55 = Enabled, APP_MMIO2 = Enable SOCMEM and
clk_hf[0] divider = 1	50	50	2.0	11.0	0.4	1.5
clk_hf[0,1,2] divider = 2	25	25	1.7	10.6	0.4	0.7
(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled	(RRAM), CM55 Active execute from RRAM, U55 Off, RRAM enabled
clk_hf[0] divider = 1	50	50	2.5	10.4	0.4	0.7
clk_hf[0,1,2] divider = 2	25	25	1.9	10.6	0.4	0.7
(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16	(RRAM), CM55 Active execute while(1) from System SRAM, U55 Off, DPLL_LP0 = Disabled, = CLK_PATH3, clk_hf[0,1,2] divider = 16
	3.1	3.1	1.3	9.4	0.2	0.3
(RRAM), CM55 Active execute from System SRAM, U55 Off	(RRAM), CM55 Active execute from System SRAM, U55 Off	(RRAM), CM55 Active execute from System SRAM, U55 Off	(RRAM), CM55 Active execute from System SRAM, U55 Off	(RRAM), CM55 Active execute from System SRAM, U55 Off	(RRAM), CM55 Active execute from System SRAM, U55 Off	(RRAM), CM55 Active execute from System SRAM, U55 Off
clk_hf[0,1,2] divider = 1	50	50	2.6	10.8	0.2	0.4
clk_hf[0,1,2] divider = 2	25	25	2.0	9.9	0.2	0.4
(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off	(RRAM), CM55 Active execute from TCM, U55 Off
clk_hf[0] divider = 1	50	50	2.4	9.4	0.2	0.3
clk_hf[0,1,2] divider = 2	25	25	1.8	8.7	0.2	0.3
(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled	(RRAM), CM55 Active execute from external Flash octal SPI, SMIF = enabled, SMIF cache = Enabled, APP_MMIO1 = Only SMIF enabled
clk_hf[0] divider = 1	50	50	2.6	11.0	1.6	2.0
clk_hf[0,1,2] divider = 2	25	25	2.0	10.2	1.2	1.5
from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off	from SRAM, CM55 Active execute from System SRAM, U55 Off
clk_hf[0] divider = 1	50	50	2.5	10.3	0.2	0.4
clk_hf[0,1,2] divider = 2	25	25	1.9	9.7	0.2	0.4

Table 43 (pages 85–85)

Table 43 · 3 columns × 17 rows · p.85–85 · CSV

Description	IDDD
Description	Typical	Max 70°C
buck regulator enabled, VDDIO currents not included, VCCD = 0.7 V
System Deep Sleep, 64 KB SRAM retention, PD1 Disabled	46.3	328.3
System Deep Sleep, 512 KB SRAM retention, PD1 Disabled	49.8	406.3
System Deep Sleep, 1 M SRAM retention, PD1 Disabled	53.9	381.5
System Deep Sleep, 64 KB SRAM retention, PD1 Enabled, CM55 Disabled	51.8	453.5
System Deep Sleep, 64 KB SRAM + 512 kB System SRAM retention, PD1 Enabled, CM55 Disabled	55.9	487.8
System Deep Sleep, 64 kB SRAM + 1024 kB System SRAM+TCM retention, PD1 and CM55 Enabled	72.9	652.5
System Deep Sleep, 64 KB SRAM + 5.5 MB System SRAM+TCM retention, PD1 and CM55 Enabled	106.4	923.4
System Deep Sleep, 1 MB SRAM + 5.5 MB System SRAM+TCM retention, PD1 and CM55 Enabled	114.5	867.4
System Deep Sleep-RAM, 64 KB SRAM retention, PD1 Disabled	37.9	286.8
System Deep Sleep-RAM, 1 M SRAM retention, PD1 Disabled	46.1	350.6
System Deep Sleep-RAM, 64 kB SRAM + 512 kB System SRAM, PD1 Enabled	46.8	360.8
System Deep Sleep-RAM, 64 kB SRAM + 5.0 MB System SRAM retention, PD1 Enabled	80.2	642.0
System Deep Sleep-OFF, PD1 Disabled	36.1	274.4
currents not included	currents not included	currents not included
No Clocks	5.6	10.5
ILO+WDT	6.7	11.5
WCO+RTC	5.7	10.0

Table 44 (pages 86–86)

Table 44 · 5 columns × 26 rows · p.86–86 · CSV

Parameter	Min	Max
Parameter	Min	HP	LP	ULP
CLK_HF[0] – SYSCPUSS, CM33	0	200	80	50
CLK_HF[1] – APPCPUSS, GFXSS (GPU, DC), CM55, U55	0	400	140	50
CLK_HF[2] -SoCMEM	0	300	110	50
CLK_HF[3] – SMIF[0]	0	400	200	50
CLK_HF[4] – SMIF[1]	0	400	200	50
CLK_HF[5] – SDHC[0], Ethernet	0	208	104	50
CLK_HF[6] – SDHC[1], Ethernet	0	208	104	50
CLK_HF[7] – I2S, TDM, PDM	0	100	50	25
CLK_HF[8] -USB	0	50	50	N/A
CLK_HF[9] – Analog, DACs	0	100	50	25
CLK_HF[10] – SCB[0, 2-11], CAN, TCPWMs, SMARTI/O	0	100	40	25
CLK_HF[11] – SCB[1], I3C	0	200	80	50
CLK_HF[12] – MIPI DSI D-PHY PLL reference clock	0	64	N/A	N/A
CLK_HF[13] – I3C	0	125	60	25
Power mode transition times	Power mode transition times	Power mode transition times	Power mode transition times	Power mode transition times
Description	Paramet er	Min	Typ	Max
times	times	times	times	times
System HP to LP transition time	THP_LP	-	65	78
System HP to ULP transition time	THP_ULP	-	108	110
System LP to ULP transition time	TLP_ULP	-	40	41
System ULP to LP transition time	TULP_LP	-	53	55
System ULP to HP transition time	TULP_HP	-	114	115
System LP to HP transition time	TLP_HP	-	49	62
System Deep Sleep to Active ULP transition time	TDS_ACT	-	27	30
System Deep Sleep to Active LP transition time	TDS_ACT	-	27	28
System Deep Sleep to Active HP transition time	TDS_ACT	-	28	40

Table 45 (pages 87–87)

Table 45 · 12 columns × 15 rows · p.87–87 · CSV

	Description			Paramet er		Min		Typ		Max
	System Deep Sleep-RAM to Active transition time	System Deep Sleep-RAM to Active transition time	System Deep Sleep-RAM to Active transition time	TDSR_ACT	TDSR_ACT	-	-	25.5	25.5	-	-
	System Deep Sleep-OFF to Active transition time	System Deep Sleep-OFF to Active transition time	System Deep Sleep-OFF to Active transition time	TDSO_ACT	TDSO_ACT	-	-	25.5	25.5	-	-
	System Hibernate to Active transition time	System Hibernate to Active transition time	System Hibernate to Active transition time	THIB_ACT	THIB_ACT	-	-	25.5	25.5	-	-
XRES XRES	XRES XRES	XRES XRES	XRES XRES	XRES XRES	XRES XRES	XRES XRES	XRES XRES	XRES XRES	XRES XRES	XRES XRES	XRES XRES
Parameter	Parameter	Symbol	Values	Values	Values	Values	Values	Values	Unit	Unit	Note or condition
Parameter	Parameter	Symbol	Min.	Min.	Typ.	Typ.	Max.	Max.	Unit	Unit	Note or condition
Low) Specifications Specifications	Low) Specifications Specifications	Low) Specifications Specifications	Low) Specifications Specifications	Low) Specifications Specifications	Low) Specifications Specifications	Low) Specifications Specifications	Low) Specifications Specifications	Low) Specifications Specifications	Low) Specifications Specifications	Low) Specifications Specifications	Low) Specifications Specifications
POR or XRES release to Active transition time	POR or XRES release to Active transition time	TXRESACT	-	-	25.5	25.5	-	-	ms	ms	From release Extended Does not required Extended (Cold
XRES Pulse width	XRES Pulse width	TXRESPW	5	5	-	-	-	-	µs	µs
Time to establish valid voltage levels before XRES Release	Time to establish valid voltage levels before XRES Release	TXRESPWR	60	60	-	-	-	-	µs	µs
Boot AC -From start of extended boot to start of main.c	Boot AC -From start of extended boot to start of main.c	Boot AC -From start of extended boot to start of main.c	Boot AC -From start of extended boot to start of main.c	Boot AC -From start of extended boot to start of main.c	Boot AC -From start of extended boot to start of main.c	Boot AC -From start of extended boot to start of main.c	Boot AC -From start of extended boot to start of main.c	Boot AC -From start of extended boot to start of main.c	Boot AC -From start of extended boot to start of main.c	Boot AC -From start of extended boot to start of main.c	Boot AC -From start of extended boot to start of main.c
Non secure boot	Non secure boot	TEXBOOT	-	-	29	29	-	-	ms	ms	No initial
Secure boot. 100 KB internal	Secure boot. 100 KB internal	TEXBOOT	-	-	200	200	-	-	ms	ms	Authenticate initial in RRAM
Secure boot. 100 KB external	Secure boot. 100 KB external	TEXBOOT	-	-	217	217	-	-	ms	ms	Authenticate initial in Octal
Secure boot. 5 MB external	Secure boot. 5 MB external	TEXBOOT	-	-	932	932	-	-	ms	ms	Authenticate initial in Octal

Table 46 (pages 88–90)

Table 46 · 6 columns × 67 rows · p.88–90 · CSV

Parameter	Symbol	Values			Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
Specifications
IBAT when XRES asserted	TXRESIBAT	-	0.3	-	µA
IDDD when XRES asserted	TXRESIDDD	-	1.1	-	µA
IDDD when XRES asserted	TXRESIDDD	-	1.2	-	µA
Input Voltage high threshold	VIH	0.7*VDD	-	-	V
Input Voltage low threshold	VIL	-	-	0.3*VDD	V
Input Capacitance	CIN	-	3	-	pF
Input voltage hysteresis	VHYSXRES	-	100	-	mV
Current through protection diode to VDD/Vss	DIODE	-	-	100	µA
GPIO GPIO	GPIO GPIO	GPIO GPIO	GPIO GPIO	GPIO GPIO	GPIO GPIO
Parameter	Symbol	Values	Values	Values	Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
Specifications Specifications	Specifications Specifications	Specifications Specifications	Specifications Specifications	Specifications Specifications	Specifications Specifications
Input Voltage high threshold	VIH	0.7*VDD	-	-	v
Input current when Pad > VDDIO for OVT inputs	lihs	-	-	10	µA
Input Voltage low threshold	VIL	-	-	0.3*VDD	V
Output Voltage high level	VOH	VDD-O.5	-	-	V
Output Voltage low level	VOL	-	-	0.4	V
Pull-up resistor	RPULLUP	-	50	-	kΩ
Pull-down resistor	RPULLDOWN	-	50	-	kΩ
Input leakage current(absolute value)	IL	-	-	2	nA
Input Capacitance	CIN	-	-	5	pF
Input hysteresis CMOS	VHYSCMOS	0.05*VDD	-	-	mV
Current through protection diode to VDD/VSS	DIODE	-	-	100	C
Maximum Total Source or Sink Chip Current	ITOTGPIO	-	-	200	mA
Rise time in Fast Strong Mode. 10% to 90% of VDD	TRISEF	-	-	2.5	ns
Fall time in Fast Strong Mode. 10% to 90% of VDD	TFALLF	-	-	2.5	ns
Fall time (30% to 70% ofVDD) in Slow Strong mode	TFALL12C	20*VDDIO/5.5	-	250	ns
GPIO Fout. Fast Strong mode	FGPIOUT1	-	-	100	MHz
GPIO Fout. Slow Strong mode	FGPIOUT2	-	-	5	MHz
GPIO Fout. Fast Strong mode	FGPIOUT3	-	-	100	MHz
GPIO Fout. Slow Strong mode	FGPIOUT4	-	-	5	MHz
GPIO input operating frequency. 1.71 V<=VDDIO <= 1.89 V	FGPIOIN	-	-	100	MHz
GPIO Specifications Specifications	GPIO Specifications Specifications	GPIO Specifications Specifications	GPIO Specifications Specifications	GPIO Specifications Specifications	GPIO Specifications Specifications
Input Voltage high threshold	VIH	0.7*VDD	-	-	V
Input current when Pad > VDDIO for OVT inputs	lihs	-	-	10	µA
Input Voltage low threshold	VIL	-	-	0.3*VDD	V
Output Voltage high level	VOH	VDD-O.5	-	-	V
Output Voltage low level	VOL	-	-	0.4	V
Pull-up resistor	RPULLUP	-	50	-	kΩ
Pull-down resistor	RPULLDOWN	-	50	-	kΩ
Input leakage current (absolute value)	IIL	-	-	2	nA
Input Capacitance	CIN	-	-	5	pF
Input hysteresis CMOS	VHYSCMOS	0.05*VDD	-	-	mV
Current through protection diode to VDD/VSS	IDIODE	-	-	100	µA
Maximum Total Source or Sink Chip Current	ITOTGPIO	-	-	200	mA
Rise time in Fast Strong Mode. 10% to 90% of VDD	TRISEF	-	-	1.2	ns
Fall time in Fast Strong Mode. 10% to 90% of VDD	TFALLF	-	-	1.2	ns
GPIO Fout. Fast Strong mode	FGPIOUT1	-	-	208	MHz
GPIO Fout. Fast Strong mode	FGPIOUT3	-	-	208	MHz
GPIO input operating frequency. 1.71 V<=VDD<=1.89 V	FGPIOIN	-	-	208	MHz
Specifications Specifications	Specifications Specifications	Specifications Specifications	Specifications Specifications	Specifications Specifications	Specifications Specifications
Input Voltage high threshold	VIH	0.7*VDD	-	-	V
Input current when Pad > VDDIO for OVT inputs	lihs	-	-	10	µA
Input Voltage low threshold	VIL	-	-	0.3*VDD	V
Output Voltage high level	VOH	VDD-O.5	-	-	V
Output Voltage low level	VOL	-	-	0.4	V
Pull-up resistor	RPULLUP	-	50	-	kΩ
Pull-down resistor	RPULLDOWN	-	50	-	kΩ
Input leakage current (absolute value)	IIL	-	-	2	nA
Input Capacitance	CIN	-	-	5	pF
Input hysteresis CMOS	VHYSCMOS	0.05*VDD	-	-	mV
Current through protection diode to VDD/VSS	DIODE	-	-	100	µA
Maximum Total Source or Sink Chip Current	ITOT_GPIO	-	-	200	mA
Specifications	Specifications	Specifications	Specifications	Specifications	Specifications
Rise time in Fast Strong Mode. 10% to 90% of VDD	TRISEF	-	-	5	ns
Fall time in Fast Strong Mode. 10% to 90% of VDD	TFALLF	-	-	5	ns
GPIO Fout. Fast Strong mode	FGPIOUT1	-	-	50	MHz

Table 47 (pages 91–92)

Table 47 · 6 columns × 32 rows · p.91–92 · CSV

Parameter	Symbol	Values			Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
GPIO Fout, Slow Strong mode	FGPIOUT2	-	-	0.8	MHz
GPIO Fout. Fast Strong mode	FGPIOUT3	-	-	50	MHz
GPIO Fout. Slow Strong mode	FGPIOUT4	-	-	0.8	MHz
GPIO input operating frequency. 1.71 V<=VDD<=3.6 V	FGPIOIN	-	-	50	MHz
Analog peripherals Autonomous analog specifications Autonomous analog specifications	Analog peripherals Autonomous analog specifications Autonomous analog specifications	Analog peripherals Autonomous analog specifications Autonomous analog specifications	Analog peripherals Autonomous analog specifications Autonomous analog specifications	Analog peripherals Autonomous analog specifications Autonomous analog specifications	Analog peripherals Autonomous analog specifications Autonomous analog specifications
Description	Symbol	Values	Values	Values	Unit
Description	Symbol	Min.	Typ.	Max.	Unit
Analog Supply Voltage	VDD18	1.71	1.8	1.89	V
Current Consumption for VAD (PTComp + CTB Opamp + ADC, 12b-16 ksps)	ITOT-Audio	-	100	-	µA
Power Down Current for the Autonomous Analog	IleakLPPASS	-	1	-	µA
Start Up time of Autonomous Analog from power down	Tstart Up	-	25	-	µs
DC Specifications	DC Specifications	DC Specifications	DC Specifications	DC Specifications	DC Specifications
Input offset voltage for COMPI. Normal power mode	VOFFSET1	-5	-	5	mV
Input offset voltage. Low-power mode	VOFFSET2	-10	-	10	mV
Input offset voltage. Ultra low-power mode	VOFFSET3	-10	-	10	mV
Hysteresis when enabled in Normal mode	VHYST1	-	-	60	mV
Hysteresis when enabled in Low-power mode	VHYST2	-	-	80	mV
Input common mode voltage in Normal mode	VICM1	0	-	VDDIO1-0.1	V
Input common mode voltage in Low power mode	VICM2	0	-	VDDIO1-0.1	V
Input common mode voltage in Ultra low power mode	VICM3	0	-	VDDIO1-0.1	V
Common mode rejection ratio in Normal power mode	CMRR	50	-	-	dB
Power Supply Rejection Ratio ≤500 kHz	PSRR	55	-	-	dB
Block Current, Normal mode	ICMP1	-	-	150	µA
Block Current, Low power mode	ICMP2	-	-	10	µA
Block Current in Ultra low power mode	ICMP3	-	0.3	0.85	µA
DC Input impedance of comparator	ZCMP	35	-	-	MΩ
AC Specifications	AC Specifications	AC Specifications	AC Specifications	AC Specifications	AC Specifications
Response time, Normal mode, 100 mV overdrive	TRESP1	-	-	100	ns
Response time, Low power mode, 100 mV overdrive	TRESP2	-	-	1000	ns
Response time, Ultra-low power mode, 100 mV overdrive	TRESP3	-	-	7	µs
Time from Enabling to operation	TCMPEN1	-	-	10	µs
Time from Enabling to operation	TCMPEN2	-	-	50	µs

Table 48 (pages 93–95)

Table 48 · 6 columns × 46 rows · p.93–95 · CSV

Description	Symbol	Values			Unit
Description	Symbol	Min.	Typ.	Max.	Unit
Numerical resolution of ADC results	Res	12	-	20	bits
Conversion Rate of ADC in HS mode, continous conversion of one channel	CR1	-	-	4	Msps
Conversion Rate of ADC in HS mode, continous conversion of four channels with simultaneous sampling	CR2	-	-	5	Msps
Conversion Rate of ADC in LP mode (system Deep Sleep mode), continous conversion of one channel	CR3	-	-	200	ksps
Clock of ADC in HS mode (available only in system Active mode)	ADCClkHF	4.1	-	80	MHz
Clock of ADC in LP mode (available in system Deep Sleep mode)	ADCClkLP	-	4.1	-	MHz
GPIOs, ADC unbuffered (Buffers bypassed)	GPIOs, ADC unbuffered (Buffers bypassed)	GPIOs, ADC unbuffered (Buffers bypassed)	GPIOs, ADC unbuffered (Buffers bypassed)	GPIOs, ADC unbuffered (Buffers bypassed)	GPIOs, ADC unbuffered (Buffers bypassed)
Average current from VDDA for ADC in HS mode, all channels	IDDA_HS	-	-	3.05	mA
Average VDDA current for ADC in LP mode, 100% duty cycled	IDDA_LP	-	-	410	µA
Differential input voltage range of LP ADC	VDIFFSAR	-VREF	-	VREF	V
Input common mode voltage of HS/LP ADC	VICMSAR	-	-	VDDA	V
Input leakage current of ADC in HS mode while sampling	ip_leak_h s	-	-	450	nA
INL of ADC in HS mode	INL_hs	-2	-	2	LSBs
DNL of ADC in HS mode	DNL_hs	-1	-	2	LSBs
Analog offset of ADC in HS mode, calibrated	ofst_hs	-1	-	1	mV
Gain error of ADC in HS mode, with internal bandgap reference (VBGR, 0.9 V)	gerr_hs	-1	-	1	%
Input leakage current of ADC in LP mode while sampling	ip_leak_l p	-350	-	350	nA
INL of ADC in LP mode	INL_lp	-2	-	2	LSBs
DNL of ADC in LP mode	DNL_lp	-1	-	2	LSBs
Analog offset of ADC in LP mode, calibrated	ofst_lp	-1	-	1	mV
Gain error of ADC in LP mode, with internal bandgap reference (VBGR, 0.9 V)	gerr_lp	-1	-	1	%
SINAD of ADC in HS mode, VDDA as reference, 4 Msps, 80 MHz clock	SINADHF12b	-	63	-	dB
SINAD of ADC in HS mode, with VDDA as the reference, 125 ksps with 32 samples accumulated (16 b), 80 MHz clock	SINADHF16b	-	75	-	dB
GPIOs, ADC buffered (Buffer in Low, Rail to Rail power mode)	GPIOs, ADC buffered (Buffer in Low, Rail to Rail power mode)	GPIOs, ADC buffered (Buffer in Low, Rail to Rail power mode)	GPIOs, ADC buffered (Buffer in Low, Rail to Rail power mode)	GPIOs, ADC buffered (Buffer in Low, Rail to Rail power mode)	GPIOs, ADC buffered (Buffer in Low, Rail to Rail power mode)
Average current from VDDA for ADC in HS mode, one channel	IDDA_HS	-	-	3.2	mA
Average current from VDDA for ADC in LP mode, 100% duty cycled	IDDA_LP	-	-	650	µA
Average current from VDDA for ADC in LP mode, 16 ksps, duty cycled	IDDA_LP_16 ksps	-	-	50	µA
Average current from VDDA for ADC in LP mode, 1 ksps, duty cycled	ITOT-HRV	-	20	-	µA
Offset voltage of ADC buffer	ofst_buffe r	-1	-	1	mV
Gain error of ADC buffer	gerr_buff er	-0.1	-	0.1	%
Temperature sensor accuracy	temp_acc	-5	-	5	°C
Temperature sensor Current from VDDA	temp_idd a	-	-	4	µA
Input leakage of ADC buffers	ip_leak	-150	-	150	nA
INL of ADC in HS mode, with internal bandgap reference (VBGR, 0.9 V)	INL_hs	-2	-	2	LSBs
DNL of ADC in HS mode, with internal bandgap reference (VBGR, 0.9 V)	DNL_hs	-1	-	2	LSBs
Analog offset of ADC in HS mode and buffer combined	ofst_chan_hs	-2	-	2	mV
Gain error of ADC in HS mode and buffer combined, with internal bandgap reference (VBGR, 0.9 V)	gerr_chan_hs	-1	-	1	%
Gain error of ADC in HS mode and buffer combined, with external (off-chip) reference	gerr_chan_hs_ext	-1	-	1	%
INL of ADC in LP mode, with internal bandgap reference (VBGR, 0.9 V)	INL_lp	-2	-	2	LSBs
DNL of ADC in LP mode, with internal bandgap reference (VBGR, 0.9 V)	DNL_lp	-1	-	2	LSBs
Analog offset of ADC in LP mode and buffer combined	ofst_chan_lp	-2	-	2	mV
Gain error of ADC in LP mode and buffer combined, with internal bandgap reference (VBGR, 0.9 V)	gerr_chan_lp	-1	-	1	%
Gain error of ADC in LP mode and buffer combined, with external (off-chip) reference	gerr_chan_lp_ext	-1	-	1	%
Startup time of ADC channel buffers	t_buff_sta rtup	-	5	-	µS
Settling time at input of ADC, differential input swing from VDDA-400 mV to VDDA+400 mV	t_settle	-	2	-	µS
Temperature sensor startup time, from enabled to settled at ADC input	temp_star tup	-	15	-	µS

Table 49 (pages 96–96)

Table 49 · 13 columns × 16 rows · p.96–96 · CSV

	Description	Symbol		Values						Unit
	Description	Symbol	Symbol	Min.	Min.	Typ.	Typ.	Max.	Max.	Unit	Unit	Unit
	Bandgap reference voltage (VBGR)	VREF	VREF	-	-	0.9	0.9	-	-	V	V	V
	Current from VDDA for the bandgap reference	IDD_VBG	IDD_VBG	-	-	25	25	50	50	µA	µA	µA
	Percentage variation of the bandgap voltage at room temperature, with respect to VDDA, trimmed (Vmax-Vmin)/Vtyp x 100	VBG_VDD	VBG_VDD	-0.3	-0.3	-	-	0.3	0.3	%	%	%
	Bandgap voltage temperature coefficient, trimmed [-40°C,125°C] temp co =(Vmax-Vmin)/ {Vnom x (Tmax-Tmin)} x 1E6	VBG_TEMPJ	VBG_TEMPJ	-	-	-	-	40	40	ppm/°C	ppm/°C	ppm/°C
DAC DAC	DAC DAC	DAC DAC	DAC DAC	DAC DAC	DAC DAC	DAC DAC	DAC DAC	DAC DAC	DAC DAC	DAC DAC	DAC DAC	DAC DAC
Parameter	Parameter	Parameter	Symbol	Symbol	Values	Values	Values	Values	Values	Values	Unit
Parameter	Parameter	Parameter	Symbol	Symbol	Min.	Min.	Typ.	Typ.	Max.	Max.	Unit
Numerical Resolution of DAC	Numerical Resolution of DAC	Numerical Resolution of DAC	DACRES	DACRES	-	-	-	-	12	12	bits
Settling time of buffered DAC with a 25 pF load capacitance	Settling time of buffered DAC with a 25 pF load capacitance	Settling time of buffered DAC with a 25 pF load capacitance	DACCONV	DACCONV	-	-	-	-	2	2	µs
Maximum Refresh Rate of DAC	Maximum Refresh Rate of DAC	Maximum Refresh Rate of DAC	DACRate	DACRate	-	-	-	-	1.024	1.024	MHz
Current from VDDA, unbuffered DAC ("Direct" topologies), VDDA reference	Current from VDDA, unbuffered DAC ("Direct" topologies), VDDA reference	Current from VDDA, unbuffered DAC ("Direct" topologies), VDDA reference	IDDA_ctdac_v ddaref	IDDA_ctdac_v ddaref	-	-	92	92	133	133	µA
Current from VDDA, unbuffered DAC ("Direct" topologies), internal bandgap reference (VBGR, 0.9 V)	Current from VDDA, unbuffered DAC ("Direct" topologies), internal bandgap reference (VBGR, 0.9 V)	Current from VDDA, unbuffered DAC ("Direct" topologies), internal bandgap reference (VBGR, 0.9 V)	IDDA_ctdac_vref0p9	IDDA_ctdac_vref0p9	-	-	418	418	700	700	µA
Current from VDDA buffered DAC (buffer power mode: Medium), VDDA as reference	Current from VDDA buffered DAC (buffer power mode: Medium), VDDA as reference	Current from VDDA buffered DAC (buffer power mode: Medium), VDDA as reference	IDDA_ctdac_buf_vddaref	IDDA_ctdac_buf_vddaref	-	-	2288	2288	3100	3100	µA
Current from VDDA, buffered DAC (buffer power mode: Medium), internal bandgap reference (VBGR, 0.9 V)	Current from VDDA, buffered DAC (buffer power mode: Medium), internal bandgap reference (VBGR, 0.9 V)	Current from VDDA, buffered DAC (buffer power mode: Medium), internal bandgap reference (VBGR, 0.9 V)	IDDA_ctdac_buf_vref0p9	IDDA_ctdac_buf_vref0p9	-	-	2493	2493	3500	3500	µA
Average current from VDDA, buffered DAC (buffer power mode: Ultra-Low), 10% duty cycle, Sample and Hold enabled, VDDA reference	Average current from VDDA, buffered DAC (buffer power mode: Ultra-Low), 10% duty cycle, Sample and Hold enabled, VDDA reference	Average current from VDDA, buffered DAC (buffer power mode: Ultra-Low), 10% duty cycle, Sample and Hold enabled, VDDA reference	IDDA_duty_ctdac_buf_sh_ vddaref	IDDA_duty_ctdac_buf_sh_ vddaref	-	-	25	25	80	80	µA

Table 50 (pages 97–112)

Table 50 · 6 columns × 295 rows · p.97–112 · CSV

Parameter	Symbol	Values			Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
Average current from VDDA, buffered DAC (buffer power mode: Ultra-Low), 10% duty cycle, Sample and Hold enabled, internal bandgap reference (VBGR, 0.9 V)	IDDA_duty_ctdac_buf_sh_vref0p9	-	448	710	µA
Average current from VDDD for DAC	IDDD_dac	-	1	7	µA
Integral Non-Linearity of DAC	DACINL	-4	-	4	LSBs
Differential Non-Linearity of DAC	DACDNL	-2	-	2	LSBs
Offset error with input code = 0x000 unsigned	DACOFFSET	-10	-	10	mV
Gain error of unbuffered DAC	GAINERR	-1	-	1	%
Gain error of buffered DAC	GAINERR_BUF	-1	-	1	%
Output resistance of unbuffered DAC	RO_enable	5	-	16	kΩ
Output impedance of buffered DAC	DACOUTRES	-	-	1	Ω
Value of Sample and Hold capacitors combined	DACCAP	-	-	50	pF
Output voltage range of unbuffered DAC	VRANGE	0	-	VDDA	V
Output voltage range of buffered DAC, buffer in a "rail to rail" power mode	VRANGE_BUF	0.2	-	VDDA-1VDDA-0. 2*	V
DC PSRR of buffered output	PSRR	-	-40	-	dB
DAC offset (output when input code = 0x000 unsigned, with respect to the VSSA)	Offset	-	-	3	mV
Drift in DAC offset across temperature (-40°C to 125°C) at constant code input and VDDA	Offset Drift	-	20	-	µV/C
Temperature coefficient of DAC output voltage (mid-scale code) (-40°C to 125°C)	Tempco	-	-	20	V/C
Analog output settling time of DAC from disabled state, VDDA reference	tsen_vddaref	-	-	1.4	µs
Analog output settling time of DAC from disabled state, internal bandgap reference (VBGR, 0.9 V)	tsen_vre0p9	-	-	1.4	µs
Maximum hold time	thold	100	-	-	µs
Wake-Up time (from enabling to ready for conversion)	DACWakeup	-	-	10	µs
CTBL Op Amp CTBL Op Amp	CTBL Op Amp CTBL Op Amp	CTBL Op Amp CTBL Op Amp	CTBL Op Amp CTBL Op Amp	CTBL Op Amp CTBL Op Amp	CTBL Op Amp CTBL Op Amp
Parameter	Symbol	Values	Values	Values	Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
VDDA for one Opamp, Output driving a pin	VDDA for one Opamp, Output driving a pin	VDDA for one Opamp, Output driving a pin	VDDA for one Opamp, Output driving a pin	VDDA for one Opamp, Output driving a pin	VDDA for one Opamp, Output driving a pin
Ultra-Low power mode, input common mode voltage from 0.2 to VDDA-1 V	Idd_ultralow_10x	-	15	45	µA
Ultra-Low power mode, Rail-to-Rail inputs, input common mode voltage 0.2 to VDDA-0.2 V	Idd_ultralow_10x	-	35	60	µA
Low power mode, Rail-to-Rail inputs, input common mode voltage 0.2 to VDDA-0.2 V	Idd_low_10x	-	150	200	µA
Medium power mode, Rail-to-Rail inputs, input common mode voltage 0.2 to VDDA-0.2 V	Idd_med_10x	-	300	350	µA
High power mode, Rail-to-Rail inputs, input common mode voltage 0.2 to VDDA-0.2 V	Idd_hi_10x	-	800	920	µA
Ultra-High power mode, Rail-to-Rail inputs, input common mode voltage 0.2 to VDDA-0.2 V	Idd_ultrahi_10x	-	1300	1500	µA
VDDA for one Opamp, Internal-drive only	VDDA for one Opamp, Internal-drive only	VDDA for one Opamp, Internal-drive only	VDDA for one Opamp, Internal-drive only	VDDA for one Opamp, Internal-drive only	VDDA for one Opamp, Internal-drive only
Ultra-Low power mode, common mode voltage from 0.2 to VDDA-1 V	Idd_ultralow_1x	-	15	30	µA
Ultra-Low power mode, Rail-to-Rail inputs, input common mode voltage 0.2 to VDDA-0.2 V	Idd_ultralow_1x	-	35	60	µA
Low power mode, Rail-to-Rail inputs, input common mode voltage 0.2 to VDDA-0.2 V	Idd_low_1x	-	150	200	µA
Medium power mode, Rail-to-Rail inputs, input common mode voltage 0.2 to VDDA-0.2 V	Idd_med_1x	-	200	250	µA
High power mode, Rail-to-Rail inputs, input common mode voltage 0.2 to VDDA-0.2 V	Idd_hi_1x	-	600	700	µA
Ultra-High power mode, Rail-to-Rail inputs, input common mode voltage 0.2 to VDDA-0.2 V	Idd_ultrahi_1 x	-	800	1000	µA
Capability, Driving a pin	Capability, Driving a pin	Capability, Driving a pin	Capability, Driving a pin	Capability, Driving a pin	Capability, Driving a pin
Ultra-Low power mode, output 200 mV from rail , output voltage change <2 mV	Iout_max_ultralow_10x	-	-	10	µA
Low power mode, output 200 mV from rail, output voltage change <1 mV	Iout_max_low_10x	-	-	100	µA
Medium power mode, output 200 mV from rail, output voltage change <1 mV	Iout_max_med_10x	-	-	500	µA
High power mode, output 200 mV from rail, output voltage change <1 mV	Iout_max_hi_10x	-	-	1000	µA
Ultra-High power mode, output 200 mV from rail, ,output voltage change <1 mV	Iout_max_ultrahi_10x	-	-	10000	µA
Capability, Internal-Drive only	Capability, Internal-Drive only	Capability, Internal-Drive only	Capability, Internal-Drive only	Capability, Internal-Drive only	Capability, Internal-Drive only
Ultra-Low power mode, output 200 mV from rail , output voltage change <2 mV	Iout_max_1x_ultralow	-	-	1	µA
Low power mode, output 200 mV from rail, output voltage change <1 mV	Iout_max_1x_low	-	-	10	µA
Medium power mode, output 200 mV from rail, output voltage change <1 mV	Iout_max_1x_med	-	-	25	µA
High power mode, output 200 mV from rail, output voltage change <1 mV	Iout_max_1x_hi	-	-	100	µA
Ultra-High power mode, output 200 mV from rail, ,output voltage change <1 mV	Iout_max_1x_Ultrahi	-	-	200	µA
Voltage Range	Voltage Range	Voltage Range	Voltage Range	Voltage Range	Voltage Range
Ultra-High power mode, output driving pin, 10 mA	Vout_1_10x_10mA_ ultrahi	0.5	-	VDDA-0. 5	V
High power mode, output driving pin, 1 mA	Vout_2_10x_1mA_hi	0.2	-	VDDA-0. 2	V
Medium power mode, output driving pin, 1 mA	Vout_3_10x_1mA_med	0.2	-	VDDA-0. 2	V
Low power mode , output driving pin, 0.1 mA	Vout_4_10x_0.1mA_lo	0.2	-	VDDA-0. 2	V
Range	Range	Range	Range	Range	Range
Input Voltage Range, Ultra-Low power mode	Vin_pump_of f	0	-	VDDA-1	V
Input Voltage Range, power mode with Rail-to-Rail inputs	Vin_pump_o n	0	-	VDDA-0. 2	V
trimmed	trimmed	trimmed	trimmed	trimmed	trimmed
Ultra-High power mode, output driving pin	Vos_tr_10x_u ltrahi	-1	-	1	mV
High power mode, output driving pin	Vos_tr_10x_h i	-1	-	1	mV
Medium power mode, output driving pin	Vos_tr_10x_ med	-1	-	1	mV
Ultra-High power mode, internal drive-only	Vos_tr_1x_ult rahi	-1	-	1	mV
High power mode, internal drive-only	Vos_tr_1x_hi	-1	-	1	mV
Medium power mode, internal drive-only	Vos_tr_1x_m ed	-1	-	1	mV
Offset trim step, output driving pin	Vos_step_10x_hi	300	-	500	µV
Offset trim step, internal drive-only	Vos_step_1x_ hi	300	-	500	µV
Temperature Drift	Temperature Drift	Temperature Drift	Temperature Drift	Temperature Drift	Temperature Drift
Output driving pin, Medium power mode	Vos_dr_tr_10x_med	-10	-	10	µV/C
Output driving pin, High power mode	Vos_dr_tr_10x_hi	-10	-	10	µV/C
Output driving pin, Ultra-High power mode	Vos_dr_tr_10x_Ultrahi	-10	-	10	µV/C
Internal drive-only, Medium power mode	Vos_dr_tr_1x_med	-10	-	10	µV/C
Internal drive-only, High power mode	Vos_dr_tr_1x_hi	-10	-	10	µV/C
Internal drive-only, Ultra-High power mode	Vos_dr_tr_1x_Ultrahi	-10	-	10	µV/C
mode rejection ratio, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V)	mode rejection ratio, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V)	mode rejection ratio, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V)	mode rejection ratio, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V)	mode rejection ratio, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V)	mode rejection ratio, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V)
Ultra-Low power mode, output driving pin	CMRR_ultralow_10x	-40	-	-	dB
Low power mode, output driving pin	CMRR_low_10x	-40	-	-	dB
Medium power mode, output driving pin	CMRR_med_10x	-40	-	-	dB
High power mode, output driving pin	CMRR_hi_10x	-40	-	-	dB
Ultra-High power mode, output driving pin	CMRR_ultrahi_10x	-40	-	-	dB
Ultra-Low power mode, internal drive-only	CMRR_ultralow_1x	-40	-	-	dB
Low power mode, internal drive-only	CMRR_low_1 x	-40	-	-	dB
Medium power mode, internal drive-only	CMRR_med_1 x	-40	-	-	dB
High power mode, internal drive-only	CMRR_hi_1x	-40	-	-	dB
Ultra-High power mode, internal drive-only	CMRR_ultrahi_1x	-40	-	-	dB
Input leakage current from CTB port pin	Input Leakage	-	2	800	nA
rejection ratio (DC), Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2	rejection ratio (DC), Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2	rejection ratio (DC), Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2	rejection ratio (DC), Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2	rejection ratio (DC), Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2	rejection ratio (DC), Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2
Ultra-Low power mode, output driving pin	PSRR_ultralow_10x	-45	-	-	dB
Low power mode, output driving pin	PSRR_low_10 x	-45	-	-	dB
Medium power mode, output driving pin	PSRR_med_10x	-45	-	-	dB
High power mode, output driving pin	PSRR_hi_10x	-45	-	-	dB
Ultra-High power mode, output driving pin	PSRR_ultrahi_10x	-45	-	-	dB
Ultra-Low power mode, internal drive-only	PSRR_ultralow_1x	-45	-	-	dB
Low power mode, internal drive-only	PSRR_low_1x	-45	-	-	dB
Medium power mode, internal drive-only	PSRR_med_1 x	-45	-	-	dB
High power mode, internal drive-only	PSRR_hi_1x	-45	-	-	dB
Ultra-High power mode, internal drive-only	PSRR_ultrahi_1x	-45	-	-	dB
rejection ratio at 1 kHz, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2	rejection ratio at 1 kHz, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2	rejection ratio at 1 kHz, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2	rejection ratio at 1 kHz, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2	rejection ratio at 1 kHz, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2	rejection ratio at 1 kHz, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2
Ultra-Low power mode, output driving pin	PSRR_ultralow_10x	-45	-	-	dB
Low power mode, output driving pin	PSRR_low_10 x	-45	-	-	dB
Medium power mode, output driving pin	PSRR_med_10x	-45	-	-	dB
High power mode, output driving pin	PSRR_hi_10x	-45	-	-	dB
Ultra-High power mode, output driving pin	PSRR_ultrahi_10x	-45	-	-	dB
Ultra-Low power mode, internal drive-only	PSRR_ultralow_1x	-45	-	-	dB
Low power mode, internal drive-only	PSRR_low_1x	-45	-	-	dB
Medium power mode, internal drive-only	PSRR_med_1 x	-45	-	-	dB
High power mode, internal drive-only	PSRR_hi_1x	-45	-	-	dB
Ultra-High power mode, internal drive-only	PSRR_ultrahi_1x	-45	-	-	dB
Gain, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V)	Gain, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V)	Gain, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V)	Gain, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V)	Gain, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V)	Gain, Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V)
Ultra-Low power mode, output driving pin	Gain_Ultralow_10x	60	-	-	dB
Low power mode, output driving pin	Gain_Low_10 x	70	-	-	dB
Medium power mode, output driving pin	Gain_Med_10 x	70	-	-	dB
High power mode, output driving pin	Gain_Hi_10x	70	-	-	dB
Ultra-High power mode, output driving pin	Gain_Ultrahi_10x	70	-	-	dB
Ultra-Low power mode, internal drive-only	Gain_Ultralow_1x	60	-	-	dB
Low power mode, internal drive-only	Gain_Low_1x	70	-	-	dB
Medium power mode, internal drive-only	Gain_Med_1x	70	-	-	dB
High power mode, internal drive-only	Gain_Hi_1x	70	-	-	dB
Ultra-High power mode, internal drive-only	Gain_Ultrahi_1x	70	-	-	dB
noise spectral density at 100 kHz, common mode input voltage at VDDA/2	noise spectral density at 100 kHz, common mode input voltage at VDDA/2	noise spectral density at 100 kHz, common mode input voltage at VDDA/2	noise spectral density at 100 kHz, common mode input voltage at VDDA/2	noise spectral density at 100 kHz, common mode input voltage at VDDA/2	noise spectral density at 100 kHz, common mode input voltage at VDDA/2
Ultra-Low power mode, output driving pin	Vnoise_Ultralow_10x_100k	-	-	200	nV/ √Hz
Low power mode, output driving pin	Vnoise_Low_10x_100k	-	-	80	nV/ √Hz
Medium power mode, output driving pin	Vnoise_Med_10x_100k	-	-	70	nV/ √Hz
High power mode, output driving pin	Vnoise_Hi_10x_100k	-	-	60	nV/ √Hz
Ultra-High power mode, output driving pin	Vnoise_Ultrahi_10x_100k	-	-	50	nV/ √Hz
Ultra-Low power mode, internal drive-only	Vnoise_Ultralow_1x_100k	-	-	500	nV/ √Hz
Low power mode, internal drive-only	Vnoise_Low_1x_100k	-	-	80	nV/ √Hz
Medium power mode, internal drive-only	Vnoise_Med_1x_100k	-	-	70	nV/ √Hz
High power mode, internal drive-only	Vnoise_Hi_1x_100k	-	-	60	nV/ √Hz
Ultra-High power mode, internal drive-only	Vnoise_Ultrahi_1x_100k	-	-	50	nV/ √Hz
Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), 50 pF load, Output	Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), 50 pF load, Output	Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), 50 pF load, Output	Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), 50 pF load, Output	Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), 50 pF load, Output	Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), 50 pF load, Output
Ultra-Low power mode, compensation trim = 1	PM_Ultralow_10x	40	60	-	deg
Low power mode, compensation trim = 2	PM_Low_10x	40	60	-	deg
Medium power mode, compensation trim = 2	PM_Med_10x	40	60	-	deg
High power mode, compensation trim = 2	PM_Hi_10x	40	60	-	deg
Ultra-High power mode, compensation trim = 2	PM_Ultrahi_10x	40	60	-	deg
Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), 15 pF load,	Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), 15 pF load,	Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), 15 pF load,	Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), 15 pF load,	Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), 15 pF load,	Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), 15 pF load,
Ultra-Low power mode,compensation trim = 2	PM_Ultralow_1x	40	60	-	deg
Low power mode, compensation trim = 3	PM_Low_1x	40	60	-	deg
Medium power mode, compensation trim = 4	PM_Med_1x	40	60	-	deg
High power mode, compensation trim = 4	PM_Hi_1x	40	60	-	deg
Ultra-High power mode, compensation trim = 5	PM_Ultrahi_1 x	40	60	-	deg
product (GBW), Rail to Rail inputs common mode voltage 0.2 to VDDA-0.2 V), load	product (GBW), Rail to Rail inputs common mode voltage 0.2 to VDDA-0.2 V), load	product (GBW), Rail to Rail inputs common mode voltage 0.2 to VDDA-0.2 V), load	product (GBW), Rail to Rail inputs common mode voltage 0.2 to VDDA-0.2 V), load	product (GBW), Rail to Rail inputs common mode voltage 0.2 to VDDA-0.2 V), load	product (GBW), Rail to Rail inputs common mode voltage 0.2 to VDDA-0.2 V), load
Ultra-Low power mode, compensation trim = 1	GBW_Ultralow_10x	0.1	0.15	-	MHz
Low power mode, compensation trim = 2	GBW_Low_10 x	1.2	1.5	-	MHz
Medium power mode, compensation trim = 2	GBW_Med_10 x	2.4	3	-	MHz
High power mode, compensation trim = 2	GBW_Hi_10x	6	7.5	-	MHz
Ultra-High power mode, compensation trim = 2	GBW_Ultrahi_10x	7.5	12	-	MHz
product (GBW), Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), load	product (GBW), Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), load	product (GBW), Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), load	product (GBW), Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), load	product (GBW), Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), load	product (GBW), Rail to Rail inputs (common mode voltage 0.2 to VDDA-0.2 V), load
Ultra-Low power mode, compensation trim = 2	GBW_Ultralow_1x	0.03	0.15	-	MHz
Low power mode, compensation trim = 3	GBW_Low_1x	0.35	1.5	-	MHz
Medium power mode, compensation trim = 4	GBW_Med_1x	0.7	3	-	MHz
High power mode, compensation trim = 4	GBW_Hi_1x	1.75	7.5	-	MHz
Ultra-High power mode, compensation trim = 5	GBW_Ultrahi_1x	2.8	12	-	MHz
(f3dB) of the PGA (non-inverting) topology, Output Driving pin, input and output to VDDA-0.2, compensation capacitors enabled	(f3dB) of the PGA (non-inverting) topology, Output Driving pin, input and output to VDDA-0.2, compensation capacitors enabled	(f3dB) of the PGA (non-inverting) topology, Output Driving pin, input and output to VDDA-0.2, compensation capacitors enabled	(f3dB) of the PGA (non-inverting) topology, Output Driving pin, input and output to VDDA-0.2, compensation capacitors enabled	(f3dB) of the PGA (non-inverting) topology, Output Driving pin, input and output to VDDA-0.2, compensation capacitors enabled	(f3dB) of the PGA (non-inverting) topology, Output Driving pin, input and output to VDDA-0.2, compensation capacitors enabled
Ultra-High power mode, Gain = 2	f3db_2_10x_NI_GND_Ultr aHI	3	-	-	Mhz
Ultra-High power mode, Gain = 4	f3db_4_10x_NI_GND_Ultr aHI	0.5	-	-	Mhz
Ultra-High power mode, Gain =16	f3db_16_10x_NI_GND_Ultr aHI	0.086	-	-	Mhz
Ultra-High power mode, Gain =32	f3db_32_10x_NI_GND_Ultr aHI	0.009	-	-	Mhz
High power mode, Gain = 2	f3db_2_10x_NI_GND_HI	3.8	-	-	Mhz
High power mode, Gain = 4	f3db_4_10x_NI_GND_HI	0.5	-	-	Mhz
High power mode, Gain = 16	f3db_16_10x_NI_GND_HI	0.2	-	-	Mhz
High power mode, Gain = 32	f3db_32_10x_NI_GND_HI	0.1	-	-	Mhz
Medium power mode, Gain = 2	f3db_2_10x_NI_GND_Med	1.9	-	-	Mhz
Medium power mode, Gain = 4	f3db_4_10x_NI_GND_Med	0.4	-	-	Mhz
Medium power mode, Gain = 16	f3db_16_10x_NI_GND_Med	0.1	-	-	Mhz
Medium power mode, Gain = 32	f3db_32_10x_NI_GND_Med	0.072	-	-	Mhz
Low power mode, Gain = 2	f3db_2_10x_NI_GND_Low	1.1	-	-	Mhz
Low power mode, Gain = 4	f3db_4_10x_NI_GND_Low	0.3	-	-	Mhz
Low power mode, Gain = 16	f3db_16_10x_NI_GND_Low	0.086	-	-	Mhz
Low power mode, Gain = 32	f3db_32_10x_NI_GND_Low	0.043	-	-	Mhz
Ultra-Low power mode, Gain = 2	f3db_2_10x_NI_GND_Ultr aLow	0.1	-	-	Mhz
Ultra-Low power mode, Gain = 4	f3db_4_10x_NI_GND_Ultr aLow	0.043	-	-	Mhz
Ultra-Low power mode, Gain = 16	f3db_16_10x_NI_GND_Ultr aLow	0.007	-	-	Mhz
Ultra-Low power mode, Gain = 32	f3db_32_10x_NI_GND_Ultr aLow	0.005	-	-	Mhz
(f3dB) of the PGA (non-inverting) topology, internal drive-only, input and output to VDDA-0.2, compensation capacitors enabled	(f3dB) of the PGA (non-inverting) topology, internal drive-only, input and output to VDDA-0.2, compensation capacitors enabled	(f3dB) of the PGA (non-inverting) topology, internal drive-only, input and output to VDDA-0.2, compensation capacitors enabled	(f3dB) of the PGA (non-inverting) topology, internal drive-only, input and output to VDDA-0.2, compensation capacitors enabled	(f3dB) of the PGA (non-inverting) topology, internal drive-only, input and output to VDDA-0.2, compensation capacitors enabled	(f3dB) of the PGA (non-inverting) topology, internal drive-only, input and output to VDDA-0.2, compensation capacitors enabled
Ultra-High power mode, Gain = 2	f3db_2_1x_NI_GND_UltraHI	0.259	-	-	Mhz
Ultra-High power mode, Gain = 4	f3db_4_1x_NI_GND_UltraHI	0.302	-	-	Mhz
Ultra-High power mode, Gain =16	f3db_16_1x_NI_GND_Ultr aHI	0.331	-	-	Mhz
Ultra-High power mode, Gain =32	f3db_32_1x_NI_GND_Ultr aHI	0.035	-	-	Mhz
High power mode, Gain = 2	f3db_2_1x_NI_GND_HI	0.554	-	-	Mhz
High power mode, Gain = 4	f3db_4_1x_NI_GND_HI	0.4	-	-	Mhz
High power mode, Gain = 16	f3db_16_1x_NI_GND_HI	0.1	-	-	Mhz
High power mode, Gain = 32	f3db_32_1x_NI_GND_HI	0.005	-	-	Mhz
Medium power mode, Gain = 2	f3db_2_1x_NI_GND_Med	0.454	-	-	Mhz
Medium power mode, Gain = 4	f3db_4_1x_NI_GND_Med	0.3	-	-	Mhz
Medium power mode, Gain = 16	f3db_16_1x_NI_GND_Med	0.065	-	-	Mhz
Medium power mode, Gain = 32	f3db_32_1x_NI_GND_Med	0.004	-	-	Mhz
Low power mode, Gain = 2	f3db_2_1x_NI_GND_Low	0.288	-	-	Mhz
Low power mode, Gain = 4	f3db_4_1x_NI_GND_Low	0.173	-	-	Mhz
Low power mode, Gain = 16	f3db_16_1x_NI_GND_Low	0.04	-	-	Mhz
Low power mode, Gain = 32	f3db_32_1x_NI_GND_Low	0.02	-	-	Mhz
Ultra-Low power mode, Gain = 2	f3db_2_1x_NI_GND_UltraL ow	0.006	-	-	Mhz
Ultra-Low power mode, Gain = 4	f3db_4_1x_NI_GND_UltraL ow	0.029	-	-	Mhz
Ultra-Low power mode, Gain = 16	f3db_16_1x_NI_GND_Ultr aLow	0.002	-	-	Mhz
Ultra-Low power mode, Gain = 32	f3db_32_1x_NI_GND_Ultr aLow	0.003	-	-	Mhz
(rise ansd fall), output driving pin, 50 pF load, output voltage transitioning VDDA/2+500 mV	(rise ansd fall), output driving pin, 50 pF load, output voltage transitioning VDDA/2+500 mV	(rise ansd fall), output driving pin, 50 pF load, output voltage transitioning VDDA/2+500 mV	(rise ansd fall), output driving pin, 50 pF load, output voltage transitioning VDDA/2+500 mV	(rise ansd fall), output driving pin, 50 pF load, output voltage transitioning VDDA/2+500 mV	(rise ansd fall), output driving pin, 50 pF load, output voltage transitioning VDDA/2+500 mV
Ultra-Low power mode	SL_Ultralow_10x	0.10	-	-	V/µs
Low power mode	SL_Low_10x	1.00	-	-	V/µs
Medium power mode	SL_Med_10x	2.00	-	-	V/µs
High power mode	SL_Hi_10x	3.00	-	-	V/µs
Ultra-High power mode	SL_Ultrahi_10x	4.00	-	-	V/µs
(rise ansd fall), internal drive-only, 15 pF load, output voltage transitioning from mV	(rise ansd fall), internal drive-only, 15 pF load, output voltage transitioning from mV	(rise ansd fall), internal drive-only, 15 pF load, output voltage transitioning from mV	(rise ansd fall), internal drive-only, 15 pF load, output voltage transitioning from mV	(rise ansd fall), internal drive-only, 15 pF load, output voltage transitioning from mV	(rise ansd fall), internal drive-only, 15 pF load, output voltage transitioning from mV
Ultra-Low power mode	SL_Ultralow_1x	0.03	-	-	V/µs
Low power mode	SL_Low_1x	0.30	-	-	V/µs
Medium power mode	SL_Med_1x	0.60	-	-	V/µs
High power mode	SL_Hi_1x	1.80	-	-	V/µs
Ultra-High power mode	SL_Ultrahi_1x	3.00	-	-	V/µs
time, output driving pin, 50 pF load, output voltage transitioning from VDDA/2+50 mV	time, output driving pin, 50 pF load, output voltage transitioning from VDDA/2+50 mV	time, output driving pin, 50 pF load, output voltage transitioning from VDDA/2+50 mV	time, output driving pin, 50 pF load, output voltage transitioning from VDDA/2+50 mV	time, output driving pin, 50 pF load, output voltage transitioning from VDDA/2+50 mV	time, output driving pin, 50 pF load, output voltage transitioning from VDDA/2+50 mV
Ultra-Low power mode	Tsettle_Ultralow_10x	-	-	4000	ns
Low power mode	Tsettle_Low_10x	-	-	600	ns
Medium power mode	Tsettle_Med_10x	-	-	450	ns
High power mode	Tsettle_Hi_10 x	-	-	300	ns
Ultra-High power mode	Tsettle_Ultrahi_10x	-	-	250	ns
time, internal drive-only, 15pF load, output voltage transitioning from VDDA/2+50 mV	time, internal drive-only, 15pF load, output voltage transitioning from VDDA/2+50 mV	time, internal drive-only, 15pF load, output voltage transitioning from VDDA/2+50 mV	time, internal drive-only, 15pF load, output voltage transitioning from VDDA/2+50 mV	time, internal drive-only, 15pF load, output voltage transitioning from VDDA/2+50 mV	time, internal drive-only, 15pF load, output voltage transitioning from VDDA/2+50 mV
Ultra-Low power mode	Tsettle_Ultralow_1x	-	-	5000	ns
Low power mode	Tsettle_Low_1x	-	-	1500	ns
Medium power mode	Tsettle_Med_1x	-	-	800	ns
High power mode	Tsettle_Hi_1x	-	-	400	ns
Ultra-High power mode	Tsettle_Ultrahi_1x	-	-	300	ns
times	times	times	times	times	times
Start up time, output driving a pin, with 50pF load, all power modes	Tstartup_10x	-	-	5000	ns
Start up time, internal-drive only, 15pf load, all power modes	Tstartup_1x	-	-	5000	ns
PGA/Differential PGA Specs	PGA/Differential PGA Specs	PGA/Differential PGA Specs	PGA/Differential PGA Specs	PGA/Differential PGA Specs	PGA/Differential PGA Specs
PGA Gain Range (Non-inverting)	PGAGAIN	1.42	-	32
PGA Gain Range (Inverting)	PGA_Inv_Gain_Range	0.42	-	31
Differential PGA Gain Range	DIFF_Gain_R ange	0.42	-	31
VDDA for PGA (non-inverting) topology, Output Driving pin, Common mode output compensation capacitors enabled	VDDA for PGA (non-inverting) topology, Output Driving pin, Common mode output compensation capacitors enabled	VDDA for PGA (non-inverting) topology, Output Driving pin, Common mode output compensation capacitors enabled	VDDA for PGA (non-inverting) topology, Output Driving pin, Common mode output compensation capacitors enabled	VDDA for PGA (non-inverting) topology, Output Driving pin, Common mode output compensation capacitors enabled	VDDA for PGA (non-inverting) topology, Output Driving pin, Common mode output compensation capacitors enabled
Ultra-Low power mode	Idd_ultra_low_10x_PGA	-	-	60	µA
Low power mode	Idd_low_10x_PGA	-	-	200	µA
Medium power mode	Idd_med_10x_PGA	-	-	350	µA
High power mode	Idd_hi_10x_PGA	-	-	1000	µA
Ultra-High power mode	Idd_Ultra_hi_10x_PGA	-	-	1620	µA
VDDA for PGA (non-inverting) topology, Internal-drive only, common mode output compensation capacitors enabled	VDDA for PGA (non-inverting) topology, Internal-drive only, common mode output compensation capacitors enabled	VDDA for PGA (non-inverting) topology, Internal-drive only, common mode output compensation capacitors enabled	VDDA for PGA (non-inverting) topology, Internal-drive only, common mode output compensation capacitors enabled	VDDA for PGA (non-inverting) topology, Internal-drive only, common mode output compensation capacitors enabled	VDDA for PGA (non-inverting) topology, Internal-drive only, common mode output compensation capacitors enabled
Ultra-Low power mode	Idd_Ultra_low_1x_PGA	-	-	50	µA
Low power mode	Idd_low_1x_PGA	-	-	120	µA
Medium power mode	Idd_med_1x_PGA	-	-	200	µA
High power mode	Idd_hi_1x_PGA	-	-	500	µA
Ultra-High power mode	Idd_Ultra_hi_1x_PGA	-	-	800	µA
of PGA (non-inverting) topology, internal-drive only, input and output common compensation capacitors enabled	of PGA (non-inverting) topology, internal-drive only, input and output common compensation capacitors enabled	of PGA (non-inverting) topology, internal-drive only, input and output common compensation capacitors enabled	of PGA (non-inverting) topology, internal-drive only, input and output common compensation capacitors enabled	of PGA (non-inverting) topology, internal-drive only, input and output common compensation capacitors enabled	of PGA (non-inverting) topology, internal-drive only, input and output common compensation capacitors enabled
Ultra-High power mode, Gain = 2	G_error_2_1x_NI_GND__Ul traHI	-5	-	5	%
Ultra-High power mode, Gain = 4	G_error_4_1x_NI_GND__Ul traHI	-5	-	5	%
Ultra-High power mode, Gain =16	G_error_16_1x_NI_GND__ UltraHI	-10	-	10	%
Ultra-High power mode, Gain =32	G_error_32_1x_NI_GND__ UltraHI	-10	-	10	%
High power mode, Gain = 2	G_error_2_1x_NI_GND__HI	-5	-	5	%
High power mode, Gain = 4	G_error_4_1x_NI_GND__HI	-5	-	5	%
High power mode, Gain = 16	G_error_16_1x_NI_GND__HI	-10	-	10	%
High power mode, Gain = 32	G_error_32_1x_NI_GND__HI	-10	-	10	%
Medium power mode, Gain = 2	G_error_2_1x_NI_GND__m ed	-5	-	5	%
Medium power mode, Gain = 4	G_error_4_1x_NI_GND__m ed	-5	-	5	%
Medium power mode, Gain = 16	G_error_16_1x_NI_GND__ med	-10	-	10	%
Medium power mode, Gain = 32	G_error_32_1x_NI_GND__ med	-10	-	10	%
Low power mode, Gain = 2	G_error_2_1x_NI_GND__lo w	-5	-	5	%
Low power mode, Gain = 4	G_error_4_1x_NI_GND__lo w	-5	-	5	%
Low power mode, Gain = 16	G_error_16_1x_NI_GND__l ow	-10	-	10	%
Low power mode, Gain = 32	G_error_32_1x_NI_GND__l ow	-10	-	10	%
Ultra-Low power mode, Gain = 2	G_error_2_1x_NI_GND__Ul tralow	-5	-	5	%
Ultra-Low power mode, Gain = 4	G_error_4_1x_NI_GND__Ul tralow	-5	-	5	%
Ultra-Low power mode, Gain = 16	G_error_16_1x_NI_GND__ Ultralow	-10	-	10	%
Ultra-Low power mode, Gain = 32	G_error_32_1x_NI_GND__ Ultralow	-10	-	10	%
of PGA (non-inverting) topology, output driving pin, input and output common mode compensation capacitors enabled	of PGA (non-inverting) topology, output driving pin, input and output common mode compensation capacitors enabled	of PGA (non-inverting) topology, output driving pin, input and output common mode compensation capacitors enabled	of PGA (non-inverting) topology, output driving pin, input and output common mode compensation capacitors enabled	of PGA (non-inverting) topology, output driving pin, input and output common mode compensation capacitors enabled	of PGA (non-inverting) topology, output driving pin, input and output common mode compensation capacitors enabled
Ultra-High power mode, Gain = 2	G_error_2_10x_NI_GND__ UltraHI	-5	-	5	%
Ultra-High power mode, Gain = 4	G_error_4_10x_NI_GND__ UltraHI	-5	-	5	%
Ultra-High power mode, Gain =16	G_error_16_10x_NI_GND__ UltraHI	-10	-	10	%
Ultra-High power mode, Gain =32	G_error_32_10x_NI_GND__ UltraHI	-10	-	10	%
High power mode, Gain = 2	G_error_2_10x_NI_GND_HI	-5	-	5	%
High power mode, Gain = 4	G_error_4_10x_NI_GND_HI	-5	-	5	%
High power mode, Gain = 16	G_error_16_10x_NI_GND_HI	-10	-	10	%
High power mode, Gain = 32	G_error_32_10x_NI_GND_HI	-10	-	10	%
Medium power mode, Gain = 2	G_error_2_10x_NI_GND_m ed	-5	-	5	%
Medium power mode, Gain = 4	G_error_4_10x_NI_GND_m ed	-5	-	5	%
Medium power mode, Gain = 16	G_error_16_10x_NI_GND_ med	-10	-	10	%
Medium power mode, Gain = 32	G_error_32_10x_NI_GND_ med	-10	-	10	%
Low power mode, Gain = 2	G_error_2_10x_NI_GND_lo w	-5	-	5	%
Low power mode, Gain = 4	G_error_4_10x_NI_GND_lo w	-5	-	5	%
Low power mode, Gain = 16	G_error_16_10x_NI_GND_l ow	-10	-	10	%
Low power mode, Gain = 32	G_error_32_10x_NI_GND_l ow	-10	-	10	%
Ultra-Low power mode, Gain = 2	G_error_2_10x_NI_GND__ Ultralow	-5	-	5	%
Ultra-Low power mode, Gain = 4	G_error_4_10x_NI_GND__ Ultralow	-5	-	5	%
Ultra-Low power mode, Gain = 16	G_error_16_10x_NI_GND__ Ultralow	-10	-	10	%
Ultra-Low power mode, Gain = 32	G_error_32_10x_NI_GND__ Ultralow	-10	-	10	%
Mode Rejection Ratio of Differential PGA	Mode Rejection Ratio of Differential PGA	Mode Rejection Ratio of Differential PGA	Mode Rejection Ratio of Differential PGA	Mode Rejection Ratio of Differential PGA	Mode Rejection Ratio of Differential PGA
CMRR (input common mode voltage 0.2 to VDDA-0.2 V, internal drive only, High power mode, Small signal Gain=2, CL =15 pF)	CMRR_1x_hi_diff_pga_1x	-60	-	-	dB
CMRR (input common mode voltage 0.2 to VDDA-0.2 V, internal drive only, High power mode, Small signal Gain=8, CL =15 pF)	CMRR_1x_hi_diff_pga_8x	-60	-	-	dB
Specs	Specs	Specs	Specs	Specs	Specs
TIA Gain Range	TIA Gain Range	57	-	186	kΩ
Specs	Specs	Specs	Specs	Specs	Specs
Comparator Hysteresis Ultra-High power mode, (input common mode voltage =VDDA/2,CL=300 fF)	Comparator Hyst Ultra-High power	2	-	-	mV
Comparator Hysteresis High power mode, (input common mode voltage =VDDA/2,CL=300 fF)	Comparator Hyst High power	5	-	-	mV
Comparator Hysteresis Medium power mode, (input common mode voltage =VDDA/2,CL=300 fF)	Comparator Hyst Medium power	10	-	-	mV
Comparator Hysteresis Low power mode, (input common mode voltage =VDDA/2,CL=300 fF)	Comparator Hyst Low power	20	-	-	mV
Comparator Hysteresis Ultra-Low power mode, (input common mode voltage =VDDA/2,CL=300 fF)	Comparator Hyst Ultra-Low power	40	-	-	mV
Comparator-topology response time (delay) 50mV overdrive, Rail to Rail inputs (output common VDDA-0.2 V), load capacitance of 300 fF	Comparator-topology response time (delay) 50mV overdrive, Rail to Rail inputs (output common VDDA-0.2 V), load capacitance of 300 fF	Comparator-topology response time (delay) 50mV overdrive, Rail to Rail inputs (output common VDDA-0.2 V), load capacitance of 300 fF	Comparator-topology response time (delay) 50mV overdrive, Rail to Rail inputs (output common VDDA-0.2 V), load capacitance of 300 fF	Comparator-topology response time (delay) 50mV overdrive, Rail to Rail inputs (output common VDDA-0.2 V), load capacitance of 300 fF	Comparator-topology response time (delay) 50mV overdrive, Rail to Rail inputs (output common VDDA-0.2 V), load capacitance of 300 fF
Low power mode, compensation trim = 2	Comparator Tpd_lo	-	-	150	ns
Medium power mode, compensation trim = 3	Comparator Tpd med	-	-	100	ns
High power mode, compensation trim = 4	Comparator Tpd hi	-	-	80	ns

Table 51 (pages 113–114)

Table 51 · 6 columns × 29 rows · p.113–114 · CSV

Description	Symbol	Values			Unit
Description	Symbol	Min.	Typ.	Max.	Unit
DC Specifications
Input offset voltage. Normal power mode	VOFFSET1	-5	-	5	mV
Input offset voltage. Low-power mode	VOFFSET2	-10	-	10	mV
Input offset voltage. Ultra low-power mode	VOFFSET3	-10	-	10	mV
Hysteresis when enabled in Normal mode	VHYST1	-	-	60	mV
Hysteresis when enabled in Low-power mode	VHYST2	-	-	80	mV
Input common mode voltage in Normal mode	VICM1	0	-	VDDA-0.1	V
Input common mode voltage in Low power mode	VICM2	0	-	VDDA-0.1	V
Input common mode voltage in Ultra low power mode	VICM3	0	-	VDDA-0.1	V
Common mode rejection ratio in Normal power mode	CMRR	50	-	-	dB
Block Current, Normal mode	ICMP1	-	-	150	µA
Block Current, Low power mode	ICMP2	-	-	10	µA
Block Current in Ultra low power mode	ICMP3	-	0.3	0.85	µA
AC Specifications	AC Specifications	AC Specifications	AC Specifications	AC Specifications	AC Specifications
Response time, Normal mode, 100 mV overdrive	TRESP1	-	-	100	ns
Response time, Low power mode, 100 mV overdrive	TRESP2	-	-	1000	ns
Response time, Ultra-low power mode, 100 mV overdrive	TRESP3	-	-	7	µs
Time from Enabling to operation	TCMPEN1	-	-	10	µs
Time from Enabling to operation	TCMPEN2	-	-	50	µs
Numerical Resolution of PRB		4	-	4	bits
Current from VDDA when PRB enabled	IDDA_acti ve	650	850	2200	nA
Total resistance of potential dividers on VDDA/VBGR	Res	1.6	2.2	2.8	MΩ
DNL of output 1 with VDDA as reference, output 0 connected to tap 7, no load	Vref_DNL_Step_Size_VDDAl adder	-1	-	1	LSB
DNL of output 1 with VBGR(0.9 V) as reference, output 0 connected to tap 7, no load	Vref_DNL_Step_Size_BGlad der	-1	-	1	LSB
INL of output 1 with VDDA as reference, output 0 connected to tap 7, no load	Vref_INL_Step_Size_VDDAla dder	-1	-	1	LSB
INL of output 1 with VBGR(0.9 V) as reference, output 0 connected to tap 7, no load	Vref_INL_Step_Size_BGladd er	-1	-	1	LSB
Start-up time (output within +-10 mV of steady state) when both outputs from VBGR (0.9 V) reference	Tstartup_ BGladder	-	-	100	µs
Start-up time (output within +-10 mV of the steady state) when both outputs from VDDA reference	Tstartup_ VDDAlad der	-	-	150	µs
Output settling time to +-10 mV when one code changes, VBGR (0.9 V) reference	Tsettling _code_B Gladder	-	25	40	µs
Output settling time to +-10 mV when one code changes, VDDA reference	Tsettling _code_V DDAladd er	-	45	60	µs

Table 52 (pages 115–120)

Table 52 · 6 columns × 123 rows · p.115–120 · CSV

Parameter	Symbol	Values			Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
Specifications
Block current at 100 MHz. HP mode.	ITCPWM	-	-	540	µA
Operating frequency	TCPWMFREQ	-	-	100	MHz
Input Trigger Pulse Width for all Trigger Events	TPWMENEXT	2/Fc	-	-	ns
Output Trigger Pulse widths	TPWMEXT	1.5/Fc	-	-	ns
Resolution of Counter	TCRES	1/Fc	-	-	ns
PWM Resolution	PWMRES	1/Fc	-	-	ns
Quadrature inputs resolution	QRES	2/Fc	-	-	ns
Operating frequency. HP mode	TCPWMFREQ	-	-	100	MHz
Operating frequency. LP mode	TCPWMFREQ	-	-	40	MHz
Operating frequency. ULP mode	TCPWMFREQ	-	-	25	MHz
AC Specifications	AC Specifications	AC Specifications	AC Specifications	AC Specifications	AC Specifications
Bit Rate	FI2C1	-	-	1	Mbps
AC Specifications	AC Specifications	AC Specifications	AC Specifications	AC Specifications	AC Specifications
Bit rate in HP mode	FUART1	-	-	16	Mbps
Bit rate at LP mode	FUART2	-	-	8	Mbps
Bit rate at ULP mode	FUART3	-	-	3	Mbps
AC Specifications	AC Specifications	AC Specifications	AC Specifications	AC Specifications	AC Specifications
SPI Operating frequency Externally Clocked Slave	FSPI	-	-	25	MHz
SPI Operating frequency Master (Fscb is SPI clock)	FSPIEXT	-	-	Fscb/4	MHz
SPI Slave Internally Clocked	FSPIIC	-	-	15	MHz
SPI Operating frequency Externally Clocked Slave	FSPI	-	-	18	MHz
SPI Operating frequency Master (Fscb is SPI clock)	FSPIEXT	-	-	18	MHz
SPI Slave Internally Clocked	FSPIIC	-	-	10	MHz
SPI Operating frequency Externally Clocked Slave	FSPI	-	-	12	MHz
SPI Operating frequency Master (Fscb is SPI clock)	FSPIEXT	-	-	12	MHz
SPI Slave Internally Clocked	FSPIIC	-	-	5	MHz
SPI Operating frequency Externally Clocked Slave	FSPIHS	-	-	50	MHz
SPI Operating frequency Master (Fscb is SPI clock)	FSPIEXTHS	-	-	Fscb/4	MHz
SPI Slave Internally Clocked	FSPIICHS	-	-	15	MHz
Master mode AC Specifications	Master mode AC Specifications	Master mode AC Specifications	Master mode AC Specifications	Master mode AC Specifications	Master mode AC Specifications
MOSI Valid after ScIock driving edge	TDMO	-	-	12	ns
MOSI Valid after ScIock driving edge	TDMOHS	-	-	5	ns
MISO Valid before ScIock capturing edge	TDSI	5	-	-	ns
MISO Valid before ScIock capturing edge	TDSIHS	3	-	-	ns
MOSI and MISO data hold time	THMO	2	-	-	ns
Slave mode AC Specifications	Slave mode AC Specifications	Slave mode AC Specifications	Slave mode AC Specifications	Slave mode AC Specifications	Slave mode AC Specifications
MOSI Valid before Sclock Capturing edge	TDMI	5	-	-	ns
MISO Valid after Sclock driving edge in Ext. Clk. mode	TDSOEXT	-	-	20	ns
MISO Valid after Sclock driving edge in Ext. Clk. mode	TDSOEXT	-	-	7	ns
MISO Valid after Sclock driving edge in Internally Clk. Mode	TDSO	-	-	TDSO_EXT + 3*Tscb	ns
MISO Valid after Sclock driving edge in Internally Clk. Mode with Median filter enabled.	TDSO	-	-	TDSO_EXT + 4*Tscb	ns
MOSI and MISO data hold time	THSO	2	-	-	ns
SSEL Valid to first SCK Valid edge	TSSELSCK1	65	-	-	ns
SSEL Hold after Last SCK Valid edge	TSSELSCK2	65	-	-	ns
System Resources System Resource System Resource	System Resources System Resource System Resource	System Resources System Resource System Resource	System Resources System Resource System Resource	System Resources System Resource System Resource	System Resources System Resource System Resource
Parameter	Symbol	Values	Values	Values	Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
with Brown-out DC specifications	with Brown-out DC specifications	with Brown-out DC specifications	with Brown-out DC specifications	with Brown-out DC specifications	with Brown-out DC specifications
VBAT BOD trip voltage in Active and Sleep modes.	VFALLPPOR	2.23	-	-	V
Maximum power supply ramp rate (any supply)	VDDRAMP	-	-	100	mV/ uSec
Maximum power supply ramp rate (any supply) in Deep Sleep	VDDR_DS	-	-	10	mV/ uSec
VDDD 1.8V BOD trip voltage in Active and Sleep modes.	VFALL1V8	1.53	-	-	V
Monitors AC specification	Monitors AC specification	Monitors AC specification	Monitors AC specification	Monitors AC specification	Monitors AC specification
VBAT Voltage monitor range	VMON	2.75	-	3.15
VBAT Voltage monitor error	VMON	-	0.3	-	%V
Single Wire Debug SWD and Trace Interface Single Wire Debug SWD and Trace Interface	Single Wire Debug SWD and Trace Interface Single Wire Debug SWD and Trace Interface	Single Wire Debug SWD and Trace Interface Single Wire Debug SWD and Trace Interface	Single Wire Debug SWD and Trace Interface Single Wire Debug SWD and Trace Interface	Single Wire Debug SWD and Trace Interface Single Wire Debug SWD and Trace Interface	Single Wire Debug SWD and Trace Interface Single Wire Debug SWD and Trace Interface
Parameter	Symbol	Values	Values	Values	Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
Trace Interface	Trace Interface	Trace Interface	Trace Interface	Trace Interface	Trace Interface
1.7 V <= VDDD <= 3.6 V	FSWDCLK2	-	-	25	MHz
T = 1/f SWDCLK	TSWDISETUP	0.25*T	-	-	ns
T = 1/f SWDCLK	TSWDIHOLD	0.25*T	-	-	ns
T = 1/f SWDCLK	TSWDOVALID	-	-	0.5*T	ns
T = 1/f SWDCLK	TSWDOHOLD	1	-	-	ns
With Trace Data setup/hold times of 2/1 ns respectively	FTRCLKLP1	-	-	50	MHz
With Trace Data setup/hold times of 3/2 ns respectively	FTRCLKLP2	-	-	50	MHz
Internal Oscillators Crystal Oscillators External Clock and PLLs Internal Oscillators Crystal Oscillators External Clock and PLLs	Internal Oscillators Crystal Oscillators External Clock and PLLs Internal Oscillators Crystal Oscillators External Clock and PLLs	Internal Oscillators Crystal Oscillators External Clock and PLLs Internal Oscillators Crystal Oscillators External Clock and PLLs	Internal Oscillators Crystal Oscillators External Clock and PLLs Internal Oscillators Crystal Oscillators External Clock and PLLs	Internal Oscillators Crystal Oscillators External Clock and PLLs Internal Oscillators Crystal Oscillators External Clock and PLLs	Internal Oscillators Crystal Oscillators External Clock and PLLs Internal Oscillators Crystal Oscillators External Clock and PLLs
Parameter	Symbol	Values	Values	Values	Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
Specifications	Specifications	Specifications	Specifications	Specifications	Specifications
IMO Operating current at 4.096 MHz	IIMO1	-	5	9	µA
Specifications	Specifications	Specifications	Specifications	Specifications	Specifications
Frequency variation centered on 4.096 MHz	FIMOTOL1	-1	-	1	%
Cycle-to-Cycle and Period jitter	TJITR	-	1	-	ns
Specifications	Specifications	Specifications	Specifications	Specifications	Specifications
IHO Operating current at 50 MHz	IIHO	-	115	-	µA
Specifications	Specifications	Specifications	Specifications	Specifications	Specifications
Frequency variation centered on 50 MHz	FIHOTOL1	-1	-	1	%
Specifications	Specifications	Specifications	Specifications	Specifications	Specifications
PILO Operating current	IPILO	-	1.15	-	µA
PILO Start-up time to 95% of final frequency	TSTARTPILO	-	-	150	µs
PILO Duty cycle	PILODUTY	45	50	55	%
PILO Temperature Drift	PILODRIFT	-	40	-	ppm/° c
PILO Accuracy	PILOACC	-	250	-	ppm
Specifications	Specifications	Specifications	Specifications	Specifications	Specifications
Block operating current with 32 kHz crystal	Idd_kHz	-	0.38	1.2	µA
Equivalent Series Resistance	ESR32K	-	80	-	kΩ
Drive Level	PD32K	-	-	1	µW
Specifications	Specifications	Specifications	Specifications	Specifications	Specifications
32 KHz trimmed frequency	F_kHz	-	32.768	-	KHz
Startup time	Ton_kHz	-	-	1000	ms
Frequency tolerance	FTOL32K	-	50	250	ppm
Specifications	Specifications	Specifications	Specifications	Specifications	Specifications
MHz oscillator current at 4 MHz	Idd4M	-	180	-	µA
MHz oscillator current at 16 MHz	Idd16M	-	360	-	µA
MHz oscillator current at 38 MHz	Idd38M	-	600	-	µA
External crystal load capacitance	Cload	-	-	18	pF
Specifications	Specifications	Specifications	Specifications	Specifications	Specifications
Crystal frequency range	ECOMHz	4	-	38	MHz
Clock Specifications	Clock Specifications	Clock Specifications	Clock Specifications	Clock Specifications	Clock Specifications
External Clock input Frequency	EXTCLKFREQ	0	-	100	MHz
Duty cycle; Measured at VDD/2	EXTCLKDUTY	45	-	55	%
Specifications Specifications	Specifications Specifications	Specifications Specifications	Specifications Specifications	Specifications Specifications	Specifications Specifications
Output frequency. HP mode.	PLLOUT	-	-	500	MHz
Output frequency. LP mode.	PLLOUT	-	-	350	MHz
Output frequency. ULP Mode.	PLLOUT	-	-	100	MHz
Phase Frequency Detector (PFD) input	PLLPFD	4	-	50	MHz
Period Jitter in integer operation	PLLJTR	3	-	3	%
Period Jitter in fractional operation	PLLJTRF	4	-	4	%
PLL Cold Start Lock Time (After Boot)	PLLLOCKCOLD	-	-	60	µs
Time to achieve PLL Lock with frequency change	PLLLOCK	-	-	20	µs
Clock input	PLLCLOCKIN	4	-	400	MHz
Specifications	Specifications	Specifications	Specifications	Specifications	Specifications
Output frequency. HP mode.	PLL_OUT	-	-	500	MHz
Output frequency. LP mode.	PLL_OUT	-	-	350	MHz
Output frequency. ULP mode.	PLL_OUT	-	-	100	MHz
Phase Frequency Detector (PFD) input	PLL_PFD	4	-	8	MHz
Period Jitter in integer operation	PLL_JTR	2	-	2	%
PLL Cold Start Lock Time (After Boot)	PLL_LOCKCOLD	-	-	60	µs
Time to achieve PLL Lock with frequency change	PLL_LOCK	-	-	20	µs
Clock input	PLL_CLOCKIN	4	-	128	MHz
Switching Time	Switching Time	Switching Time	Switching Time	Switching Time	Switching Time
Clock switching from clk1 to clk2 in clock periods	TCLKSWITCH	-	-	4 clk1 +3 clk2	period s

Table 53 (pages 121–121)

Table 53 · 13 columns × 28 rows · p.121–121 · CSV

	Parameter		Symbol		Min		Max
	Parameter	Parameter	Symbol	Symbol	Min	Min	HP	HP	LP	LP	ULP	ULP
Specifications	Specifications	Specifications	Specifications	Specifications	Specifications	Specifications	Specifications	Specifications	Specifications	Specifications	Specifications	Specifications
	Output frequency from PLL Block for Low Power PLL	Output frequency from PLL Block for Low Power PLL	PLL_OUT	PLL_OUT	-	-	500	500	350	350	100	100
	Output frequency from PLL Block for High Performance PLL	Output frequency from PLL Block for High Performance PLL	PLL_OUT	PLL_OUT	-	-	500	500	350	350	100	100
Serial Memory Interface SMIF Controller Serial Memory Interface SMIF Controller	Serial Memory Interface SMIF Controller Serial Memory Interface SMIF Controller	Serial Memory Interface SMIF Controller Serial Memory Interface SMIF Controller	Serial Memory Interface SMIF Controller Serial Memory Interface SMIF Controller	Serial Memory Interface SMIF Controller Serial Memory Interface SMIF Controller	Serial Memory Interface SMIF Controller Serial Memory Interface SMIF Controller	Serial Memory Interface SMIF Controller Serial Memory Interface SMIF Controller	Serial Memory Interface SMIF Controller Serial Memory Interface SMIF Controller	Serial Memory Interface SMIF Controller Serial Memory Interface SMIF Controller	Serial Memory Interface SMIF Controller Serial Memory Interface SMIF Controller	Serial Memory Interface SMIF Controller Serial Memory Interface SMIF Controller	Serial Memory Interface SMIF Controller Serial Memory Interface SMIF Controller	Serial Memory Interface SMIF Controller Serial Memory Interface SMIF Controller
Parameter	Parameter	Symbol	Symbol	Values	Values	Values	Values	Values	Values	Unit	Unit	Note condition
Parameter	Parameter	Symbol	Symbol	Min.	Min.	Typ.	Typ.	Max.	Max.	Unit	Unit	Note condition
Specifications. All specs with 15 pF Load. Switching levels are 50% clock to 30%/70% data flight/skew times.	Specifications. All specs with 15 pF Load. Switching levels are 50% clock to 30%/70% data flight/skew times.	Specifications. All specs with 15 pF Load. Switching levels are 50% clock to 30%/70% data flight/skew times.	Specifications. All specs with 15 pF Load. Switching levels are 50% clock to 30%/70% data flight/skew times.	Specifications. All specs with 15 pF Load. Switching levels are 50% clock to 30%/70% data flight/skew times.	Specifications. All specs with 15 pF Load. Switching levels are 50% clock to 30%/70% data flight/skew times.	Specifications. All specs with 15 pF Load. Switching levels are 50% clock to 30%/70% data flight/skew times.	Specifications. All specs with 15 pF Load. Switching levels are 50% clock to 30%/70% data flight/skew times.	Specifications. All specs with 15 pF Load. Switching levels are 50% clock to 30%/70% data flight/skew times.	Specifications. All specs with 15 pF Load. Switching levels are 50% clock to 30%/70% data flight/skew times.	Specifications. All specs with 15 pF Load. Switching levels are 50% clock to 30%/70% data flight/skew times.	Specifications. All specs with 15 pF Load. Switching levels are 50% clock to 30%/70% data flight/skew times.	Specifications. All specs with 15 pF Load. Switching levels are 50% clock to 30%/70% data flight/skew times.
SMIF xSPI output clock frequency	SMIF xSPI output clock frequency	Fsmifclock	Fsmifclock	-	-	-	-	200	200	MHz	MHz
SMIF HYPERBUS ™ output clock frequency	SMIF HYPERBUS ™ output clock frequency	Fsmifclockh	Fsmifclockh	-	-	-	-	166	166	MHz	MHz
™ /xSPI SDR and DDR	™ /xSPI SDR and DDR	™ /xSPI SDR and DDR	™ /xSPI SDR and DDR	™ /xSPI SDR and DDR	™ /xSPI SDR and DDR	™ /xSPI SDR and DDR	™ /xSPI SDR and DDR	™ /xSPI SDR and DDR	™ /xSPI SDR and DDR	™ /xSPI SDR and DDR	™ /xSPI SDR and DDR	™ /xSPI SDR and DDR
Interface frequency	Interface frequency	fCK	fCK	-	-	-	-	200	200	MHz	MHz
Allowable clock distortion	Allowable clock distortion	tCKDCD	tCKDCD	-	-	-	-	0.25	0.25	ns	ns
Minimum clock pulse width	Minimum clock pulse width	tCKMPW	tCKMPW	2.25	2.25	-	-	-	-	ns	ns
Output setup time of DS and IO[7:0] to CK	Output setup time of DS and IO[7:0] to CK	tOUTSETUP	tOUTSETUP	1.045	1.045	-	-	-	-	ns	ns
Output hold time of DS and IO[7:0] to CK	Output hold time of DS and IO[7:0] to CK	tOUTHOLD	tOUTHOLD	0.89	0.89	-	-	-	-	ns	ns
Input min pulse width of DS	Input min pulse width of DS	tINDSMPW	tINDSMPW	2.05	2.05	-	-	-	-	ns	ns
Input DS to IO[7:0] valid time	Input DS to IO[7:0] valid time	tINRQ	tINRQ	-	-	-	-	0.4	0.4	ns	ns
Input IO[7:0] invalid to DS time	Input IO[7:0] invalid to DS time	tINRQH	tINRQH	-	-	-	-	0.4	0.4	ns	ns
Input data valid time of IO[7:0]	Input data valid time of IO[7:0]	tINDV	tINDV	1.15	1.15	-	-	-	-	ns	ns
CK low to CS low	CK low to CS low	tCSCKLCSL	tCSCKLCSL	4	4	-	-	-	-	ns	ns
CS low to CK high	CS low to CK high	tCSCSLCKH	tCSCSLCKH	4	4	-	-	-	-	ns	ns
CK low to CS high	CK low to CS high	tCSCKLCSH	tCSCKLCSH	4	4	-	-	-	-	ns	ns
CS high to CK high	CS high to CK high	tCSCSHCKH	tCSCSHCKH	4	4	-	-	-	-	ns	ns
DS low to CS high	DS low to CS high	tCSDSLCSH	tCSDSLCSH	4	4	-	-	-	-	ns	ns
CS high to DS tristate	CS high to DS tristate	tCSCSHDST	tCSCSHDST	-	-	-	-	5	5	ns	ns
CS low to DS low	CS low to DS low	tCSCSLDSL	tCSCSLDSL	0	0	-	-	-	-	ns	ns
DS tristate to CS low	DS tristate to CS low	tCSDSTCSL	tCSDSTCSL	0	0	-	-	-	-	ns	ns

Table 54 (pages 122–128)

Table 54 · 6 columns × 168 rows · p.122–128 · CSV

Parameter	Symbol	Values			Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
QSPI SDR
Interface frequency	fCK	-	-	166	MHz
Clock pulse width	tCKPW	-	-	-	ns
CS# active setup to CK	tCSS	4	-	-	ns
CS# active hold to CK	tCSH0	4	-	-	ns
CS# High time (Read)	tCS	10	-	-	ns
CS# High time (Read when Reset feature and Quad mode are both enabled and aborted transaction)	tCS	20	-	-	ns
CS# High time (Program/Erase)	tCS	50	-	-	ns
Output setup time of DQ[7:0] to CK high	tOUT_SETUP	2.1	-	-	ns
Output hold time of DQ[7:0] to CK high	tOUT_HOLD	2.1	-	-	ns
CK low to DQ[7:0] input valid time	tINV	-	-	6.7	ns
CK low to DQ[7:0] input hold time	tINHO	1.5	-	-	ns
Input data valid time of DQ[7:0]	tINDV	3.8	-	-	ns
QSPI DDR	QSPI DDR	QSPI DDR	QSPI DDR	QSPI DDR	QSPI DDR
Interface frequency	fCK	-	-	100	MHz
Clock pulse width	tCKPW	-	-	-	ns
CS# active setup to CK	tCSS	4	-	-	ns
CS# active hold to CK (mode 0)	tCSH0	4	-	-	ns
CS# High time (Read)	tCS	10	-	-	ns
CS# High time (Read when Reset feature and Quad mode are both enabled and aborted transaction)	tCS	20	-	-	ns
CS# High time (Program/Erase)	tCS	50	-	-	ns
Output setup time of DQ[7:0] to CK edge	tOUTSETUP	2.1	-	-	ns
Output hold time of DQ[7:0] to CK edge	tOUTHOLD	1.3	-	-	ns
CK edge to DQ[7:0] input valid time	tINV	-	-	6.7	ns
CK edge to DQ[7:0] input hold time	tINHO	1.5	-	-	ns
Input data valid time of DQ[7:0]	tINDV	2.9	-	-	ns
SDHC and eMMC SDHC and eMMC	SDHC and eMMC SDHC and eMMC	SDHC and eMMC SDHC and eMMC	SDHC and eMMC SDHC and eMMC	SDHC and eMMC SDHC and eMMC	SDHC and eMMC SDHC and eMMC
Parameter	Symbol	Values	Values	Values	Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
eMMC Specifications (Block Clock must be divided by ≥ 2 when used as source in DDR50% clock to 30%/70% data level.	eMMC Specifications (Block Clock must be divided by ≥ 2 when used as source in DDR50% clock to 30%/70% data level.	eMMC Specifications (Block Clock must be divided by ≥ 2 when used as source in DDR50% clock to 30%/70% data level.	eMMC Specifications (Block Clock must be divided by ≥ 2 when used as source in DDR50% clock to 30%/70% data level.	eMMC Specifications (Block Clock must be divided by ≥ 2 when used as source in DDR50% clock to 30%/70% data level.	eMMC Specifications (Block Clock must be divided by ≥ 2 when used as source in DDR50% clock to 30%/70% data level.
IO drive select	SDDS	8	-	8	mA
Input transition time	SDTR	0.7	-	3	ns
Interface clock period	SDCLK	-	-	25	MHz
Frequency tolerance	SDDCMDCL	30	-	30	pF
IO loading at CLK pins	SDCLKCL	30	-	30	pF
Output: Setup time of CMD/DAT prior to CLK	SDTSOUT	5.1	-	-	ns
Output: Hold time of CMD/DAT after CLK	SDHLDOUT	5.1	-	-	ns
Input: Setup time of CMD/DAT prior to CLK	SDTSIN	24	-	-	ns
Input: Hold time of CMD/DAT after CLK	SDHLDIN	0	-	-	ns
Interface clock period	SDCLK	-	-	50	MHz
IO loading at DATA/CMD pins	SDDCMDCL	30	-	30	pF
IO loading at CLK pins	SDCLKCL	30	-	30	pF
Output: Setup time of CMD/DAT prior to CLK	SDTSOUT	6.1	-	-	ns
Output: Hold time of CMD/DAT after CLK	SDHLDOUT	2.1	-	-	ns
Input: Setup time of CMD/DAT prior to CLK	SDTSIN	5.8	-	-	ns
Input: Hold time of CMD/DAT after CLK	SDHLDIN	2.5	-	-	ns
timing	timing	timing	timing	timing	timing
Interface clock period	SDCLK	-	-	25	MHz
Dutycycle of output CLK	SDCLKDC	30	-	70	%
IO loading at DATA/CMD pins	SDDCMDCL	30	-	30	pF
IO loading at CLK pins	SDCLKCL	30	-	30	pF
Output: Setup time of CMD/DAT prior to CLK	SDTSOUT	3.1	-	-	ns
Output: Hold time of CMD/DAT after CLK	SDHLDOUT	0.9	-	-	ns
Input: Setup time of CMD/DAT prior to CLK	SDTSIN	24	-	-	ns
Input: Hold time of CMD/DAT after CLK	SDHLDIN	1.5	-	-	ns
timing	timing	timing	timing	timing	timing
Interface clock period	SDCLK	-	-	50	MHz
Dutycycle of output CLK	SDCLKDC	30	-	70	%
IO loading at DATA/CMD pins	SDDCMDCL	30	-	30	pF
IO loading at CLK pins	SDCLKCL	30	-	30	pF
Output: Setup time of CMD/DAT prior to CLK	SDTSOUT	3.1	-	-	ns
Output: Hold time of CMD/DAT after CLK	SDHLDOUT	0.9	-	-	ns
Input: Setup time of CMD/DAT prior to CLK	SDTSIN	5.8	-	-	ns
Input: Hold time of CMD/DAT after CLK	SDHLDIN	1.5	-	-	ns
timing	timing	timing	timing	timing	timing
Interface clock period	SDCLK	-	-	100	MHz
Dutycycle of output CLK	SDCLKDC	30	-	70	%
IO loading at DATA/CMD pins	SDDCMDCL	20	-	20	pF
IO loading at CLK pins	SDCLKCL	20	-	20	pF
Output: Setup time of CMD/DAT prior to CLK	SDTSOUT	3.1	-	-	ns
Output: Hold time of CMD/DAT after CLK	SDHLDOUT	0.9	-	-	ns
Input: Setup time of CMD/DAT prior to CLK	SDTSIN	4.8	-	-	ns
Input: Hold time of CMD/DAT after CLK	SDHLDIN	1.5	-	-	ns
timing	timing	timing	timing	timing	timing
Interface clock period	SDCLK	-	-	50	MHz
Dutycycle of output CLK	SDCLKDC	45	-	55	%
IO loading at DATA/CMD pins	SDDCMDCL	30	-	30	pF
IO loading at CLK pins	SDCLKCL	30	-	30	pF
Output: Setup time of CMD/DAT prior to CLK	SDTSOUT	3.1	-	-	ns
Output: Hold time of CMD/DAT after CLK	SDHLDOUT	0.9	-	-	ns
Input: Setup time of CMD/DAT prior to CLK	SDTSIN	5.3	-	-	ns
Input: Hold time of CMD/DAT after CLK	SDHLDIN	1.5	-	-	ns
timing	timing	timing	timing	timing	timing
Interface clock period	SDCLK	-	-	26	MHz
IO loading at DATA/CMD pins	SDDCMDCL	30	-	30	pF
IO loading at CLK pins	SDCLKCL	30	-	30	pF
Output: Setup time of CMD/DAT prior to CLK	SDTSOUT	3.1	-	-	ns
Output: Hold time of CMD/DAT after CLK	SDHLDOUT	3.1	-	-	ns
Input: Setup time of CMD/DAT prior to CLK	SDTSIN	9.7	-	-	ns
Input: Hold time of CMD/DAT after CLK	SDHLDIN	8.3	-	-	ns
timing	timing	timing	timing	timing	timing
Interface clock period	SDCLK	-	-	52	MHz
IO loading at DATA/CMD pins	SDDCMDCL	30	-	30	pF
IO loading at CLK pins	SDCLKCL	30	-	30	pF
Output: Setup time of CMD/DAT prior to CLK	SDTSOUT	3.1	-	-	ns
Output: Hold time of CMD/DAT after CLK	SDHLDOUT	3.1	-	-	ns
Input: Setup time of CMD/DAT prior to CLK	SDTSIN	5.3	-	-	ns
Input: Hold time of CMD/DAT after CLK	SDHLDIN	2.5	-	-	ns
timing	timing	timing	timing	timing	timing
Interface clock period	SDCLK	-	-	52	MHz
Dutycycle requirement at output CLK	SDCLKDC	45	-	55	%
IO loading at DATA/CMD pins	SDDCMDCL	20	-	20	pF
IO loading at CLK pins	SDCLKCL	20	-	20	pF
Output: Setup time of CMD/DAT prior to CLK	SDTSOUT	2.6	-	-	ns
Output: Hold time of CMD/DAT after CLK	SDHLDOUT	2.6	-	-	ns
Input: Setup time of CMD/DAT prior to CLK	SDTSIN	10	-	-	ns
Input: Hold time of CMD/DAT after CLK	SDHLDIN	1.5	-	-	ns
Audio Sub system Audio Sub system	Audio Sub system Audio Sub system	Audio Sub system Audio Sub system	Audio Sub system Audio Sub system	Audio Sub system Audio Sub system	Audio Sub system Audio Sub system
Parameter	Symbol	Values	Values	Values	Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
Specifications	Specifications	Specifications	Specifications	Specifications	Specifications
PDM Active current, Stereo operation, 1 MHz clock	PDMIDD1	-	175	-	µA
PDM Active current, Stereo operation, 3 MHz clock	PDMIDD2	-	600	-	µA
RMS Jitter in PDM clock	PDMJITTER	-200	-	200	ps
PDM Clock speed	PDMCLK	0.384	-	3.072	MHz
PDM Block input clock	PDMBLKCLK	1.024	-	49.152	MHz
Data input set-up time to PDM_CLK edge	PDMSETUP	10	-	-	ns
Data input hold time after PDM_CLK edge	PDMHOLD	10	-	-	ns
Audio sample rate	PDMOUT	8	-	48	ksps
Word Length	PDMWL	16	-	24	bits
Signal-to-Noise Ratio (A-weighted 0	PDMSNR	-	100	-	dB
Dynamic Range (A-weighted)	PDMDR	-	100	-	dB
Frequency Response	PDMFR	-0.2	-	0.2	dB
Stop Band	PDMSB	-	0.566*f	-	kHz
Stop Band Attenuation	PDMSBA	-	60	-	dB
AdjusTable Gain	PDMGAIN	-12	-	10.5	dB
Startup time	PDMST	-	48	-
Specifications.	Specifications.	Specifications.	Specifications.	Specifications.	Specifications.
Length of I2S Word	I2SWORD	8	-	32	bits
Word Clock frequency	I2SWS	-	-	192	kHz
Word Clock frequency in TDM mode	I2SWSTDM	-	-	48	kHz
Mode	Mode	Mode	Mode	Mode	Mode
WS Setup Time to the Following Rising Edge of SCK	TSWS	5	-	-	ns
WS Hold Time to the Following Edge of SCK	THWS	TMCLK_SOC+5	-	-	ns
Delay Time of TX_SDO Transition from Edge of TX_SCK	TDSDO	-(TMCLK_SOC+25)	-	TMCLK_SOC+25	ns
RX_SDI Setup Time to the Following Edge of RX_SCK in	TSSDI	5	-	-	ns
RX_SDI Hold Time after the Rising Edge of RX_SCK	THSDI	TMCLK_SOC+5	-	-	ns
TX/RX_SCK Bit Clock Duty Cycle	TSCKCY	45	-	55	%
Mode	Mode	Mode	Mode	Mode	Mode
WS Transition Delay from Associated Edge of SCK	TDWS	10	-	20	ns
SDO Transition Delay from Associated Edge of SCK	TDSDO	10	-	20	ns
SDI Setup Time to the Associated Edge of SCK	TSSDI	5	-	-	ns
SDI Hold Time after the Associated Edge of SCK	THSDI	TMCLK_SOC+5	-	-	ns
SCK Bit Clock Duty Cycle	TSCKCY	45	-	55	%
MCLK_SOC Frequency	FMCLKSOC	1.024	-	98.304	MHz
MCLK_SOC Duty Cycle	TMCLKCY	45	-	55	%
MCLK_SOC Input Jitter	TJITTER	-100	-	100	ps
Ethernet MAC Ethernet MAC	Ethernet MAC Ethernet MAC	Ethernet MAC Ethernet MAC	Ethernet MAC Ethernet MAC	Ethernet MAC Ethernet MAC	Ethernet MAC Ethernet MAC
Parameter	Symbol	Values	Values	Values	Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
MAC Frequency Range	Tfreq	10	-	100	Mbits/ sec
CAN FD CAN FD	CAN FD CAN FD	CAN FD CAN FD	CAN FD CAN FD	CAN FD CAN FD	CAN FD CAN FD
Parameter	Symbol	Values	Values	Values	Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
CAN Bit rate (Min 8 MHz clock)	CANrate	-	-	5	Mbit
JTAG and Boundary Scan JTAG and Boundary Scan	JTAG and Boundary Scan JTAG and Boundary Scan	JTAG and Boundary Scan JTAG and Boundary Scan	JTAG and Boundary Scan JTAG and Boundary Scan	JTAG and Boundary Scan JTAG and Boundary Scan	JTAG and Boundary Scan JTAG and Boundary Scan
Parameter	Symbol	Values	Values	Values	Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
TCK low	TCKLOW	52	-	-	ns
TCK high	TCKHIGH	10	-	-	ns
TCK falling edge to output valid	TCKTDO	-	-	40	ns
Input valid to TCK rising edge	TSUTCK	12	-	-	ns
Input hold time after TCK rising edge	TCkTHD	10	-	-	ns
TCK falling edge to output valid	TCKTDOV	-	-	40	ns
TCK falling edge to output High-Z	TCKTDOZ	-	-	40	ns
USB HS USB HS	USB HS USB HS	USB HS USB HS	USB HS USB HS	USB HS USB HS	USB HS USB HS
Parameter	Symbol	Values	Values	Values	Unit
Parameter	Symbol	Min.	Typ.	Max.	Unit
HS Data Rate	USBHS	-	-	480	Mbits/ sec

Table 55 (pages 129–129)

Table 55 · 12 columns × 18 rows · p.129–129 · CSV

Parameter			Symbol		Values				Unit		Note condition
Parameter			Symbol		Min.		Typ.	Max.	Unit		Note condition
D-PHY data rate per lane	D-PHY data rate per lane	D-PHY data rate per lane	MIPIFS	MIPIFS	500	500	-	1500	Mbits/ sec	Mbits/ sec
MIPI DBI MIPI DBI	MIPI DBI MIPI DBI	MIPI DBI MIPI DBI	MIPI DBI MIPI DBI	MIPI DBI MIPI DBI	MIPI DBI MIPI DBI	MIPI DBI MIPI DBI	MIPI DBI MIPI DBI	MIPI DBI MIPI DBI	MIPI DBI MIPI DBI	MIPI DBI MIPI DBI	MIPI DBI MIPI DBI
Parameter	Parameter	Parameter	Symbol	Symbol	Values	Values	Values	Values	Unit	Unit	Note condition
Parameter	Parameter	Parameter	Symbol	Symbol	Min.	Min.	Typ.	Max.	Unit	Unit	Note condition
GPIO frequency for DBI Type C interface	GPIO frequency for DBI Type C interface	GPIO frequency for DBI Type C interface	DBICFreq	DBICFreq	-	-	-	50	MHz	MHz
GPIO frequency for DBI Type A and B interfaces	GPIO frequency for DBI Type A and B interfaces	GPIO frequency for DBI Type A and B interfaces	DBIABFreq	DBIABFreq	-	-	-	50	MHz	MHz
I3C I3C	I3C I3C	I3C I3C	I3C I3C	I3C I3C	I3C I3C	I3C I3C	I3C I3C	I3C I3C	I3C I3C	I3C I3C	I3C I3C
Parameter	Parameter	Parameter	Symbol	Symbol	Values	Values	Values	Values	Unit	Unit	Note condition
Parameter	Parameter	Parameter	Symbol	Symbol	Min.	Min.	Typ.	Max.	Unit	Unit	Note condition
HDR-DDR data rate	HDR-DDR data rate	HDR-DDR data rate	I3CF1	I3CF1	-	-	-	25	Mbps	Mbps	At 0.9
HDR-DDR data rate	HDR-DDR data rate	HDR-DDR data rate	I3CF2	I3CF2	-	-	-	12	Mbps	Mbps	At 0.8
HDR-DDR data rate	HDR-DDR data rate	HDR-DDR data rate	I3CF3	I3CF3	-	-	-	6	Mbps	Mbps	At 0.7
NNlite NNlite	NNlite NNlite	NNlite NNlite	NNlite NNlite	NNlite NNlite	NNlite NNlite	NNlite NNlite	NNlite NNlite	NNlite NNlite	NNlite NNlite	NNlite NNlite	NNlite NNlite
	Description	Symbol	Symbol	Values	Values	Values	Values	Values	Values	Unit	Unit
	Description	Symbol	Symbol	Min.	Min.	Typ.	Typ.	Max.	Max.	Unit	Unit
	NNLite operating frequency in system HP mode	FNNLITE	FNNLITE	0	0	-	-	200	200	MHz	MHz
	NNLite operating frequency in system LP mode	FNNLITE	FNNLITE	0	0	-	-	80	80	MHz	MHz
	NNLite operating frequency in system ULP mode	FNNLITE	FNNLITE	0	0	-	-	50	50	MHz	MHz

Table 56 (pages 131–131)

Table 56 · 6 columns × 23 rows · p.131–131 · CSV

Package	System SRAM (KB)	U55	GFX	Security	I/O Count
BGA-220	5120	Y	Y	EPC4	147
BGA-220	5120	Y	Y	EPC2	147
BGA-220	4096	Y	Y	EPC4	147
BGA-220	4096	Y	Y	EPC2	147
WLB-154	5120	Y	Y	EPC4	101
WLB-154	5120	Y	Y	EPC2	101
eWLB-235	5120	Y	Y	EPC2	147
WLB-154	4096	Y	Y	EPC4	101
eWLB-235	4096	Y	Y	EPC4	147
WLB-154	4096	Y	Y	EPC2	101
eWLB-235	4096	Y	Y	EPC2	147
eWLB-235	5120	Y	Y	EPC4	147
WLB-154	4096	Y	N	EPC4	101
WLB-154	4096	Y	N	EPC2	101
BGA-220	4096	Y	N	EPC2	147
WLB-154	2048	Y	N	EPC4	101
BGA-220	2048	Y	N	EPC4	147
WLB-154	2048	Y	N	EPC2	101
BGA-220	2048	Y	N	EPC2	147
BGA-220	4096	Y	N	EPC4	147
WLB-154	4096	N	Y	EPC4	101
WLB-154	4096	N	Y	EPC2	101
BGA-220	4096	N	Y	EPC2	147

Table 57 (pages 132–132)

Table 57 · 9 columns × 26 rows · p.132–132 · CSV

	Package	System SRAM (KB)		U55		GFX	Security	I/O Count
	WLB-154	2048	2048	N	N	Y	EPC4	101
	BGA-220	2048	2048	N	N	Y	EPC4	147
	WLB-154	2048	2048	N	N	Y	EPC2	101
	BGA-220	2048	2048	N	N	Y	EPC2	147
	BGA-220	4096	4096	N	N	Y	EPC4	147
E81	E81	E81	E81	E81	E81	E81	E81	E81
	WLB-154	4096	4096	N	N	N	EPC4	101
	BGA-220	4096	4096	N	N	N	EPC4	147
	WLB-154	4096	4096	N	N	N	EPC2	101
	BGA-220	4096	4096	N	N	N	EPC2	147
	WLB-154	2048	2048	N	N	N	EPC4	101
	BGA-220	2048	2048	N	N	N	EPC4	147
	WLB-154	2048	2048	N	N	N	EPC2	101
	BGA-220	2048	2048	N	N	N	EPC2	147
Part number nomenclature SX W C PK T X ES R S Product nomenclature	Part number nomenclature SX W C PK T X ES R S Product nomenclature	Part number nomenclature SX W C PK T X ES R S Product nomenclature	Part number nomenclature SX W C PK T X ES R S Product nomenclature	Part number nomenclature SX W C PK T X ES R S Product nomenclature	Part number nomenclature SX W C PK T X ES R S Product nomenclature	Part number nomenclature SX W C PK T X ES R S Product nomenclature	Part number nomenclature SX W C PK T X ES R S Product nomenclature	Part number nomenclature SX W C PK T X ES R S Product nomenclature
Description	Description	Description	Value	Value	Meaning	Meaning	Meaning	Meaning
Brand	Brand	Brand	PS	PS	PSOC ™	PSOC ™	PSOC ™	PSOC ™
Family	Family	Family	E	E	PSOC ™ Edge	PSOC ™ Edge	PSOC ™ Edge	PSOC ™ Edge
Series	Series	Series	8	8	E8 series	E8 series	E8 series	E8 series
Line	Line	Line	1	1	Base	Base	Base	Base
Line	Line	Line	2	2	Graphics	Graphics	Graphics	Graphics
Line	Line	Line	3	3	AI/ML	AI/ML	AI/ML	AI/ML
Line	Line	Line	4	4	Graphics + AI/ML	Graphics + AI/ML	Graphics + AI/ML	Graphics + AI/ML
Features (sub-families)	Features (sub-families)	Features (sub-families)	7-9	7-9	Performance	Performance	Performance	Performance
Features (sub-families)	Features (sub-families)	Features (sub-families)	4-6	4-6	Main	Main	Main	Main
Features (sub-families)	Features (sub-families)	Features (sub-families)	1-3	1-3	Entry	Entry	Entry	Entry

Table 58 (pages 133–133)

Table 58 · 2 columns × 25 rows · p.133–133 · CSV

Description	Value
Memory size (NVM, SRAM)	A/B/C/D/E/F/G/HK/L/M/N/O/P/Q/R S/T/U/V/W/X/Y
Security features (optional)	Blank
Security features (optional)	S1
Security features (optional)	S2
Security features (optional)	S4
Wireless (optional)	Blank
Wireless (optional)	B
Wireless (optional)	W
CPU core (optional)	Blank
CPU core (optional)	D
CPU core (optional)	T
CPU core (optional)	Q
Package	BZ
Package	FM
Package	FN
Temperature range	C
Temperature range	I
Temperature range	Q
Temperature range	M
Max frequency	0
Max frequency	1
Max frequency	2
Max frequency	3
Max frequency	4
Engineering sample (optional)	Blank
Engineering sample (optional)	ES
Tape/Reel Shipment (optional)	Blank
Tape/Reel Shipment (optional)	T

Table 59 (pages 134–134)

Table 59 · 2 columns × 3 rows · p.134–134 · CSV

Package	Maximum peak temperature Maximum time at peak temperature
All packages	260°C 30 seconds
Table 55	Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-2
Package	MSL
BGA-220	MSL3
eWLB-235	MSL1
WLB-154	MSL1

Table 60 (pages 138–138)

Table 60 · 2 columns × 0 rows · p.138–138 · CSV

PSOC ™ Edge E8	Silicon revision
All	1 (B0)
All	1 (B0)
All	1 (B0)

Table 61 (pages 146–146)

Table 61 · 3 columns × 2 rows · p.146–146 · CSV

Document revision	Date	Description of changes
*J	2025-11-04	Release to web
*K	2026-03-24	Added LPComp interrupt glitch errata to the Errata
		section.
		Added ETF support in the Processors section.