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TLV9061, TLV9062, TLV9064 SBOS839N – MARCH 2017 – REVISED JULY 2026

TLV906xS 10MHz, RRIO, CMOS Operational Amplifiers for Cost-Sensitive Systems

1 Features

• • • • • • • • • •

• • Rail-to-rail input and output Low input offset voltage: ±0.3mV Unity-gain bandwidth: 10MHz Low broadband noise: 10nV/√ Hz Low input bias current: 0.5pA Low quiescent current: 538µA Unity-gain stable Internal RFI and EMI filter Operational at supply voltages as low as 1.8V Easier to stabilize with higher capacitive load due to resistive open-loop output impedance Shutdown version: TLV906xS Extended temperature range: –40°C to 125°C The TLV906xS devices include a shutdown mode that allow the amplifiers to switch into standby mode with typical current consumption less than 1µA. The TLV906xS family helps simplify system design, because the family is unity-gain stable, integrates the RFI and EMI rejection filter, and provides no phase reversal in overdrive condition. Micro size packages, such as X2SON and X2QFN, are offered for all the channel variants (single, dual and quad), along with industry-standard packages, such as SOIC, MSOP, SOT-23, and TSSOP.

Device Information PART NUMBER (3)

2 Applications

• • • • • • • • • • E-bikes Smoke detectors HVAC: heating, ventilating, and air conditioning Motor control: AC induction Refrigerators Wearable devices Washing machines Power modules Active Filters Low-side current sensing

3 Description

The TLV9061 (single), TLV9062 (dual), and TLV9064 (quad) are single-, dual-, and quad- low-voltage, 1.8V to 5.5V) operational amplifiers, op amps) with rail-torail input and output swing capabilities. These devices are highly cost-effective options for applications where low-voltage operation, a small footprint, and high capacitive load drive are required. Although the capacitive load drive of the TLV906x is 100pF, the resistive open-loop output impedance makes stabilizing with higher capacitive loads simpler. These op amps are designed specifically for lowvoltage operation (1.8V to 5.5V), with performance specifications similar to the OPAx316 and TLVx316 devices.

TLV9061 TLV9061S TLV9062 TLV9062S TLV9064 TLV9064S

(1) (2) (3) (4)

PACKAGE (1) BODY SIZE (NOM) (4)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.

TLV9061, TLV9062, TLV9064 www.ti.com SBOS839N – MARCH 2017 – REVISED JULY 2026 R G 60 R F R 1 V OUT V IN

40 30 2 (%)

50 Small-Signal Overshoot vs Load Capacitance Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

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Table of Contents

1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Device Comparison Table...............................................4 5 Pin Configuration and Functions...................................5 6 Specifications................................................................ 10

6.1 Absolute Maximum Ratings...................................... 10 6.2 ESD Ratings............................................................. 10 6.3 Recommended Operating Conditions.......................10 6.4 Thermal Information: TLV9061..................................11 6.5 Thermal Information: TLV9061S............................... 11 6.6 Thermal Information: TLV9062..................................11 6.7 Thermal Information: TLV9062S............................... 12 6.8 Thermal Information: TLV9064................................. 12 6.9 Thermal Information: TLV9064S............................... 12 6.10 Electrical Characteristics.........................................13 6.11 Typical Characteristics............................................ 15 7 Detailed Description......................................................21

7.1 Overview................................................................... 21 7.2 Functional Block Diagram......................................... 21 7.3 Feature Description...................................................22 7.4 Device Functional Modes..........................................23 8 Application and Implementation.................................. 24

8.1 Application Information............................................. 24 8.2 Typical Applications.................................................. 24 8.3 Power Supply Recommendations.............................25 8.4 Layout....................................................................... 27 9 Device and Documentation Support............................29

9.1 Documentation Support............................................ 29 9.2 Receiving Notification of Documentation Updates....29 9.3 Support Resources................................................... 29 9.4 Trademarks............................................................... 29 9.5 Electrostatic Discharge Caution................................29 9.6 Glossary....................................................................29 10 Revision History.......................................................... 29 11 Mechanical, Packaging, and Orderable

Information.................................................................... 32 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

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4 Device Comparison Table

DUSON DRY SOT-23 DBV SC-70 DCK VSSOP DGK VSSOP DSBGA X2SON DGS YCK DPW SOT-55

3 DRL WSON DSG TSSOP

PW SOT-23 DDF WQFN RTE X2QFN RUC X2QFN RUG 8 — 5 5 — — — 5 5 — — — — — —

— 6 6 — — — — — — — — — — — —

8 — — — 8 10 — — — 8 8 8 — — —

— — — — — 10 9 — — — — — — — 10

14 — — — — — — — — — 14 — 16 14 —

— — — — — — — — — — — — 16 — — Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

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5 Pin Configuration and Functions

OUT 1 6 V+ +IN 1 6 V+ V– 2 5 SHDN V± 2 5 SHDN

Not to scale Not to scale Figure 5-4. TLV9061S DBV Package, 6-Pin SOT-23

(Top View)

Figure 5-5. TLV9061S DRY Package, 6-Pin USON

(Top View)

Table 5-2. Pin Functions: TLV9061S PIN NAME TYPE (1) DESCRIPTION SOT-23 USON IN– 4 3 I Inverting input IN+ 3 1 I Noninverting input OUT 1 4 O Output SHDN 5 5 I Shutdown: low = amp disabled, high = amp enabled. See Shutdown Function section for more information.

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Table 5-2. Pin Functions: TLV9061S (continued) PIN NAME TYPE (1) SOT-23 USON V– 2 2 I or — V+ 6 6 I

(1)

DESCRIPTION Negative (low) supply or ground (for single-supply operation) Positive (high) supply

OUT1 1 8 V+

IN1+ (1)

1 10 V+

SHDN1 5 6 SHDN2

SHDN1 2 8 OUT1 SHDN2 3 7 V+ IN2+ 4 6 OUT2 5 10 OUT1 Not to scale 6 IN2± Not to scale Figure 5-8. TLV9062S DGS Package, 10-Pin VSSOP

(Top View) Figure 5-9. TLV9062S RUG Package, 10-Pin X2QFN

(Top View)

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Figure 5-10. TLV9062S YCK Package

9-Pin DSBGA (WCSP)

Bottom View

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www.ti.com OUT4 IN4± 14 13 IN4+ OUT1 OUT4 11 IN1± 2 IN4±

15 IN1+ 12

16 1 13 IN1± 14 OUT1 SBOS839N – MARCH 2017 – REVISED JULY 2026 IN1+ 1 12 IN4+

IN2+ 3 IN2± 4 Figure 5-11. TLV9064 RUC Package, 14-Pin X2QFN

(Top View)

A.

8 OUT3 OUT2 Not to scale 7 IN3±

NC 8

OUT3 IN3+

6 5 9 Pad 5 IN2± V± NC 4

6 IN2+ 10 OUT2 3 7 V+ 10 IN3+ 9 IN3± Not to scale Connect thermal pad to V– Figure 5-12. TLV9064 RTE Package, 16-Pin WQFN

With Exposed Thermal Pad (Top View)

OUT1 1 14 OUT4

IN1+ 3 12 IN4+

IN2+ 5 10 IN3+

OUT2 7 8 OUT3 Not to scale Figure 5-13. TLV9064 D or PW Package, 14-Pin SOIC or TSSOP (Top View)

8 Submit Document Feedback Negative (low) supply or ground (for single-supply operation) Positive (high) supply Copyright © 2026 Texas Instruments Incorporated Product Folder Links: TLV9061 TLV9062 TLV9064 TLV9061, TLV9062, TLV9064 www.ti.com IN1+ 1 V+ 2

16 15 14 13 SBOS839N – MARCH 2017 – REVISED JULY 2026 12 IN4+

10 IN3+

Thermal A.

6 7 8 SHDN34 OUT3 4 SHDN12 IN2± Pad 5 3 OUT2 IN2+ Not to scale Connect thermal pad to V– Figure 5-14. TLV9064S RTE Package, 16-Pin WQFN With Exposed Thermal Pad (Top View)

Table 5-6. Pin Functions: TLV9064S PIN NAME NO.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating ambient temperature (unless otherwise noted) (1)

MIN Supply voltage [(V+) – (V–)]

Common-mode Voltage (2) Signal input pins V (V+) – (V–) + 0.2 V

10 mA

mA –40 125

150 Storage, T stg (3)

VJunction, T J Temperature (2)

6 (V+) + 0.5 Continuous Specified, T A (1)

0 –10 Output short-circuit (3)

UNIT (V–) – 0.5 Differential Current (2)

MAX –65 °C 150

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Input pins are diode-clamped to the power-supply rails. Current limit input signals that can swing more than 0.5V beyond the supply rails to 10mA or less. Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT TLV9061 PACKAGES V (ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2500 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500 Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±4000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500 V ALL OTHER PACKAGES V (ESD) Electrostatic discharge (1) (2)

VJEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating ambient temperature range (unless otherwise noted)

V S Supply voltage (V S = [V+] – [V–]) V I Input voltage range V O Output voltage range V SHDN_IH High level input voltage at shutdown pin (amplifier enabled) V SHDN_IL Low level input voltage at shutdown pin (amplifier disabled) T A Specified temperature 10 Submit Document Feedback MIN MAX UNIT 1.8 5.5 V (V–) – 0.1 (V+) + 0.1 V

V– V+ V 1.1 V+ V V– 0.2 V –40 125 °C Copyright © 2026 Texas Instruments Incorporated Product Folder Links: TLV9061 TLV9062 TLV9064

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8 PINS 8 PINS 8 PINS 8 PINS 8 PINS R θJA Junction-to-ambient thermal resistance 157.6 201.2 94.4 205.1 184.4 °C/W R θJC(top) Junction-to-case (top) thermal resistance 104.6 85.7 116.5 93.7 112.8 °C/W R θJB Junction-to-board thermal resistance 99.7 122.9 61.3 135.7 99.9 °C/W ψ JT Junction-to-top characterization parameter 55.6 21.2 13 25.0 18.7 °C/W ψ JB Junction-to-board characterization parameter 99.2 121.4 61.7 134.0 99.3 °C/W R θJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A 34.4 N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

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6.10 Electrical Characteristics

For V S (Total Supply Voltage) = (V+) – (V–) = 1.8V to 5.5V at T A = 25°C, R L = 10 kΩ connected to V S / 2, V CM = V S / 2, and V OUT = V S / 2 (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX

UNIT OFFSET VOLTAGE V OS Input offset voltage

PSRR Power-supply rejection ratio V S = 1.8V – 5.5V, V CM = (V–) ±7

Channel separation, DC At DC 100

mV µV/°C ±80 µV/V

dB INPUT VOLTAGE RANGE V CM CMRR Common-mode voltage range Common-mode rejection ratio

VdB

INPUT BIAS CURRENT I B Input bias current ±0.5 pA I OS Input offset current ±0.05 pA NOISE E n Input voltage noise (peak-to- peak)

e n Input voltage noise density i n Input current noise density

INPUT CAPACITANCE C ID Differential 2 pF C IC Common-mode 4 pF OPEN-LOOP GAIN

A OL Open-loop voltage gain

100 104 130

dB

FREQUENCY RESPONSE GBP Gain bandwidth product V S = 5V, G = +1 10 φ m Phase margin V S = 5V, G = +1 55 MHz

° SR Slew rate V S = 5V, G = +1 6.5 V/µs

t S Settling time To 0.01%, V S = 5V, 2V step,

t OR Overload recovery time V S = 5V, V IN × gain > V S THD + N Total harmonic distortion + noise (1) V S = 5.5V, V CM = 2.5V, V O = 1V RMS , G = +1, f = 1kHz

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6.10 Electrical Characteristics (continued)

For V S (Total Supply Voltage) = (V+) – (V–) = 1.8V to 5.5V at T A = 25°C, R L = 10 kΩ connected to V S / 2, V CM = V S / 2, and V OUT = V S / 2 (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Z O Open-loop output impedance V S = 5V, f = 10MHz 100 Ω

POWER SUPPLY I Q Quiescent current per amplifier

750 800 µA SHUTDOWN I QSD Quiescent current per amplifier V S = 1.8V to 5.5V, all amplifiers disabled, SHDN = Low Z SHDN Output impedance during shutdown V S = 1.8V to 5.5V, amplifier disabled

0.5 1.5 10 || 8 (V–) + 0.9V (V–) + 0.2V µA GΩ || pF (V–) + 1.1V V (V–) + 0.7V V t ON (2) Amplifier enable time (shutdown) V S = 1.8V to 5.5V, full shutdown; G = 1, V

OUT = 0.9 × V S / 2, R L connected to V– 10 µs t OFF Amplifier disable time (2) V S = 1.8V to 5.5V, G = 1, V OUT = 0.1 × V S / 2, R

L connected to V– 0.6 µs SHDN pin input bias current (per pin)

pA (1) (2)

Disable time (t OFF ) and enable time (t ON ) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.

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6.11 Typical Characteristics

at T A = 25°C, V S = 5.5V, R L = 10kΩ connected to V S / 2, V CM = V S / 2, and V OUT = V S / 2 (unless otherwise noted)

35 50 30

40 Population (%) Population (%)

25 20 15 30 20

10

10 Offset Voltage (µV)

2.8 2.4 2 1.6 1.2 0.8 1500 1250 750 1000 500 250 0 -250 -500 -750 -1000 -1250 -1500 0 0 0 0.4 5 Offset Voltage Drift (µV/C)

C002 C001 Figure 6-1. Offset Voltage Production Distribution T A = –40°C to 125°C 500 2500

400 2000

300 1500 Voltage (µV)

Offset Voltage (µV)

Figure 6-2. Offset Voltage Drift Distribution 200

100

0 1000

500

0

-3 -2 -1 0 1 2 3 4 Input Common Mode Voltage (V) C003 Figure 6-3. Offset Voltage vs Temperature V+ = 2.75V C005 V– = –2.75V

Figure 6-4. Offset Voltage vs Common-Mode

Voltage 1000 120 180 500 0 ±500 100 Phase 135 80 60

90 40 20 45

0

Supply Voltage (V)

Frequency (Hz) C004 C006

Figure 6-5. Offset Voltage vs Power Supply Phase Margin (deg)

Open Loop Voltage Gain (dB)

Offset Voltage (µV)

Gain Figure 6-6. Open-Loop Gain and Phase vs

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Open Loop Voltage Gain (µV/V)

20 VS = 1.8 V 16 12 8 4 30 20 10 0

0

Temperature (ƒC)

Figure 6-8. Closed-Loop Gain vs Frequency R L = 2kΩ

250 3

IBN

200 2 IBP

IOS

Voltage (V)

Current and offset current (pA)

Figure 6-7. Open-Loop Gain vs Temperature

150 100 50 0 125ƒC 1 -40ƒC 85ƒC

25ƒC

0

Figure 6-10. Output Voltage Swing vs Output Current

120 55

CMRR

PSRR-

50 PSRR+ 80 CMRR (µV/V)

PSRR and CMRR (dB)

100 60 40 20 0 1000 45 40 35 10k 100k 1M

Frequency (Hz)

10M C011

Figure 6-11. CMRR and PSRR vs Frequency (Referred to Input)

30

125 C012

Figure 6-12. CMRR vs Temperature

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9

9 7 PSRR (µV/V) CMRR (µV/V)

8 6

5

4

3 8 7 6 2

Figure 6-14. PSRR vs Temperature Figure 6-13. CMRR vs Temperature

Time (1s/div)

C014

Figure 6-15. 0.1Hz to 10Hz Input Voltage Noise

,QSXW 9ROWDJH 1RLVH 6SHFWUDO 'HQVLW\ Q9 ¥+] Voltage (1µV/div)

120 100 80 60 40 20 0

10 100 1k 10k 100k

Frequency (Hz) C015

Figure 6-16. Input Voltage Noise Spectral Density vs Frequency

±95 THD + N (dB)

THD + N (dB)

±60 ±100 ±105 ±110 ±80 ±100 ±115 ±120

0.001

Figure 6-17. THD + N vs Frequency

0.01 0.1 1 Output Voltage Amplitude (V RMS ) C017

C018 G = +1 f = 1kHz

Figure 6-18. THD + N vs Amplitude

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www.ti.com SBOS839N – MARCH 2017 – REVISED JULY 2026 600 Quiescent current (µA)

±40 THD + N (dB)

±60 ±80 ±100 580 560 540 520

Output Voltage Amplitude (V RMS )

2 2.5

3 3.5 4 4.5 5 5.5 Supply Voltage (V) C019 C020

Figure 6-20. Quiescent Current vs Supply Voltage Figure 6-19. THD + N vs Amplitude

800 Open Loop Output Impedance (Ÿ)

200 Quiescent Current (µA)

700 600 500 400 300 200 100 160 120 40

Temperature (ƒC)

50 40 40

Overshoot (%)

50 20 C024 30 20 10 Overshoot+ Overshoot(+)

Overshoot- Overshoot(-) 0 0

0 50 100 150 200

Capacitive Load (pF) V+ = 2.75V V OUT step = 100mV p-p

250 300 0 50 G = +1V/V 100 150 200 Capacitive Load (pF) C025

Figure 6-23. Small-Signal Overshoot vs Load Capacitance

18 10M

Figure 6-22. Open-Loop Output Impedance vs Frequency

60 30 1M Frequency (Hz)

60 10 100k C021

Figure 6-21. Quiescent Current vs Temperature

Overshoot (%)

80 V+ = 2.75V V OUT step = 100mV p-p

250 300 C026 G = –1V/V

Figure 6-24. Small-Signal Overshoot vs Load Capacitance

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www.ti.com Voltage (2 V/V)

Voltage (1V/div)

SBOS839N – MARCH 2017 – REVISED JULY 2026 INPUT Input

Output OUTPUT

Time (200 µs/div) Time (1 µs/div)

C036 V+ = 2.75V C028

Figure 6-25. No Phase Reversal

Figure 6-26. Overload Recovery

Input Voltage (1 V/div)

Voltage (20 mV/div)

Output Input

Output

Time (0.1µs/div) Time (1 µs/div)

C031

Figure 6-27. Small-Signal Step Response

Figure 6-28. Large-Signal Step Response

6 60 Output Voltage (V)

Current Limit (mA)

80 40 20

Sinking 0

Sourcing ±20 5 4 3 2

10M C035

Figure 6-30. Maximum Output Voltage vs Frequency and Supply Voltage

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Channel Separation (dB)

140 EMIRR (dB)

100 80 60 40 20 ±40 ±60 ±80 ±100 ±120

Frequency (Hz)

V+ = 2.75V

Figure 6-31. Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency

1M 10M C038 V– = –2.75V 200 Open Loop Voltage Gain (dB) 75

60 45 30 15 160 120 80 40 0 0

0 10 20 30 40 50 60 70 80 90

Capacitive Load (pF)

0 100 0.5 1 1.5 2 2.5 3 3.5 4 4.5 Output Voltage (V) C037 5 5.5 C023

Figure 6-33. Phase Margin vs Capacitive Load Figure 6-34. Open Loop Voltage Gain vs Output Voltage

100 100

75 75

50 50

(mV) Voltage (mV)

100k

Figure 6-32. Channel Separation vs Frequency

90 25

0

Settling time (µs)

Settling time (µs) C032

Figure 6-35. Large Signal Settling Time (Positive)

20 10k Frequency (Hz)

Phase Margin (degrees)

1k C041 1.2 1.5 C033

Figure 6-36. Large Signal Settling Time (Negative)

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7 Detailed Description

7.1 Overview

The TLV906x devices are a family of low-power, rail-to-rail input and output op amps. These devices operate from 1.8V to 5.5V, are unity-gain stable, and are designed for a wide range of general-purpose applications. The input common-mode voltage range includes both rails and allows the TLV906x series to be used in virtually any single-supply application. Rail-to-rail input and output swing significantly increases dynamic range, especially in low-supply applications. The high bandwidth enables this family to drive the sample-hold circuitry of analog-todigital converters (ADCs).

7.2 Functional Block Diagram

V+ Reference Current V IN+ V IN– V BIAS1 Class AB

Control Circuitry V O V BIAS2 V– (Ground)

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7.3 Feature Description

7.3.1 Rail-to-Rail Input The input common-mode voltage range of the TLV906x family extends 100mV beyond the supply rails for the full supply voltage range of 1.8V to 5.5V. This performance is achieved with a complementary input stage: an N-channel input differential pair in parallel with a P-channel differential pair, as shown in the Functional Block Diagram. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1.4V to 200mV above the positive supply, whereas the P-channel pair is active for inputs from 200mV below the negative supply to approximately (V+) – 1.4V. There is a small transition region, typically (V+) – 1.2V to (V+) – 1V, in which both pairs are on. This 200mV transition region can vary up to 200mV with process variation. Thus, the transition region (with both stages on) can range from (V+) – 1.4V to (V+) – 1.2V on the low end, and up to (V+) – 1V to (V+) – 0.8V on the high end. Within this transition region, PSRR, CMRR, offset voltage, offset drift, and THD can degrade compared to device operation outside this region. 7.3.2 Rail-to-Rail Output Designed as a low-power, low-voltage operational amplifier, the TLV906x series delivers a robust output drive capability. A class AB output stage with common-source transistors achieves full rail-to-rail output swing capability. For resistive loads of 10kΩ, the output swings to within 15mV of either supply rail, regardless of the applied power-supply voltage. Different load conditions change the ability of the amplifier to swing close to the rails. 7.3.3 EMI Rejection The TLV906x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the TLV906x benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10MHz to 6GHz. Figure 7-1 shows the results of this testing on the TLV906x. Table 7-1 lists the EMIRR IN+ values for the TLV906x at particular frequencies commonly encountered in real-world applications. See EMI Rejection Ratio of Operational Amplifiers application note for more information.

140 120 EMIRR (dB)

100 80 60 40 20 0 10M 100M 1G

Frequency (Hz) C041 Figure 7-1. EMIRR Testing

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Table 7-1. TLV906x EMIRR IN+ For Frequencies of Interest (continued) FREQUENCY APPLICATION or ALLOCATION EMIRR IN+

3.6GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88.8dB 5GHz 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4GHz to 8GHz) 87.6dB 7.3.4 Overload Recovery Overload recovery is defined as the time required for the operational amplifier output to recover from a saturated state to a linear state. The output devices of the operational amplifier enter a saturation region when the output voltage exceeds the rated operating voltage, because of the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return to the linear state. After the charge carriers return to the linear state, the device begins to slew at the specified slew rate. Therefore, the propagation delay (in case of an overload condition) is the sum of the overload recovery time and the slew time. The overload recovery time for the TLV906x family is approximately 200ns. 7.3.5 Shutdown Function The TLV906xS devices feature SHDN pins that disable the op amp, placing the op amp into a low-power standby mode. In this mode, the op amp typically consumes less than 1µA. The SHDN pins are active-low, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic low. The SHDN pins are referenced to the negative supply voltage of the op amp. The threshold of the shutdown feature lies around 800mV (typical) and does not change with respect to the supply voltage. Hysteresis has been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage between V– and V– + 0.2V. A valid logic high is defined as a voltage between V– + 1.2V and V+. The shutdown pin must either be connected to a valid high or a low voltage or driven, and not left as an open circuit. There is no internal pull-up to enable the amplifier. The SHDN pins are high-impedance CMOS inputs. Dual op amp versions are independently controlled, and quad op amp versions are controlled in pairs with logic inputs. For battery-operated applications, this feature may be used to greatly reduce the average current and extend battery life. The enable time is 10µs for full shutdown of all channels; disable time is 6µs. When disabled, the output assumes a high-impedance state. This architecture allows the TLV906xS to operate as a gated amplifier (or to have the device output multiplexed onto a common analog output bus). Shutdown time (t OFF ) depends on loading conditions and increases as load resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10kΩ load to midsupply (V S / 2) is required. If using the TLV906xS without a load, the resulting turnoff time is significantly increased.

7.4 Device Functional Modes

The TLV906x family are operational when the power-supply voltage is between 1.8V (±0.9V) and 5.5V (±2.75V). The TLV906xS devices feature a shutdown mode and are shut down when a valid logic low is applied to the shutdown pin.

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8 Application and Implementation

Note Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The TLV906x family features 10MHz bandwidth and 6.5V/µs slew rate with only 538µA of supply current per channel, providing good AC-performance at very low power consumption. DC applications are well served with a very low input noise voltage of 10nV/√ Hz at 10kHz, low input bias current, and a typical input offset voltage of 0.3mV.

8.2 Typical Applications

8.2.1 Typical Low-Side Current Sense Application Figure 8-1 shows the TLV906x configured in a low-side current-sensing application.

V BUS I LOAD Z LOAD V SHUNT R shunt 0.1 5V + V OUT TLV906x R F 165 k R G 3.4 k Figure 8-1. TLV906x in a Low-Side, Current-Sensing Application

8.2.2 Design Requirements The design requirements for this design are: • • • 24 Load current: 0A to 1A Output voltage: 4.95V Maximum shunt voltage: 100mV Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

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8.2.3 Detailed Design Procedure The transfer function of the circuit in Figure 8-1 is given in Equation 1.

V OUT = I LOAD × R SHUNT × GAIN (1) The load current (I LOAD ) produces a voltage drop across the shunt resistor (R SHUNT ). The load current is set from 0A to 1A. To keep the shunt voltage below 100mV at maximum load current, the largest shunt resistor is defined using Equation 2.

TLV906x to produce an output voltage of approximately 0V to 4.95V. Equation 3 calculates the gain required for the TLV906x to produce the required output voltage.

the R F and R G , resistors to set the gain of the TLV906x to 49.5V/V.

Figure 8-2 shows the measured transfer function of the circuit shown in Figure 8-1. Notice that the gain is only a function of the feedback and gain resistors. This gain is adjusted by varying the ratio of the resistors and the actual resistor values are determined by the impedance levels that the designer wants to establish. The impedance level determines the current drain, the effect that stray capacitance has, and a few other behaviors. There is no optimal impedance selection that works for every system, you must choose an impedance that is ideal for your system parameters. 8.2.4 Application Curve 5 Output (V)

4 3 2 1 0

0 0.2 0.4 0.6 0.8

I LOAD (A)

1 C219 Figure 8-2. Low-Side, Current-Sense, Transfer Function

8.3 Power Supply Recommendations

The TLV906x series is specified for operation from 1.8V to 5.5V (±0.9V to ±2.75V); many specifications apply from –40°C to 125°C. The Typical Characteristics section presents parameters that can exhibit significant variance with regard to operating voltage or temperature.

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TLV9061, TLV9062, TLV9064 www.ti.com SBOS839N – MARCH 2017 – REVISED JULY 2026 CAUTION Supply voltages larger than 6V can permanently damage the device; see the Absolute Maximum Ratings table.

Place 0.1µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout section. 8.3.1 Input and ESD Protection The TLV906x series incorporates internal ESD protection circuits on all pins. For input and output pins, this protection primarily consists of current-steering diodes connected between the input and power-supply pins. These ESD protection diodes provide in-circuit, input overdrive protection, as long as the current is limited to 10mA, as shown in the Absolute Maximum Ratings table. Figure 8-3 shows how a series input resistor can be added to the driven input to limit the input current. The added resistor contributes thermal noise at the amplifier input and the value must be kept to a minimum in noise-sensitive applications.

V+ I OVERLOAD 10-mA maximum

Device V OUT V IN

5 kW Figure 8-3. Input Current Protection 26 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

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8.4 Layout

8.4.1 Layout Guidelines For best operational performance of the device, use good printed circuit board (PCB) layout practices, including: • • • •

•

•

• • Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of the op amp itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry. – Connect low-ESR, 0.1µF ceramic bypass capacitors between each supply pin and ground, placed as

close to the device as possible. A single bypass capacitor from V+ to ground is adequate for single-supply applications. Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup. Take care to physically separate digital and analog grounds, paying attention to the flow of the ground current. For more detailed information, see Circuit Board Layout Techniques. To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace at a 90 degree angle is much better as opposed to running the traces in parallel with the noisy trace. Place the external components as close to the device as possible. As illustrated in Figure 8-5, keeping R F and R G close to the inverting input minimizes parasitic capacitance on the inverting input. Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials. Cleaning the PCB following board assembly is recommended for best performance. Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.

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8.4.2 Layout Example + VIN 1 + VIN 2

VOUT 1 R G VOUT 2 R G R F R F Figure 8-4. Schematic Representation for the Layout Example Place components close to device and to each other to reduce

parasitic errors .

OUT 1

V S+ OUT1 Use low-ESR, ceramic bypass capacitor . Place as close to the device

as possible .

GND V+ R F OUT 2

R G V ± Use low-ESR, ceramic bypass capacitor . Place as close to the device

as possible .

GND

V S± IN2 + Ground (GND) plane on another layer VIN 2 Keep input traces short and run the input traces

as far away from the supply lines as possible .

Figure 8-5. Layout Example 28 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

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9 Device and Documentation Support

9.1 Documentation Support

9.1.1 Related Documentation For related documentation, see the following: • • • • • •

• Texas Instruments, Circuit Board Layout Techniques Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application note Texas Instruments, QFN/SON PCB Attachment application note Texas Instruments, Quad Flatpack No-Lead Logic Packages application note Texas Instruments, Single-Ended Input to Differential Output Conversion Circuit design guide Texas Instruments, TLVx313 Low-Power, Rail-to-Rail In/Out, 500-μV Typical Offset, 1MHz Operational Amplifier for Cost-Sensitive Systems data sheet Texas Instruments, TLVx314 3MHz, Low-Power, Internal EMI Filter, RRIO, Operational Amplifier data sheet

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E ™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

TI E2E ™ is a trademark of Texas Instruments. Bluetooth ® is a registered trademark of Bluetooth SIG, Inc. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision M (December 2024) to Revision N (July 2026) Page • Changed the packaged dimensions of TLV9062S (YCK, DSBGA) to match package outline diagram ............ 1 Changes from Revision L (September 2024) to Revision M (December 2024) Page • Changed TLV9061S DBV (SOT-23) pinout drawing to match the Pin Functions table...................................... 5 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

Product Folder Links: TLV9061 TLV9062 TLV9064 29 TLV9061, TLV9062, TLV9064 www.ti.com SBOS839N – MARCH 2017 – REVISED JULY 2026

Changes from Revision K (July 2024) to Revision L (September 2024) Page • Deleted package preview note from TLV9062S (YCK, DSBGA) package in Device Information table .............1 Changes from Revision J (September 2019) to Revision K (July 2024) Page • Updated the numbering format for tables, figures, and cross-references throughout the document................. 1 • Updated the Device Information table................................................................................................................ 1 • Added package preview note for TLV9062S (YCK, DSBGA) package in Device Information table ..................1 • Added YCK packages to the Device Comparison table..................................................................................... 4 • Added TLV9062S YCK (DSBGA) pinout drawing to Pin Configuration and Functions section.......................... 5 Changes from Revision I (May 2019) to Revision J (September 2019) Page • Deleted TLV9062IDDFR (SOT-23, 8) package preview notations throughout data sheet................................. 1 • Added industry standard package names to Device Comparison Table ........................................................... 4 • Added note to packages with thermal pads, specifying that the thermal pads need to be connected to V–......5 • Added link to Shutdown Function section in SHDN pin function rows................................................................5 • Added EMI Rejection section to the Feature Description section.....................................................................22 • Changed Shutdown Function section to add more clarification .......................................................................23 Changes from Revision H (April 2019) to Revision I (May 2019) Page • Added DDF (SOT-23) thermal information to replace TBDs.............................................................................11 Changes from Revision G (December 2018) to Revision H (April 2019) Page • Added (SOT-23, 8) information to Device Information .......................................................................................1 • Added DDF package column to Device Comparison Table .............................................................................. 4 • Added DDF (SOT-23) package, to Pin Functions ..............................................................................................5 • Added DDF (SOT-23) package to Thermal Information .................................................................................. 11 Changes from Revision F (September 2018) to Revision G (December 2018) Page • Changed TLV9064 RUC package name from: (WQFN, 14) to: (X2QFN, 14) in Device Information table.........1 • Added RUC (X2QFN) package, pinout information to Pin Functions: TLV9064 table........................................5 • Added TLV9064 RUC (X2QFN) pinout drawing to Pin Configuration and Functions section.............................5 • Added RUC (X2QFN) to Thermal Information: TLV9064 table.........................................................................12 Changes from Revision E (July 2018) to Revision F (September 2018) Page • Deleted Shutdown part numbers from data sheet header .................................................................................1 • Deleted (X2QFN, 10) package from TLV9062 Device Information table............................................................1 • Added references to shutdown part numbers in Description section ................................................................ 1 • Changed TLV906xS series to TLV906xS family throughout data sheet............................................................. 1 • Added Shutdown devices to Device Comparison Table .................................................................................... 4 • Changed pin namings for all pinout drawings to reflect updated nomenclature ................................................ 5 • Added TLV9061S Thermal Information Table................................................................................................... 11 • Added TLV9064S Thermal Information Table...................................................................................................12 • Deleted Partial Shutdown Amplifier Enable Time............................................................................................. 13 30 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

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•

• SBOS839N – MARCH 2017 – REVISED JULY 2026

Added clarification on selecting resistors for a current sensing application in the Typical Applications Section .............................................................................................................................................................25 Changed wording of third bullet in Layout Guidelines...................................................................................... 27 Changes from Revision D (June 2018) to Revision E (July 2018) Page • Added TLV9061S device to Device Information table........................................................................................ 1 • Added TLV9064S device to Device Information table........................................................................................ 1 • Added RUC and RUG packages to the Device Comparison table.....................................................................4 • Added TLV9061S DBV (SOT-23) pinout drawing to Pin Configuration and Functions section.......................... 5 • Added TLV9061S DBV (SOT-23) package, pinout information to Pin Functions: TLV9061S table....................5 • Added TLV9062S RUG (VSSOP) package, pinout drawing to Pin Configuration and Functions section.......... 5 • Added TLV9064 RTE pinout information to Pin Functions: TLV9064 table........................................................ 5 • Added TLV9064S RTE (WQFN) pinout drawing to Pin Configuration and Functions section ...........................5 • Added TLV9062S RUG (VSSOP) package, pinout information to Pin Functions: TLV9062S table................... 5 • Added TLV9064 RTE (WQFN) pinout drawing to Pin Configuration and Functions section ............................. 5 Changes from Revision C (March 2018) to Revision D (June 2018) Page • Added shutdown suffix to "TLV906x" to document title...................................................................................... 1 • Added "Shutdown Version" bullet to Features list ............................................................................................. 1 • Added TLV9062S device to Device Information table........................................................................................ 1 • Added shutdown text to Description (continued) section....................................................................................1 • Added "(V S = [V+] – [V–]) supply voltage parameter in Absolute Maximum Ratings table.............................. 10 • Added "input voltage range" and "output voltage range" parameters and values to Recommended Operating

Conditions table................................................................................................................................................10 • Added shutdown pin recommended operating conditions in Recommended Operating Conditions table....... 10 • Added "T A " symbol to "specified temperature" parameter to Recommended Operating Conditions table ......10 • Added Thermal Information: TLV9062S thermal table data............................................................................. 12 • Added shutdown section to Electrical Characteristics: V S (Total Supply Voltage) = (V+) – (V–) = 1.8V to 5.5V

table.................................................................................................................................................................. 13 • Added Shutdown Function section .................................................................................................................. 23 Changes from Revision B (October 2017) to Revision C (March 2018) Page • Changed device status from Production Data/Mixed Status to Production Data .............................................. 1 • Deleted package preview note from TLV9061 (DPW, X2SON) package in Device Information table ...............1 • Deleted package, preview note from TLV9061 DPW (X2SON) package, pinout drawing .................................5 • Changed formatting of ESD Ratings table to show different results for all packages ..................................... 10 • Deleted package preview note from DPW (X2SON) package in Thermal Information: TLV9061 table .......... 11 • Deleted package preview note from DPW (X2SON) package in Thermal Information: TLV9061 table .......... 11 Changes from Revision A (June 2017) to Revision B (October 2017) Page • Added 8-pin PW package, to Pin Configuration and Functions section ............................................................ 5 • Added DSG (WSON) package to Thermal Information table........................................................................... 11 • Added PW (TSSOP) to TLV9062 Thermal Information table ...........................................................................11 • Changed maximum input offset voltage value from ±1.6mV to 2mV................................................................13 • Changed maximum input offset voltage value from ±1.5 to ±1.6mV................................................................ 13 • Changed minimum common-mode rejection ratio input voltage range from 86dB to 80dB ............................ 13 • Changed typical input current noise density value from 10 to 23fA/√ Hz ........................................................ 13 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated

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• • • • Changed THD + N test conditions from V S = 5V to V S = 5.5V......................................................................... 13 Added V CM = 2.5V test condition to THD + N parameter in Electrical Characteristics table ........................... 13 Added maximum output voltage swing value from 25mV to 60mV.................................................................. 13 Changed maximum output voltage swing value from 15mV to 20mV ............................................................. 13 Changes from Revision * (March 2017) to Revision A (June 2017) Page • Changed device status from Advance Information to Production Data ............................................................. 1

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and without revision of this document. For browser-based versions of this data sheet, see the left-hand navigation pane.

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PACKAGE OUTLINE

YCK0009-C01 DSBGA - 0.33 mm max height SCALE 12.000

DIE SIZE BALL GRID ARRAY B A E BALL A1 CORNER

D0.33 MAX

CSEATING PLANE BALL TYP 0.125 0.075 0.05 C 0.7 TYP

SYMM C

D: Max = 1.01 mm, Min = 0.97 mm

SYMM 0.7 TYP E: Max = 1.01 mm, Min = 0.97 mm

B0.35 TYP A 1 9X

0.015 0.195 0.155 C A B 2 3 0.35 TYP 4226891/A 06/2021

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

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EXAMPLE BOARD LAYOUT

YCK0009-C01 DSBGA - 0.33 mm max height

DIE SIZE BALL GRID ARRAY (0.35) TYP 9X ( 0.18)

1 2 3 A (0.35) TYP

SYMM

BC SYMM LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 50X 0.0375 MAX 0.0375 MIN METAL UNDER

SOLDER MASK EXPOSED

METAL ( 0.18) SOLDER MASK OPENING ( 0.18) METAL SOLDER MASK

OPENING EXPOSED METAL SOLDER MASK

DEFINED (PREFERRED)

NON-SOLDER MASK

DEFINED SOLDER MASK DETAILS

NOT TO SCALE 4226891/A 06/2021

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

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EXAMPLE STENCIL DESIGN

YCK0009-C01 DSBGA - 0.33 mm max height

DIE SIZE BALL GRID ARRAY (0.35) TYP (R0.05) TYP 9X ( 0.21)

1 2 3 A (0.35) TYP

SYMM

BC METAL

TYP SYMM SOLDER PASTE EXAMPLE BASED ON 0.075 mm THICK STENCIL

SCALE: 50X 4226891/A 06/2021 NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

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PACKAGE OPTION ADDENDUM

www.ti.com 20-Aug-2026

PACKAGING INFORMATION

Orderable part number Status Material type

(1) (2)

Package | Pins Package qty | Carrier RoHS

(3)

Lead finish/ Ball material MSL rating/ Peak reflow

(4) (5)

Op temp (°C) Part marking

PACKAGE OPTION ADDENDUM

www.ti.com Orderable part number (1)

20-Aug-2026 Status Material type

(1) (2)

Package | Pins Package qty | Carrier RoHS

(3)

Lead finish/ Ball material MSL rating/ Peak reflow

(4) (5)

Op temp (°C) Part marking

(6)

(2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com (3)

20-Aug-2026 RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width.

(5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLV9061, TLV9062, TLV9064 : • Automotive : TLV9061-Q1, TLV9062-Q1, TLV9064-Q1 NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jun-2026

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1 B0 W Reel Diameter

Cavity

A0 B0 K0 W P1 A0

Dimension designed to accommodate the component width Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants *All dimensions are nominal

Device Package Package Pins

Type Drawing SPQ Reel Reel A0

Diameter Width (mm)

(mm) W1 (mm)

B0 (mm)

K0 (mm)

P1 (mm)

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jun-2026 Device Package Package Pins

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jun-2026 TAPE AND REEL BOX DIMENSIONS Width (mm)

W L H *All dimensions are nominal

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jun-2026 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLV9062SIDGSR VSSOP DGS 10 2500 366.0 364.0 50.0 TLV9062SIRUGR X2QFN RUG 10 3000 205.0 200.0 33.0 TLV9062SIYCKR DSBGA YCK 9 3000 182.0 182.0 20.0

TLV9064IDR SOIC D 14 2500 353.0 353.0 32.0 TLV9064IPWR TSSOP PW 14 2000 353.0 353.0 32.0 TLV9064IPWR TSSOP PW 14 2000 356.0 356.0 35.0 TLV9064IPWT TSSOP PW 14 250 353.0 353.0 32.0 TLV9064IRTER WQFN RTE 16 3000 367.0 367.0 35.0 TLV9064IRUCR QFN RUC 14 3000 205.0 200.0 30.0 TLV9064IRUCRG4 QFN RUC 14 3000 205.0 200.0 30.0 TLV9064SIRTER WQFN RTE 16 3000 367.0 367.0 35.0 Pack Materials-Page 4

PACKAGE OUTLINE

DBV0005A SOT-23 - 1.45 mm max height

SCALE 4.000

SMALL OUTLINE TRANSISTOR C 3.0 2.6

1.75 1.45 PIN 1 INDEX AREA 1 A 5 (0.1) 2X 0.95 1.9 0.1 C B 3.05 2.75 1.9 2

(0.15)

4 0.5 5X

0.3 0.2 3 C A B NOTE 5 4X 0 -15 (1.1) 0.15 TYP 0.00

1.45 0.90 4X 4 -15 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214839/K 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178.

4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.25 mm per side.

5. Support pin may differ or may not be present.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0005A SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR PKG 5X (1.1)

1

5 5X (0.6)

SYMM

(1.9) 2

2X (0.95)

3 4 (R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK

DEFINED (PREFERRED)

SOLDER MASK

DEFINED SOLDER MASK DETAILS 4214839/K 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0005A SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR PKG

5X (1.1)

1

5 5X (0.6)

SYMM (1.9) 2

2X(0.95)

4 3 (R0.05) TYP (2.6)

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL

SCALE:15X 4214839/K 08/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DCK0005A SOT - 1.1 max height

SCALE 5.600

SMALL OUTLINE TRANSISTOR C

2.4 1.8

1.4 1.1 PIN 1 INDEX AREA B 1.1 MAX A 5 1 NOTE 4 2X 0.65 1.3 0.1 C (0.15) 2 1.3 2.15 1.85

(0.1)

0.33 0.15 C A B 4 3 5X

0.1 4X 0 -12

NOTE 5 (0.9) 0.1 TYP 0.0 4X 4 -15 0.15

0.22 TYP 0.08 GAGE PLANE 8 TYP 0 0.46 TYP 0.26 SEATING PLANE 4214834/G 11/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-203. 4. Support pin may differ or may not be present. 5. Lead width does not comply with JEDEC.

6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed

0.25mm per side www.ti.com

EXAMPLE BOARD LAYOUT

DCK0005A SOT - 1.1 max height

SMALL OUTLINE TRANSISTOR 5X (0.95) PKG

1 5 5X (0.4)

SYMM (1.3) 2 2X (0.65)

3 4 (R0.05) TYP (2.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X SOLDER MASK OPENING METAL EXPOSED METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK

DEFINED (PREFERRED)

SOLDER MASK

DEFINED SOLDER MASK DETAILS 4214834/G 11/2024

NOTES: (continued)

7. Publication IPC-7351 may have alternate designs.

8. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DCK0005A SOT - 1.1 max height

SMALL OUTLINE TRANSISTOR PKG 5X (0.95)

1

5 5X (0.4)

SYMM

(1.3) 2 2X(0.65)

4 3 (R0.05) TYP (2.2)

SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL

SCALE:18X 4214834/G 11/2024

NOTES: (continued)

9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

10. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DBV0006A SOT-23 - 1.45 mm max height

SCALE 4.000

SMALL OUTLINE TRANSISTOR C 3.0 2.6

1.75 1.45 PIN 1 INDEX AREA 1 B 6 2X 0.95 1.9 0.1 C A 3.05 2.75 5 2 4 6X

0.2 0.50 0.25 C A B 3 4X 0 -15 (1.1)

0.15 TYP 0.00 1.45 0.90 4X 4 -15 0.25 GAGE PLANE 8 TYP 0 0.22 TYP 0.08 0.6 TYP 0.3 SEATING PLANE 4214840/G 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.

4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation. 5. Refernce JEDEC MO-178.

www.ti.com

EXAMPLE BOARD LAYOUT

DBV0006A SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR PKG 6X (1.1)

1 6X (0.6)

6 SYMM

2 5 3 4 2X (0.95)

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK EXPOSED METAL EXPOSED METAL 0.07 MIN ARROUND 0.07 MAX ARROUND NON SOLDER MASK

DEFINED (PREFERRED)

SOLDER MASK

DEFINED SOLDER MASK DETAILS 4214840/G 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DBV0006A SOT-23 - 1.45 mm max height

SMALL OUTLINE TRANSISTOR PKG

6X (1.1)

1 6X (0.6)

6 SYMM

2 5 3 4 2X(0.95)

(R0.05) TYP (2.6)

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL

SCALE:15X 4214840/G 08/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DGK0008A VSSOP - 1.1 mm max height

SCALE 4.000

SMALL OUTLINE PACKAGE C 5.05 TYP 4.75 A

0.1 C PIN 1 INDEX AREA SEATING

PLANE 6X 0.65 8 1 2X 3.1 2.9 NOTE 3 1.95 4

5

8X

B 3.1 2.9

NOTE 4 0.38 0.25 0.13 C A B 0.23 0.13 SEE DETAIL A

0.25 GAGE PLANE 1.1 MAX 0 -8 0.15 0.05 0.7 0.4

DETAIL A A 20 TYPICAL 4214862/A 04/2023 PowerPAD is a trademark of Texas Instruments. NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187.

www.ti.com

EXAMPLE BOARD LAYOUT

TM DGK0008A VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE SYMM 8X (1.4)

8X (0.45)

(R0.05) TYP 1 8 SYMM 6X (0.65)

5 4 SEE DETAILS (4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X SOLDER MASK

OPENING METAL UNDER SOLDER MASK METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX ALL AROUND

NON-SOLDER MASK

DEFINED (PREFERRED)

0.05 MIN ALL AROUND SOLDER MASK

DEFINED SOLDER MASK DETAILS 15.000 4214862/A 04/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

9. Size of metal pad may vary due to creepage requirement.

www.ti.com

EXAMPLE STENCIL DESIGN

TM DGK0008A VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE SYMM (R0.05) TYP 8X (1.4)

8X (0.45) 1 8 SYMM 6X (0.65)

5 4 (4.4)

SOLDER PASTE EXAMPLE

SCALE: 15X 4214862/A 04/2023

NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

12. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DGS0010A VSSOP - 1.1 mm max height SCALE 3.200

SMALL OUTLINE PACKAGE C 5.05 TYP 4.75 SEATING PLANE

PIN 1 ID AREA A 0.1 C 10 1 3.1 2.9 NOTE 3 8X 0.5 2X 2 5

6 B 10X 3.1 2.9 NOTE 4 SEE DETAIL A 0.27 0.17 0.1 C A 1.1 MAX B 0.23 TYP 0.13 0.25 GAGE PLANE 0 - 8 0.15 0.05 0.7 0.4

DETAIL A TYPICAL 4221984/A 05/2015 NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-187, variation BA.

www.ti.com

EXAMPLE BOARD LAYOUT

DGS0010A VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE 10X (0.3)

10X (1.45)

(R 0.05 ) TYP SYMM 1

10

SYMM 8X (0.5) 6 5 (4.4)

LAND PATTERN EXAMPLE

SCALE:10X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND

SOLDER MASK

DEFINED NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE 4221984/A 05/2015 NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DGS0010A VSSOP - 1.1 mm max height

SMALL OUTLINE PACKAGE 10X (1.45) 10X (0.3) SYMM

1 (R 0.05 ) TYP 10

SYMM 8X (0.5)

6 5 (4.4)

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL

SCALE:10X 4221984/A 05/2015 NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

D0014A SOIC - 1.75 mm max height

SCALE 1.800

SMALL OUTLINE INTEGRATED CIRCUIT C

6.2 TYP 5.8 SEATING PLANE

PIN 1 ID AREA A 0.1 C 12X 1.27 14 1 2X 7.62 8.75 8.55 NOTE 3 7

8

B 4.0 3.8

NOTE 4 SEE DETAIL A 14X 0.51 0.31

0.25 C A B 1.75 MAX 0.25 TYP 0.13

0.25 GAGE PLANE 0 - 8 0.25 0.10 1.27 0.40

DETAIL A TYPICAL 4220718/A 09/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.

5. Reference JEDEC registration MS-012, variation AB.

www.ti.com

EXAMPLE BOARD LAYOUT

D0014A SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT 14X (1.55) SYMM

1

14 14X (0.6)

12X (1.27)

SYMM 8 7

(R0.05) TYP

(5.4)

LAND PATTERN EXAMPLE

SCALE:8X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND SOLDER MASK

DEFINED NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS 4220718/A 09/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0014A SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT 14X (1.55) SYMM

1

14 14X (0.6)

12X (1.27) SYMM 7 8 (5.4)

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL

SCALE:8X 4220718/A 09/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

GENERIC PACKAGE VIEW

DSG 8 WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD 2 x 2, 0.5 mm pitch This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224783/A www.ti.com

PACKAGE OUTLINE

DSG0008A WSON - 0.8 mm max height

SCALE 5.500

PLASTIC SMALL OUTLINE - NO LEAD 2.1 1.9 A B 0.32 0.18 PIN 1 INDEX AREA

2.1 1.9 0.4 0.2

ALTERNATIVE TERMINAL SHAPE

TYPICAL 0.8 0.7 C

SEATING PLANE

0.05 0.00 0.08 C EXPOSED THERMAL PAD SIDE WALL METAL THICKNESS

DIM A OPTION 2 OPTION 1

0.1 0.2 (DIM A) TYP 0.9 0.1 5 4 6X 0.5 2X 1.5 9 8 1

PIN 1 ID (45 X 0.25)

1.6 0.1 8X 0.4 8X

0.2 0.32 0.18 0.1 0.05 C A B C 4218900/E 08/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

DSG0008A WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD (0.9) 8X (0.5) ( 0.2) VIA

TYP 1 8 8X (0.25)

(0.55) SYMM 9

(1.6)

6X (0.5)

5 4

SYMM (R0.05) TYP (1.9)

LAND PATTERN EXAMPLE

SCALE:20X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND SOLDER MASK OPENING METAL METAL UNDER

SOLDER MASK NON SOLDER MASK

DEFINED (PREFERRED)

SOLDER MASK OPENING

SOLDER MASK

DEFINED

SOLDER MASK DETAILS 4218900/E 08/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

DSG0008A WSON - 0.8 mm max height

PLASTIC SMALL OUTLINE - NO LEAD 8X (0.5) SYMM METAL

1

8 8X (0.25)

(0.45) SYMM

9 (0.7) 6X (0.5)

5 4

(R0.05) TYP (0.9)

(1.9)

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 9: 87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X 4218900/E 08/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

PW0014A TSSOP - 1.2 mm max height

SCALE 2.500

SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A

0.1 C PIN 1 INDEX AREA

12X 0.65 14 1 2X 5.1 4.9 NOTE 3 3.9 4X (0 -12 )

7

8

14X B 4.5 4.3

NOTE 4 0.30 0.17 0.1 C A B 1.2 MAX (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE

0.15 0.05 0 -8 0.75 0.50

DETAIL A A 20 TYPICAL 4220202/B 12/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0014A TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE SYMM 14X (1.5)

(R0.05) TYP 1 14 14X (0.45)

SYMM 12X (0.65)

8 7 (5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X SOLDER MASK

OPENING METAL UNDER SOLDER MASK METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX ALL AROUND NON-SOLDER MASK

DEFINED (PREFERRED)

0.05 MIN ALL AROUND SOLDER MASK

DEFINED SOLDER MASK DETAILS 15.000 4220202/B 12/2023

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0014A TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE 14X (1.5) SYMM (R0.05) TYP 1 14X (0.45) 14 SYMM 12X (0.65)

8 7 (5.8)

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL

SCALE: 10X 4220202/B 12/2023

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

PW0008A TSSOP - 1.2 mm max height SCALE 2.800

SMALL OUTLINE PACKAGE C 6.6 TYP 6.2 SEATING PLANE

PIN 1 ID AREA A 0.1 C

6X 0.65 8 1

3.1 2.9 NOTE 3 2X 1.95 4

5

B 4.5 4.3

NOTE 4 SEE DETAIL A 8X 0.30 0.19

0.1 C A 1.2 MAX B (0.15) TYP 0.25 GAGE PLANE 0 - 8 0.15 0.05 0.75 0.50

DETAIL A TYPICAL 4221848/A 02/2015 NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

PW0008A TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM

1

8 (R 0.05 ) TYP SYMM 6X (0.65)

5 4 (5.8)

LAND PATTERN EXAMPLE

SCALE:10X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND

SOLDER MASK

DEFINED NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE 4221848/A 02/2015 NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0008A TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R 0.05 ) TYP

1

8

SYMM 6X (0.65)

5 4

(5.8)

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL

SCALE:10X 4221848/A 02/2015 NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

DDF0008A SOT-23-THIN - 1.1 mm max height

SCALE 4.000

PLASTIC SMALL OUTLINE C

2.95 TYP 2.65 SEATING PLANE PIN 1 ID AREA A 0.1 C 6X 0.65 8 1 2.95 2.85 NOTE 3 2X 1.95 4X 0 -15 4

5 0.38

0.22 0.1 C A B 8X B 1.65 1.55 1.1

MAX 4X 4 -15 0.20 TYP 0.08 SEE DETAIL A 0.25 GAGE PLANE 0 - 8 0.1 0.0 0.6 0.3

DETAIL A TYPICAL 4222047/E 07/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

www.ti.com

EXAMPLE BOARD LAYOUT

DDF0008A SOT-23-THIN - 1.1 mm max height

PLASTIC SMALL OUTLINE 8X (1.05) SYMM

1

8 8X (0.45)

SYMM 6X (0.65)

5 4 (R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:15X SOLDER MASK OPENING 0.05 MAX ALL AROUND METAL EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING 0.05 MIN ALL AROUND EXPOSED METAL SOLDER MASK

DEFINED NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS 4222047/E 07/2024

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

DDF0008A SOT-23-THIN - 1.1 mm max height

PLASTIC SMALL OUTLINE 8X (1.05) SYMM

(R0.05) TYP 1

8 8X (0.45)

SYMM 6X (0.65)

5 4 (2.6)

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL

SCALE:15X 4222047/E 07/2024

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

7. Board assembly site may have different recommendations for stencil design.

www.ti.com

GENERIC PACKAGE VIEW

RTE 16 WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD 3 x 3, 0.5 mm pitch This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4225944/A www.ti.com

PACKAGE OUTLINE

RTE0016C WQFN - 0.8 mm max height

SCALE 3.600

PLASTIC QUAD FLATPACK - NO LEAD 3.1 2.9 A B PIN 1 INDEX AREA

3.1 2.9 SIDE WALL METAL THICKNESS

DIM A OPTION 1 OPTION 2

0.1 0.2 C 0.8 MAX

SEATING PLANE

0.05 0.00 0.08 1.68 0.07 (DIM A) TYP 5 8

EXPOSED THERMAL PAD 12X 0.5

4

9 4X 1.5 SYMM 17 1 12

16X

PIN 1 ID (OPTIONAL)

16 13 0.1

0.05 SYMM 16X 0.30 0.18

C A B 0.5 0.3 4219117/B 04/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RTE0016C WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD ( 1.68)

SYMM 13 16 16X (0.6)

1

12 16X (0.24)

SYMM 17

(2.8) (0.58) TYP 12X (0.5)

9 4 ( 0.2) TYP

VIA 5 (R0.05) ALL PAD CORNERS 8 (0.58) TYP

(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:20X 0.07 MIN ALL AROUND 0.07 MAX ALL AROUND

SOLDER MASK DETAILS

4219117/B 04/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RTE0016C WQFN - 0.8 mm max height

PLASTIC QUAD FLATPACK - NO LEAD ( 1.55) 16 13 16X (0.6)

1

12 16X (0.24)

17 SYMM

(2.8)

12X (0.5)

9 4 METAL ALL AROUND 5

SYMM 8

(R0.05) TYP (2.8)

SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17: 85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:25X 4219117/B 04/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

GENERIC PACKAGE VIEW

RUC 14 X2QFN - 0.4 mm max height

PLASTIC QUAD FLATPACK - NO LEAD 2 x 2, 0.4 mm pitch This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4229871/A www.ti.com

PACKAGE OUTLINE

X2QFN - 0.4 mm max height RUC0014A

PLASTIC QUAD FLAT PACK- NO LEAD A 2.1 1.9 B 2.1 1.9 PIN 1 INDEX AREA 0.4 MAX

CSEATING PLANE 0.08 C 0.05 0.00 (0.15) TYP 2X 0.4 7 6 8X 0.4

5 8 SYMM 1.6 12 1

14 PIN 1 ID (45 o X0.1)

13 SYMM 14X 0.25 0.15 14X 0.5 0.3 0.1

0.05 C A B C

4220584/A 05/2019 NOTES:

All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

X2QFN - 0.4 mm max height RUC0014A

PLASTIC QUAD FLAT PACK- NO LEAD SYMM 14X (0.6) 14X (0.2)

8X (0.4) SYMM

(1.6) (1.8)

(R0.05)

2X (0.4)

(1.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 23X 0.05 MAX ALL AROUND EXPOSED METAL 0.05 MIN ALL AROUND METAL SOLDER MASK OPENING EXPOSED METAL NON-SOLDER MASK

DEFINED (PREFERRED)

SOLDER MASK OPENING METAL UNDER SOLDER MASK

SOLDER MASK

DEFINED SOLDER MASK DETAILS 4220584/A 05/2019

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .

www.ti.com

EXAMPLE STENCIL DESIGN

X2QFN - 0.4 mm max height RUC0014A

PLASTIC QUAD FLAT PACK- NO LEAD SYMM 14X (0.6) 14X (0.2)

8X (0.4) SYMM

(1.6) (1.8)

(R0.05)

2X (0.4)

(1.8)

SOLDER PASTE EXAMPLE BASED ON 0.100mm THICK STENCIL

SCALE: 23X 4220584/A 05/2019

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

GENERIC PACKAGE VIEW

RUG 10 X2QFN - 0.4 mm max height

PLASTIC QUAD FLATPACK - NO LEAD 1.5 x 2, 0.5 mm pitch This image is a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4231768/A www.ti.com

PACKAGE OUTLINE

RUG0010A X2QFN - 0.4 mm max height

SCALE 7.500

PLASTIC QUAD FLATPACK - NO LEAD 1.55 1.45 B A PIN 1 INDEX AREA 2.05 1.95 0.1 MIN SIDE WALL WETTABLE FLANK

OPTIONAL: SIDE WALL PIN DETAIL NOTE 3 40.000 0.40 0.34 C SEATING PLANE

0.05 0.00

2X

0.1 0.05 0.05 C 0.35 0.25 C A B C SYMM (0.127) TYP 5 4 6 4X 0.3 0.2

0.1 0.05 C A B C SYMM 2X 1.5 4X 6X 0.5 9 1 0.45 2X

0.35 0.25 0.15 0.1 0.05 C A B C 10 PIN 1 ID (45 X 0.1) 8X 0.4 0.3 4231745/B 03/2026

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. Minimum 0.1 mm solder wetting on pin side wall. Available for wettable flank version only.

www.ti.com

EXAMPLE BOARD LAYOUT

RUG0010A X2QFN - 0.4 mm max height

PLASTIC QUAD FLATPACK - NO LEAD 2X (0.3)

SYMM 10 SEE SOLDER MASK DETAIL 8X (0.55) 4X (0.25)

1 9 4X (0.2)

SYMM 6X (0.5) (1.8)

(R0.05) TYP 4 6 2X (0.6)

5 (1.35)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 35X 0.05 MIN ALL AROUND 0.05 MAX ALL AROUND

METAL UNDER SOLDER MASK METAL EDGE EXPOSED METAL SOLDER MASK

OPENING EXPOSED

METAL NON SOLDER MASK

DEFINED (PREFERRED)

SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4231745/B 03/2026

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

RUG0010A X2QFN - 0.4 mm max height

PLASTIC QUAD FLATPACK - NO LEAD 2X (0.3)

SYMM 10

8X (0.55) 4X (0.25)

1 9 4X (0.2)

SYMM 6X (0.5) (1.8)

(R0.05) TYP 4 6 2X (0.6)

5

(1.35)

SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL

SCALE: 35X 4231745/B 03/2026

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

DPW0005A X2SON - 0.4 mm max height

SCALE 12.000

PLASTIC SMALL OUTLINE - NO LEAD 0.85 0.75 B

A0.85 0.75 PIN 1 INDEX AREA 0.4 MAX C SEATING PLANE

NOTE 3 (0.1)

0.05 0.00 (0.324) 4X (0.05)

0.25 0.1 2

4

2X 0.48 3 NOTE 3

2X (0.26)

5 1 4X 0.239 0.139

3X 0.288 0.188 0.27 0.17 0.1 0.05 C A B C 4223102/D 03/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice. 3. The size and shape of this feature may vary.

www.ti.com

EXAMPLE BOARD LAYOUT

DPW0005A X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD (0.78)

SYMM 4X (0.42) ( 0.1)

VIA 0.05 MIN

ALL AROUND TYP 1 5 4X (0.22)

SYMM 4X (0.26)

(0.48) 3 2 4 (R0.05) TYP ( 0.25)

SOLDER MASK DEFINED

SCALE:60X 4223102/D 03/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note

in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

DPW0005A X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD 4X (0.42)

4X (0.22)

4X (0.06)

5 1 ( 0.24)

4X (0.26) SYMM

(0.21) TYP SOLDER MASK

EDGE 3 2 (R0.05) TYP (0.48)

4 SYMM (0.78)

SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 3 92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:100X 4223102/D 03/2022

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

DPW0005B X2SON - 0.4 mm max height

SCALE 12.000

PLASTIC SMALL OUTLINE - NO LEAD 0.85 0.75 B

APIN 1 INDEX AREA 0.85 0.75 0.4 MAX C SEATING PLANE

0.05 0.00 NOTE 3 2X (0.36) 0.35 0.15

4X 0.27 0.17 (0.1) TYP 2

4

NOTE 3 3 2X 0.48 1 2X (0.26)

5 4X PIN 1 ID 0.27 0.17 0.1 0.05 C A B C 4228233/D 09/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice. 3. The size and shape of this feature may vary.

www.ti.com

EXAMPLE BOARD LAYOUT

DPW0005B X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD (0.78)

SYMM 4X (0.42) 4X (0.06) 0.05 MIN

ALL AROUND TYP

5 4X (0.22) 1 (0.48) SYMM

3 4X (0.26)

2 4 (R0.05) TYP ( 0.25)

( 0.1) VIA (0.21) TYP EXPOSED METAL CLEARANCE SOLDER MASK OPENING, TYP METAL UNDER SOLDER MASK, TYP LAND PATTERN EXAMPLE

SOLDER MASK DEFINED

SCALE:60X 4228233/D 09/2023

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note

in literature No. SLUA271 (www.ti.com/lit/slua271).

www.ti.com

EXAMPLE STENCIL DESIGN

DPW0005B X2SON - 0.4 mm max height

PLASTIC SMALL OUTLINE - NO LEAD 4X (0.42)

4X (0.06)

5 4X (0.22) 1

( 0.24)

SOLDER MASK EDGE SYMM 3

(0.48)

(0.21) TYP

2 (R0.05) TYP 4 SYMM (0.78)

SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL

EXPOSED PAD 5 92% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:60X 4228233/D 09/2023

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

PACKAGE OUTLINE

D0008A SOIC - 1.75 mm max height

SCALE 2.800

SMALL OUTLINE INTEGRATED CIRCUIT C SEATING PLANE .228-.244 TYP [5.80-6.19] A .004 [0.1] C PIN 1 ID AREA

6X .050

[1.27] 8 1 2X .150 [3.81] .189-.197 [4.81-5.00] NOTE 3 4X (0 -15 )

4

5 B 8X .012-.020

[0.31-0.51] .010 [0.25] C A B .150-.157 [3.81-3.98] NOTE 4 .069 MAX [1.75] .005-.010 TYP [0.13-0.25] 4X (0 -15 )

SEE DETAIL A

.010 [0.25] .004-.010 [0.11-0.25] 0 - 8

.016-.050 [0.41-1.27] DETAIL A

(.041) [1.04] TYPICAL 4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15] per side.

4. This dimension does not include interlead flash. 5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

EXAMPLE BOARD LAYOUT

D0008A SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 )

[1.55]

SYMM SEE

DETAILS 1

8 8X (.024)

[0.6] 6X (.050 )

[1.27] SYMM 5 4 (R.002 ) TYP

[0.05] (.213) [5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:8X METAL SOLDER MASK OPENING EXPOSED

METAL

.0028 MAX [0.07] ALL AROUND SOLDER MASK

OPENING METAL UNDER SOLDER MASK EXPOSED

METAL

.0028 MIN [0.07] ALL AROUND SOLDER MASK

DEFINED NON SOLDER MASK

DEFINED SOLDER MASK DETAILS 4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

D0008A SOIC - 1.75 mm max height

SMALL OUTLINE INTEGRATED CIRCUIT 8X (.061 )

[1.55] SYMM

1

8 8X (.024)

[0.6] 6X (.050 )

[1.27] SYMM 5 4 (R.002 ) TYP

[0.05] (.213) [5.4] SOLDER PASTE EXAMPLE BASED ON .005 INCH [0.125 MM] THICK STENCIL

SCALE:8X 4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OUTLINE

YCK0009 DSBGA - 0.33 mm max height

SCALE 12.000

DIE SIZE BALL GRID ARRAY B A E BALL A1 CORNER

D0.33 MAX

CSEATING PLANE BALL TYP 0.125 0.075 0.05 C 0.7 TYP

SYMM C SYMM 0.7 TYP

B D: Max = 0.98 mm, Min = 0.92 mm 0.35 TYP

E: Max = 0.98 mm, Min = 0.92 mm A 1 9X

0.015 0.195 0.155 C A B 2 3 0.35 TYP 4225837/A 04/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

YCK0009 DSBGA - 0.33 mm max height

DIE SIZE BALL GRID ARRAY (0.35) TYP 9X ( 0.18)

1 2 3 A (0.35) TYP

SYMM

BC SYMM LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 50X 0.0325 MAX 0.0325 MIN METAL UNDER

SOLDER MASK EXPOSED

METAL ( 0.18) SOLDER MASK OPENING ( 0.18) METAL SOLDER MASK

OPENING EXPOSED METAL SOLDER MASK

DEFINED (PREFERRED)

NON-SOLDER MASK

DEFINED SOLDER MASK DETAILS

NOT TO SCALE 4225837/A 04/2020

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.

See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).

www.ti.com

EXAMPLE STENCIL DESIGN

YCK0009 DSBGA - 0.33 mm max height

DIE SIZE BALL GRID ARRAY (0.35) TYP (R0.05) TYP 9X ( 0.21)

1 2 3 A (0.35) TYP

SYMM

BC METAL

TYP SYMM SOLDER PASTE EXAMPLE BASED ON 0.075 mm THICK STENCIL

SCALE: 50X 4225837/A 04/2020 NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

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Last updated 10/2025