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2024 IEEE Energy Conversion Congress and Exposition (ECCE)

| 979-8-3503-7606-7/24/$31.00 ©2024 IEEE | DOI:

10.1109/ECCE55643.2024.10860273

Fast Circuit Simulation of Linear Electronic Circuits using Modified Nodal Analysis

Table 1 · 3 columns × 1 rows · p.1–1 · CSV
Nicolas VoyerAkinu NakabayashiRyota Kondo
Mitsubishi Electric Research andAdvanced R&D Center
Development Centre EuropeMitsubishi Electric Corporation
Rennes, FranceAmagasaki, Japan
[email protected][email protected][email protected]

Amagasaki, Japan [email protected] Abstract—This paper introduces a method that reaches the closed-form expression of waveforms in linear electronic circuits, enabling fast and accurate simulations. The method is automated for circuits described with Modified Nodal Analysis (MNA) formalism, that is easy to reach with collection of Kirchhoff laws. The method produces same closed-form expressions of waveforms as in State-Space Analysis (SSA), expressed as sums of weighted exponential functions of time, driven by characteristic frequencies of the circuit. However, the proposed method does not use SSA formalism and can therefore be applied to any circuit. The precise formulation of waveforms enables its computation in a single step with ultimate accuracy and constant CPU effort. Significant acceleration ratio was verified on DC/DC circuit by comparison with commercial simulation tool. The proposed method can effectively reduce the calculation effort at the design and verification stages of applications which need loss analysis over long mission profiles, like mobility applications.

Keywords— Simulation, Electronic circuits, Modified Nodal Analysis, State-Space Analysis

I. I NTRODUCTION

Simulation-based design of power electronic converters involves a very large number of simulations at various timescales, as key performance indicators (KPI) such as losses, temperature, must be verified over a large design space of circuit and control parameters. Each design must be verified at (or between) many operating conditions met during the desired mission of the converter. To deal with such a high number of simulations, the execution speed of simulation becomes crucial. Speed of execution and the related computing resource is also critical for other applications (e.g. virtual twin, model-predicted control, simulation/hardware-in-the-loop), which must run simulation faster than in real-time, in parallel to the real converter.

The speed of execution generally relates to the level of accuracy. In a first class of simple circuit solvers, circuit waveforms are assumed linear in time over small, fixed simulation step [1]. Accuracy is also affected by the choice of numerical integration method (e.g. Trapezoidal, BackwardEuler, Runge-Kutta, …). The simulation step must be carefully chosen to control inaccuracies brought from the linearity assumption. While the choice of small simulation steps improves the accuracy of simulation, it increases the number of timesteps for a given simulation period and negatively impacts the execution speed.

979-8-3503-7606-7/24/$31.00 ©2024 IEEE Ryota Kondo Advanced R&D Center Mitsubishi Electric Corporation

Amagasaki, Japan [email protected] To reduce the number of timesteps, a second class of circuit solvers use variable simulation steps, which are determined according to a given accuracy target [2]. As example, simulation steps are small during switching transients, and then relaxed after the ringing oscillations resulting from the switching. The reduced number of timesteps after the switching significantly accelerates the speed of simulation.

A third class of circuit solvers [3-4] use polynomial approximation of waveforms with time and both simulation step and polynomial order are adapted to reach desired accuracy with minimal complexity. This strategy can help increasing the simulation step for a given accuracy and further reduces the number of timesteps. Additional waveform coefficients must however be computed, negatively impacting the execution speed, but this can get compensated by the reduction in number of timesteps. This approach introduces the possibility of eventdriven simulation, where the simulation step is enlarged to the interval between consecutive simulation events (sampling, switching), skipping the simulation of circuit waveform at intermediate timesteps for the sake of accuracy.

All above strategies are applicable for any circuit using Modified Nodal Analysis (MNA) [5], where electronic circuit is described by the collection of Kirchhoff laws, relating the voltage waveforms of each circuit node with the current waveforms flowing in each branch of the circuit through a Laplace transfer function.

These strategies are equally applicable to circuits described with State-Space Analysis (SSA) formalism, where a single matrix relates the vector of circuit states to its derivatives and to power sources. The state vector contains waveforms driving the storage of energy in the passive components of the circuit, (e.g. capacitor voltage, inductor currents). For SSA formalism, a closed-form expression of state waveforms can be precisely formulated as a weighted sum of exponential functions of time [6-7], using eigen decomposition of the matrix. SSA formalism is thus very attractive for the simulation of electronic circuits, as waveforms can then be directly computed at any time event of interest (single-step simulation), without any need to simulate intermediate timesteps, at constant processing effort and without any impairment on accuracy.

The fixed or variable-order polynomial formulation used in MNA can be viewed as truncated Taylor-series approximation of the perfectly precise SSA exponential formulation. The 3825

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applicability of SSA exponential formulation to any electrical circuit is however limited, as for circuits with nonlinear The state vector #⃗ also relates to the waveform vector ⃗

circuit is however limited, as for circuits with nonlinear components (e.g. saturable inductances, diodes, voltage- dependent capacitances of transistors, …), the closed-form expression of waveforms derived from SSA no longer holds, and incremented-step approach is needed to keep accuracy under control. Yet, non-linear circuits can get locally linearized and therefore SSA has the potential to reduce CPU complexity. One other limiting factor in SSA is that automatic translation between the easy-to-reach MNA formalism and the easy-to- solve SSA formalism is not yet clearly established [8-11]. The present paper presents a novel method to automatically reach the precise formulation of waveforms using MNA formalism only. Section II first describes the mathematical equations of MNA and SSA formalisms for static electric circuits and then recalls the closed-form expression of waveforms reachable by SSA. Section III introduces the proposed new Fast Circuit Simulation (FCS) method that reaches the closed-form waveform formulation without SSA formalism for linear time-invariant (LTI) circuits. Section IV then addresses the usage of FCS in circuit composed of active devices driven by a circuit controller. Section V examines the simulation performance of proposed FCS solver applied to the simulation for DC/DC converter circuit experiencing Discontinued Current Mode (DCM) during deadtimes. II. MNA AND SSA FORMALISMS A. Modified Nodal Analysis We shall here consider an electronic circuit composed of branches and nodes. Considering that the last node o f the circuit i s grounded, the electrical circuit exhibits = + − 1 circuit w aveforms, collected i n waveform vector ⃗ . ⃗ = ,…, , ,…, (1) Branch impedance analysis yields branch voltage relations as f unction of branch current. Kirchhoff law of currents ⃗ through a simple a nd easy to determine matrix relation: #⃗ = , ⃗ (4) where , is a $ × matrix filled with values in {−1,0,1}. Collecting first the voltage equations of branches containing passive energy storage components (inductances, capacitances), MNA formulation (2) can be driven to have =01 . , 0 3 (5) where 1 is a $ × $ diagonal matrix containing values of inductances and c apacitances. B. Truncated Taylor-Series approximation The MNA system represented by (2) can be numerically solved, using polynomial approximation. The waveform vector is s e arched under a polynomial form with coefficient vectors 456 ⃗ 76 89 . ⃗ = ∑ 56 ⃗ 6 ;6 < = = ∑ 56 ⃗ 6 96 < = + >⃗ 9 (6) The derivation of waveform vector is then expressed as ⃗ = ∑ ? + 1 56 @ ⃗ 6 96 < = + >⃗ 9 (7) The resolution must start from the initial conditions observed on passive energy storage components of t he circuit, bringing $ relations for unknowns on vector 5=⃗ : #⃗ 0 = ,5=⃗ (8)

sented by an equation system: ⃗ + ⃗ = ⃗ (2)

of branches connected to each node of the circuit. For a circuit comprising ! capacitors and " inductors, t he energy state o f th e c ircuit is represented by the state vector #⃗ of size $ = ! + " . #⃗ = % !& , … , !' ( , )" & , … , )" ' * + (3)

Other missing relation terms may be found through recursive identification of polynomial terms arising from (2).

Identification on the kt h order each tim e adds new relations and new unknowns on vector 56 @ ⃗ : ?+1 56 @ ⃗ + 56 ⃗ = 6⃗ (9) where input power source term ⃗ = ∑ 6⃗ 6 ;6 < = is represented by its Taylor-series expansion. E ventually, th is

builds a linear system with ? + $ relations with ? + 1

unknowns. The apparent lack of relations can be resolved by neglecting highest order, and by setting − $ terms to zero in the last 5 6@ ⃗ expression.

The accuracy is driven by the term >⃗ 9 , which is a function of approximation order A and of step size and is approximated as:

‖>⃗ 9 ‖ ≅ D56 @ ⃗D 9@ (10)

The complexity of the linear system to be inverted increases with the approximation order, so that added complexity brought 3826

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by higher order approximation does not guarantee a significant complexity gain compared with using smaller steps.

initialisation Get

C. Solution formulation with State-Space Analysis

In SSA framework, the state vector relates to its derivatives according to:

#⃗ = EF FG# ⃗ + H⃗

(12) where {P K } K8 Q are eigenvalues of matrix E FFG identified as characteristic frequencies of electrical circuit, and ⃗ K , ≤ $ are corresponding eigenvectors of matrix E, i.e. E FFG ⃗ K = P K ⃗ K .

igenvectors of matrix E, i.e. EF F {JK }K 8 Q are identified from init #⃗ 0 = −EF FG H⃗ + ∑ JK ⃗K K J⃗ = S T #⃗ 0 + EF FG H⃗

(13)

(14) where S is a matrix gathering eigenvectors of matrix E FFG . The weight vector J⃗ is thus determined from (13), enabling the identification of state vector #⃗ at any time instant with (12).

Using (2), (4) and (12), considering that is of full rank, we ultimately reach the expression of full waveform vector:

ultimately reach the expression of full waveform ve ⃗ = T U ⃗ − V1. #⃗ 0 W where #⃗ = −EF FG H⃗ + ∑ JK P K L MN O ⃗K K

= −EF FG H⃗ + ∑ JK L MN O ⃗K K

(15)

(16)

The formal solution (15) brought by SSA thus allows the computation of waveforms at any time with perfect accuracy. In contrast to former MNA solver, SSA has great benefit of absence of any approximation, and a repeatable CPU complexity that is independent of initial conditions of the circuit.

Translating MNA equation system into SSA is however not a trivial task and could not yet be generalised especially for circuits with a large number of circuit branches.

III. F AST C IRCUIT S OLVER

The Fast Circuit Solver (FCS) presented in this section addresses static circuits, composed of RLC components and variable power sources.

A. Overall solver workflow

Fig. 1 depicts the general workflow of the proposed fast circuit solver. An initialization stage gathers computation steps that are independent of circuit state. This includes the identification of MNA matrices and , a triangulation of the Get Get and Get (11) where E FFG is a full-rank I × I matrix, and H ⃗ is representative of the input power source vector ⃗ . From (11), and assuming constant power sources H ⃗ = H ⃗ , the solution elegantly comes as

es as #⃗

Step simulations Get and Get Fig. 1. Workflow of proposed Fast Circuit Solver related Laplace matrix E X G Y using two Gauss-Jordan elimination steps, the identification of a vector characteristic frequencies Z ⃗ , the determination of a filter matrix ,[ of input power sources, and the determination and the inversion of a matrix ,\ of weights of transfer functions.

The simulation step determines a vector S ⃗ of filtered functions of power sources, a weight vector ] ⃗ , and characteristic functions of time ^ ⃗ and finally the circuit waveforms _ ⃗ at any instant t from the initial conditions of passive components _ ⃗ 0

. The complexity of the simulation step is independent of the time at which the waveforms must be computed.

B. Notations and Lower-Upper (LU) decomposition

MNA equation (2) can get rewritten as

2) can get rewritten as EX G Y ⃗ = ⃗ (17)

where E X G Y = + Y is a matrix of transfer functions, and Y is the Laplace operator: Y 6 = 6 a 6 . Considering E X G Y is of full rank, we shall apply a first Gauss-Jordan elimination step. Using pivotal matrix b Y , we get

c Y d⃗ =b Y ⃗ (18)

where c Y = b Y EX G Y is an u pper tr iangular matrix of transfer functions, w ith 5 K ,e Y = 0 ∀g, ∀ > g , and unity diagonal terms: ∀ , 5K ,K Y = 1 . As also shown in Fig. 2, a second partial Gauss-Jordan

elimination step is then applied. Using upper triangular matrix b i Y

, we get

j Y d⃗ = bi Y b Y ⃗ (19)

j Y d⃗ = bi Y b Y ⃗ (19) where j Y = bi Y b Y EX G Y is still a n upper triangular matrix o f t ransfer fu nctions, w ith k K , e Y = 0 ∀ < , ∀g ≠ , and unity d iagonal terms : ∀ , k K ,K Y = 1 , ze ro t erms elsewhere kK ,e Y = 0 , (∀ g, < g < ), except on the last

where j Y = bi Y b Y EX G Y is still a n upper triangular matrix o f t ransfer fu nctions, w ith k K , e Y = 0 ∀ < , ∀g ≠ , and unity d iagonal terms : ∀ , k K ,K Y = 1 , ze ro t erms elsewhere kK ,e Y = 0 , (∀ g, < g < ), except on the last column, where k K , n Y = −o K Y ≠ 0 ∀ < .

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waveform n through a transfer fu nction oK Y . For the sake of no tations, we s hall denote xy⃗ the canonical vector (xy⃗ = 1, xy⃗ g ≠ = 0 , to reach K = oK Y n + xy⃗ . bi Y b Y ⃗ (25)

1 2 successive

{ { } }

Unlike traditional LU decomposition, t he second Gauss- Jordan elimination is applied on the − 1 first d imensions only, preserving transfer relations between th e last waveform and all other waveforms in the circuit. Some terms oK Y on the last column could be zero if the electronic circuit can b e severed into disjoint subcircuits, in which case waveforms of one subcircuit cannot get interrelated to waveforms of other subcircuits. For circuits th at cannot be reduced into disjoint subcircuits, all circuit waveforms are interrelated with non-zero transfer functions, and oK Y r epresents the transfer function between each it h w aveform a nd th e last waveform of circuit waveform vector ⃗ . Gains oK Y are analogue to the Mason’s gains applied t o the signal fl ow graph (SFG) of the circuit [12]. C. Identification of characteristic frequencies On its last dimension, equation (19) expresses the last waveform as n = ∑ pq , n, 6 Y 6 6 (20) By pivotal construction, pq , n, 6 Y is a transfer function, equal to a ratio of Y polynomials pq , n6 Y = $' n, r s t s (21) E quation (20) can thus be reduced to the following ordinary differential equation (ODE) driven by characteristic polynomial u Y , the common denominator of matrix b Y : u Y % n −v +=0 (22) where v = ∑ w n, 6 Y 6 6 . The last waveform n thus necessarily t akes t he f ollowing formal expression of time: n = v + ∑ J6 L Mr O 6 (23) where ]⃗ = {J6 } is a vector of complex w eights and {P6 } are the characteristic f r equencies of the circuit, i dentified as c omplex roots of the characteristic polynomial u Y u P6 = 0 (24) D. Intermediate formulation of circuit waveforms sake of no tations, we s hall denote xy⃗ the canonical vector (xy⃗ = 1, xy⃗ g ≠ = 0 , to reach K = oK Y n + xy⃗ . bi Y b Y ⃗ (25) From (22) and identification of characteristic components in (24), we then reach the expression of each circuit waveform: K = ∑ J6 oK P6 L Mr O 6 8 Q + zK (26) where zK are filtered functions of input power sources and transfer f unction [K Y of corresponding filters are expressed as: zK = [K Y ⃗ (27) [K Y = x⃗K + oK Y x⃗ n . bi Y b Y (28) E. Filtered function of example power sources By construction (28), transfer functions of filters are determined as ratios of polynomial transfer functions: [K Y = {N s t s = ∑ | N rs r r ∑ } r s r r (29) The proposed a nalysis is applicable to any input power sources. When power source is sinusoidal with time, then filtered functions zK are also oscillating with same frequency but different amplitude and phase: ⃗ = ~ Le •O@€ H⃗= , (30) zK = ~ Le •O@€[ K g• H⃗= (31) When power source is linear with time ⃗ = H⃗= + H⃗ , (32) Then, if ‚= ≠ 0, zK = K= + K is also linear with time. ƒ K = |N „ } „ H ⃗ K= = |N „ } „ H⃗= + }„ | N & } & | N „ } „ … H⃗ (33) Some derated cases may occur with ‚= = 0 : as example when a capacitor is connected in series with a cu rrent source, or when an inductance is connected in parallel t o a voltage s ource. Then zK gets quadratic with time zK = K + K† †. ƒ K† = |N „ } & H ⃗ K = |N „ } & H⃗= + }& | N & } ‡ | N „ } & … H⃗ (34) Fig. 2. MNA matrix of transfer function EX G Y is m odified with 2 successive Gauss-Jordan elimination steps with matrices bi Y and b Y . Final matrix j Y is identity matrix with nonzero elements on i ts last column. { } 1 { } { } { } Gauss-Jordan pivot steps

Nevertheless, it is possible to always avoid derated cases, simply adding artificial (large) resistances ˆ ‰ in parallel to 3828

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capacitors, and (small) in series to inductors. With an appropriate choice of each resistance ˆ ‰ , the resulting time constants Š ! = ˆ ‰ ‹, Š " = Œ/ˆ ‰ is significantly higher than the simulation step time (e.g. switching period), and eventually the associated inaccuracy brought by adding artificial resistance is limited to a desired level /Š ! .

F. Identification of weights from initial conditions

F. Identification of weights from initial conditions Waveform of energetic p assive component #⃗ 0 = , ⃗ 0 are k nown a t i nitial time = 0. Using (26), in troducing a m atrix \ = 4oK e=o K Pe 7 , and no ting ⃗ = ,z⃗ where z⃗ = %z ,…,z n + , initial conditions come as #⃗ 0 = , ⃗ 0 = ,\J⃗ + ⃗ 0 (35)

ally identified as %#⃗ 0 − ⃗ 0 + (36)

The weight vector J⃗ is finally identified as

ector J⃗ is fi J⃗ = ,\

It should be noted here that the matrix ,\ to get inverted is independent of initial circuit conditions and of dimensions $ × $

, equal to that of SSA formulation, and of much reduced complexity compared with the × dimension of matrix of initial MNA problem expressed from (9).

Some derated cases may occur when ,\ is singular and cannot get inverted. This occurs as example when capacitors are connected in parallel, or inductors are connected in series and therefore share the same transfer function o K Y . Such derated case can get avoided by simplification of circuit, merging the parallel capacitors or the series-connected inductances into a single component.

G. Final formulation of waveforms

Once weight vector J⃗ is identified, the waveform vector is identified from (26) as

identified from (26) as ⃗ = z⃗ + \ %J⃗ ∨ •⃗ + (37) where •⃗ = L M& O ,…,L M' QO are characteristic functions of time of th e circuit, identified by characteristic frequencies {P6 }. ∨ is the term-by-term product operator. Using (4), state vector becomes #⃗ = ⃗ + ,\ %J⃗ ∨ •⃗ + (38)

IV. C IRCUITS WITH ACTIVE DEVICES

A. Ideal switch concept

Modern power electronic designs generally also comprise switching devices, such as diodes or transistors. In these circuits, the circuit state changes together with the conduction or the blocking state of its switching components.

After switching transients, the circuit derates into RLC subcircuits, which can be analyzed with the proposed FCS method. Switching transients carry information on switching losses, and occur at nanoseconds scale, especially for wide bandgap devices (SiC, GaN). This time scale is generally small with respect to the precision of pulse-width modulation (PWM) (few hundreds of nanoseconds), and to the deadtime (few microseconds or less) applied to top and bottom switches of half bridges. Analytic model of switches comprises ideal switches, parasitic RLC components, waveform-controlled power source and e.g. non-linear Miller or output capacitance, that impact switching transients. On the other hand, simulations of switching transients involve nanosecond-scale precision, which is hardly compatible with the objective of reduction of CPU effort for simulation.

Using ideal switches in the simulation can relax the simulation effort, as switching losses can be later be accounted for using loss maps, where switching losses are functions of arm current and bus voltage, of gate circuit parameters (e.g. gate resistance, low/high gate voltages) and/or of junction temperature. Such maps are ideally tabulated using measurements or simulation results of double pulse test method.

B. Circuit / Controller interactions

Active devices (IGBTs, MosFETs) being modelled as ideal switches, the circuit topology evolves dynamically according to the conduction state of circuit switches, as shown in Fig. 3 for a simple DC/DC boost circuit example. For a given switching state, the circuit derates into one or several independent subcircuits built of only passive and power source elements. Non-conductive switches get removed from the circuit, and conductive switches are replaced with shortcut current paths.

At initialization stage, FCS initialization is run for all subcircuits of all possible states of the circuit. The associated relatively CPU-consuming tasks are realized only once.

The final expressions (37) and (38) are very similar to (15) and (12), leading to the same analytical solution, built with identical exponential characteristic functions: they are both equally precise, for any time instant, and without approximation / truncation of polynomial solution.

With the proposed MNA method, the closed-form expression of waveform was reached without identification of SSA framework, nor eigenvector analysis of SSA matrix.

a) b)

c) d)

Fig. 3. Decomposition of boost converter circuit (a) into disjoint subcircuits for each half-bridge state: (b) bottom-side connected, (c) disconnected, (d) topside connected 3829

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At simulation stage, the circuit simulator must operate in coordination with one or more circuit controller. Circuit controller takes as input some waveform data sampled at precise ADC sampling events, and then determines the timing of next switching and next ADC events. As an example, the circuit controller decides switching events according to PWM, by comparison of a triangular PWM carrier and desired modulating voltage, and the timing of ADC events are aligned with the edges of PWM carrier.

C. Transitions between circuit states

The circuit simulator applies fast circuit solver individually for each subcircuit concerned by the present state of the circuit. The waveforms of the circuits are partitioned across subcircuits and determined by each solver according to the initial conditions of the passive circuit component (at the time of entering the circuit state), and to the timings of ADC and next switching events. At the effective time of switching, the state of the circuit is updated according to the controller output, leading to different active subcircuits. The solvers associated with these subcircuits are then used for the following simulation step, until a new switching event occurs. The initial state conditions #⃗ 0 of the circuit is used to estimate weights J⃗ from (36). For subsequent time events following the change of circuit, the state waveforms #⃗

is determined using (38). Optionally, all other circuit waveforms ⃗ may get computed using (37).

D. Deadtimes

In circuits composed of half-bridges, circuit controller must implement a deadtime between the activation periods of top and bottom switches to avoid short circuit across top and bottom switches during the switching transients. During deadtime, the half bridge current continues to flow in either body diode or freewheeling diodes. Which (top or bottom) diode conducts is determined by the direction of current. This behaviour is known as Continuous Current Mode (CCM). Depending on the sign of current, CCM can be modelled as instant switching or switching with a simple delay brought by the deadtime as seen in Fig. 4.

During deadtime though, the half bridge current may reach zero value, an event at which the circuit enters Discontinuous Current Mode (DCM). In DCM, top and bottom switches are both in blocking state, meaning that the circuit is no longer in the initial state, and not yet in its final state. The mid-point of the half bridge is simply disconnected from both top and bottom points due to combined interlocking of body/forward diodes.

Delayed Switching DCM type I Control event Instant Switching DCM type II Deadtime event Zero-crossing event

Fig. 4. Effective timings of switching during deadtimes

The general workflow of circuit simulation is not much affected by the presence of deadtime, CCM and DCM, it only needs to simulate waveforms at events additional to those defined by the controller. In Fig. 4, control time events for switching are followed by additional end-of-deadtime events. The effective timing of state switching is dictated by the direction of current simulated at the control time event, as one bypass diodes of the half bridge can immediately start conduction.

As shown in Fig. 5, if the current reverses sign between control and deadtime events, another zero-crossing (ZC) event is added, at which circuit enters another state, where both top and bottom switches are disconnected. This state is short lived, as effective switching then gets effective at the end of the deadtime. The timing of zero-crossing event is determined from estimated currents at switching and deadtime events, assuming that the current behaves linearly at this time scale, and under assumption that diode would be still conducting while polarised.

V. V ERIFICATION OF FCS PERFORMANCE

A. DC/DC converter with DCM during deadtimes

In our application example shown in Fig. 6 and table I, a bidirectional DC/DC boost chopper is fed by a battery and aims at delivering higher DC voltage to a load with regeneration capability. The load is symbolised as a controllable current source.

The circuit controller decides the activation timing of the unique half bridge to steer the DC bus voltage to some predetermined DC bus voltage reference. Switching frequency

Fig. 5. Handling of transitions between switching states including effect of deadtime and DCM.

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TABLE I P ARAMETERS FOR VERIFICATION OF SIMULATION CONCEPT

g. 8 (left) confirms that fixed-step simulation results v PA RAMETERS FOR VERIFICATION OF SIMULATION CONCEPT Parameter Value Parameter Value • “O 200 V • s ∗ 650 V ˆ “ O 50 mΩ Œ 170mH ˆ " 50 mΩ ‹ “ O 250 mF ) ‘ ’“” 100 / -100 A ‹ •s 850 µF ™s KOš› 5kHz ™! œ " 10 kHz deadtime 4 µs ? • 0.1 s

Fig. 6. DC/DC converter circuit and waveforms of passive components used for the verification of simulation concept 150

100

50

0

-50

-100

-150

0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

Time (s) Fig. 7. Reversal of controllable load current source

was set to 5kHz, and controller operates at 10 kHz, with DC bus voltage ADC sampled at both edges of PWM carrier. The duty cycle of the half bridge is controlled by an integral regulator to steer the capacitor voltage to the desired regulation voltage. As shown in Fig. 7, at = 0.05Y, the load current source ) ‘’“”

changes from power consumption mode to power regeneration mode. During the power ramp period, the energy collected in the passive energy storage device must adapt to new levels, causing an inevitable overshoot in DC bus voltage ! •s . Such overshoot may be harmful to the design of the DC/DC converter and needs to get evaluated with accuracy.

according to the choice of simulation step. On the right side are displayed waveforms computed only at timings of interest with FCS: switching (SW) timings decided by controller, sampling (ADC) events, end of deadtimes (DT), and possibly Zerocrossing events (ZC/DCM) occurring during deadtimes.

With both simulators, the circuit exhibits secondary overshoots amplified by the duration of deadtime, with DCM occurrence when the inductor current " enters (around = 0.06Y)

and leaves (around = 0.07Y) the zero-current area in presence of deadtimes, as indicated by the presence of ZC/DCM events. To replicate such secondary overshoot with accuracy, the simulation of precise behaviour of DCM in such situation typically requires a high precision on the simulation step, which should be typically much smaller than the deadtime.

Fig. 9 shows the differences in the results obtained with commercial simulation software under different timesteps versus results reached with proposed approach, around the main peak in DC bus voltage overshoot.

The observed differences not only lie in the accuracy of waveform prediction between two simulation steps. Conventional fixed step simulators have additional following weaknesses:

The verification of this power reversal scenario was realized with proposed fast circuit simulation (FCS) and compared with the results of commercial circuit simulation tool (PSIM [5]).

740 720 700 680 660 640 620

0.04 • the timing precision of sampling and switching events

(including deadtime and zero-crossing) is necessarily limited by the simulation step, 740

waveform ADC events SW events DT events ZC/DCM events 720 700 680 660 640 0.05 0.06 0.07 0.08 0.09 620 0.04 0.1 0.05 0.06 500 500 0 0 0.09 0.1 waveform ADC events SW events DT events ZC/DCM events 0.05 0.06 0.07 0.08 0.09 0.04 0.1 0.05 0.06 240 240

220 220

200 200

180 180 0.05 0.06 0.07 0.07 0.08 0.09 0.1 Time (s) Time (s)

160

0.04 0.08 -500 -500

0.04 0.07 Time (s) Time (s)

0.08 0.09 160 0.04 0.1 waveform ADC events SW events DT events ZC/DCM events 0.05 0.06 0.07 0.08 0.09 0.1 Time (s) Time (s) Fig. 8. Comparison of circuit waveforms (left) fixed simulation steps (blue : 1žY , red : 10ŸY ) versus (right) Fast Circuit Simulator (FCS)

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TABLE II C OMPARISON OF SIMULATORS FOR DC/DC BOOST CIRCUIT Simulator Number of Elapsed Peak Vbus

simulation CPU time Level (V)

steps Fast Circuit Solver 6028 97 ms 734.9 1us fixed step 2e5 1 s 730.2 100ns fixed step 2e6 8 s 734.4 10ns fixed step 2e7 98 s 734.8 Fig. 9. Comparison of detailed circuit waveform using FCS vs commercial simulation software with different time steps

• the circuit behaviour is not clearly defined between

consecutive simulation steps surrounding a zero crossing, as the circuit state is not unique in that period.

• duty cycles decided by controller are sensitive to input

ADC waveform inaccuracies, also causing supplemental marginal errors. Selecting smaller simulation steps, the above impairments of fixed-step simulators can get reduced. Ultimately, results of fixed step simulator then converge towards FCS results with ultimate accuracy. Table II shows that the improved accuracy comes with a higher number of simulation steps and a CPU effort increased by several orders of magnitude.

In comparison, FCS reaches same accuracy results (100mV ~ 0.01%) with a CPU effort reduced by a factor 1000, with even higher impact on disk/memory usage. Despite implementation in interpreted software language on a standard i7-1265U 1.8GHz laptop computer, FCS was even faster than real-time on this application.

II. C ONCLUSION

As known from SSA analysis, the simulation of power electronic circuit can be greatly accelerated using closed-form expression of its waveforms as function of time : waveforms are directly expressed at the event timings of interest, skipping the need for evaluation at intermediate simulation steps. The formal solutions are expressed as a weighted sum of exponential functions of time. The formulation is exact and is free of inaccuracies resulting from truncation of polynomial series.

We have presented an automated algorithm that determines the characteristic complex frequencies of the circuit, and the complex weights required in this analytical expression using the easy-to-reach MNA description of the circuit. The obtained solution is mathematically equivalent to that reached using SSA. Thus, circuit waveforms can get directly formulated skipping the difficult problem of translating MNA into SSA.

The proposed method was applied for the verification of bidirectional DC/DC converter, aiming at evaluating the voltage overshoot during torque reversal, under influence of DCM during deadtimes.

Compared with existing commercial simulation software, the proposed fast circuit simulation method could drastically reduce the simulation effort for design/control verification over the long mission profiles involved in the development of emobility solutions. The memory/disk footprint of simulation is also greatly reduced as waveform details are stored with much less number of samples.

By construction, the proposed MNA method can apply to any linear circuit. Further investigation is needed to extend the method to the simulation of non-linear circuits e.g. comprising saturable inductances and/or rotating machines.

The approach is very promising for accelerating simulation effort and may also enable new usage of real-time simulation in embedded applications, e.g., simulation-in-the-loop, digital twins, or model-predicted control.

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