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DS13805 - Rev 6 - July 2024 For further information contact your local STMicroelectronics sales office.
Specifically designed for long-range, multitarget measurements, the VL53L4CX provides very accurate distance measurements up to 6 m with excellent results over short distances. A new generation laser emitter with 18° FoV improves performance under ambient light. Thanks to ST's patented algorithms and innovative module construction, the VL53L4CX is also able to detect multiple objects within the FoV with depth understanding. ST histogram algorithms ensure cover glass crosstalk immunity beyond 80 cm and dynamic smudge compensation for targets below 80 cm. Like all Time-of-Flight sensors based on ST's FlightSense technology, the VL53L4CX records an absolute distance measurement regardless of the target color and reflectance. Housed in a miniature reflowable package, which integrates a SPAD (single photon avalanche diode) array, the VL53L4CX achieves the best ranging performance even when hidden behind a wide range of cover glass materials. All of ST's Time-of-Flight sensors integrate a VCSEL (vertical-cavity surface-emitting laser) which emits a fully invisible 940 nm IR light, which is totally safe for the eyes (Class 1 certification).
DS13805 - Rev 6 page 2/38
Product overview
Table 1. Technical specification
| Feature | Detail |
|---|---|
| Package | Optical LGA12 |
| Size | 4.4 x 2.4 x 1 mm |
| Operating voltage | 2.6 to 3.5 V |
| Operating temperature | -30 to 85°C |
| Infrared emitter | 940 nm |
| I²C | Up to 1 MHz (fast mode plus) serial bus Address: 0x52 |
DS13805 - Rev 6 page 3/38
Product overview
The following figure shows the pinout of the VL53L4CX (see also Section 7: Outline drawings).
Figure 2. VL53L4CX pinout (bottom view)
| Pin number | Signal name | Signal type | Signal description |
|---|---|---|---|
| 1 | AVDDVCSEL | Supply | VCSEL supply, to be connected to main supply |
| 2 | AVSSVCSEL | Ground | VCSEL ground, to be connected to main ground |
| 3 | GND | Ground | To be connected to main ground |
| 4 | GND2 | Ground | To be connected to main ground |
| 5 | XSHUT | Digital input | Xshutdown pin, active low |
| 6 | GND3 | Ground | To be connected to main ground |
| 7 | GPIO1 | Digital output | Interrupt output. Open drain output |
| 8 | DNC | Digital input | Do not connect, must be left floating |
| 9 | SDA | Digital input/output | I²C serial data |
| 10 | SCL | Digital input | I²C serial clock input |
| 11 | AVDD | Supply | Supply, to be connected to main supply |
| 12 | GND4 | Ground | To be connected to main ground |
To be connected to main ground Note: AVSSVCSEL and GND are ground pins and can be connected together in the application schematics. Note: GND2, GND3, and GND4 are standard pins that are forced to the ground domain in the application schematics
to avoid possible instabilities if set to other states.
DS13805 - Rev 6 page 4/38
Product overview
The following figure shows the application schematic of the VL53L4CX.
Table 3. Suggested pull-up and series resistors for I²C fast mode
| I²C load capacitance (CL)(1) | Pull up resistor (Ohms) | Series resistor (Ohms) |
|---|---|---|
| CL ≤ 90 pF | 3.6 k | 0 |
| 90 pF < CL ≤ 140 pF | 2.4 k | 0 |
| 140 pF < CL ≤ 270 pF | 1.2 k | 0 |
| 270 pF < CL ≤ 400 pF | 0.8 k | 0 |
| CL ≤ 90 pF | 1.5 k | 100 |
| 90 pF < CL ≤ 140 pF | 1 k | 50 |
| 140 pF < CL ≤ 270 pF | 0.5 k | 50 |
| 270 pF < CL ≤ 400 pF | 0.3 k | 50 |
DS13805 - Rev 6 page 5/38
Product overview Table 4. Suggested pull-up and series resistors for I²C fast mode plus
I²C load capacitance (CL) (1) Pull up resistor (Ohms) Series resistor (Ohms)
DS13805 - Rev 6 page 6/38
Functional description
Figure 4. VL53L4CX system functional description shows the system level functional description. The host customer application controls the device using an API (application programming interface). The API implementation is delivered to the customer as a driver (bare C code, or Linux/Android driver). The driver shares with the customer application a set of high level functions that allow control of the firmware, like initialization, ranging start/stop, setting the system accuracy. The driver is a turnkey solution consisting of a set of “C” functions that enable fast development of end-user applications without the complication of direct multiple register access. The driver is structured in a way that it can be compiled on any kind of platform through a well abstracted platform layer. The driver package allows the user to take full advantage of the VL53L4CX capabilities. A detailed description of the driver is available in the user manual (UM2923). The firmware fully manages the hardware registers access. Section 2.2: State machine description details the firmware state machine.
DS13805 - Rev 6 page 7/38
Functional description
The following figure shows the device state machine.
Figure 5. Device state machine Power Off
Host applies AVDD Host removes AVDD
HW Standby
Host raises XSHUT Host lowers XSHUT
Initial Boot SW Standby
Host initiates START Host initiates STOP Continuous Ranging Host clears interrupt Next range starts automatically after Host has cleared the interrupt
Up to calibrations are needed to ensure the best sensor performances. Offset needed in all applications. If a cover glass is used, crosstalk calibration is also needed. Two part-to-part calibrations are needed to ensure the best sensor performance, while one is optional. Offset and RefSpad calibrations are needed in all applications. If a cover glass is used, crosstalk calibration data are needed. The xtalk calibration data can be measured during a part-to-part calibration in the customer production line, and stored in the host, as part-to-part calibration data. Xtalk calibration data can also be computed from a xtalk characterization of a few devices, not in the production line, and stored in the host as generic calibration data. The detailed procedure is provided in the VL53L4CX user manual (UM2923).
The device physical control interface is I²C, described in Section 3: Control interface. A software layer (driver) is provided to control the device. This avoids complex I²C register operations with turnkey functions to start, stop, and read the ranging values. The driver structure and functions are described in the VL53L4CX user manual.
DS13805 - Rev 6 page 8/38
Functional description
The VL53L4CX dedicated operating mode is “Ranging mode”. In this mode, the software driver proposes turnkey functionalities to allow fast and easy ranging in all customer applications. • • • Ranging mode is natively immune to cover glass crosstalk and smudge beyond 80 cm. Ranging mode can detect several objects concurrently within the FoV. Up to four ranges can be output simultaneously by the software driver, to indicate an object's range. Check the latest software driver manual for further details. Ranging operation is performed by default at 30 Hz once the driver function is called (typical ranging operation lasts 33 ms). It includes internal housekeeping, ranging, and postprocessing. Note: Ranging mode requires a handshake between the host and the VL53L4CX, at each ranging operation. This
handshake is mandatory to ensure that the right result is read by the host to continue the ranging operation. Refer to Section 2.10: Handshake management for further details.
Digital processing is the final operation of the ranging sequence that computes, validates or rejects a ranging measurement. Part of this processing is performed by the internal firmware and completed on the host processor running the software driver. At the end of digital processing, the ranging distance is computed by the device itself. If the distance cannot be measured (no target or weak signal), a corresponding status error code is generated and can be read by the host. A full description of the status errors is provided in the VL53L4CX user manual (UM2923).
DS13805 - Rev 6 page 9/38
Functional description
The software driver provides turnkey functions to read output results after the measurement: • • • Signal rate Ranging distance Ambient light level A full description is provided in the VL53L4CX user manual (UM2923).
There are two options available for device power-up and boot sequence. Note: In all cases, XSHUT has to be raised only when AVDD is tied on.
Option 1
The XSHUT pin is connected and controlled from the host. This option optimizes power consumption as the device can be completely powered off when not used, and then woken up through the host (using the XSHUT pin). HW STANDBY mode is the period when AVDD is present and XSHUT is low.
Note: t BOOT is 1.2 ms maximum.
Option 2
The XSHUT pin is not controlled by the host; it is tied to AVDD through the pull-up resistor. When the XSHUT pin is not controlled, the power-up sequence is presented in the following figure. In this case, the device goes automatically to SW STANDBY after FW BOOT, without entering HW STANDBY.
Note:
DS13805 - Rev 6 t BOOT is 1.2 ms maximum.
page 10/38
Functional description
Note: API in the figure above means application programmable interface. Note: t timing_budget is a parameter set by the user, using a dedicated driver function.
Once a ranging measurement is available, an interrupt is generated. This is communicated to the host as a physical signal on the GPIO1 pin, which is driven low, and the output of a driver function. The former operating method is called “hardware interrupt”, and the latter is referred to as “polling mode”. Once the host reads the result, the interrupt is cleared by the driver and the ranging sequence can continue. If the interrupt is not cleared, the ranging operation inside the device is on hold. The interrupt behavior allows a good synchronization between the device and the host, which avoids losing results if the host is not available to acquire or process the data. It is strongly recommended to use the hardware interrupt pin to manage this handshake. For more details, refer to the VL53L4CX user manual.
DS13805 - Rev 6 page 11/38
Control interface
This section specifies the control interface. The I²C interface uses two signals: serial data line (SDA) and serial clock line (SCL). Each device connected to the bus uses a unique address and a simple controller/target relationship exists. Both SDA and SCL lines are connected to a positive supply voltage using pull-up resistors located on the host. Lines are only actively driven low. A high condition occurs when lines are floating and the pull-up resistors pull lines up. When no data is transmitted both lines are high. Clock signal generation is performed by the controller device. The controller device initiates data transfer. The I²C bus has a maximum speed of 1 Mbits/s and uses a default device address of 0x52.
Figure 9. Data transfer protocol Acknowledge Start condition SDA
MSB
SCL S LSB 1 3 2 4 5 8 7 6
Address or data byte Ac/Am P Stop condition Information is packed in 8-bit packets (bytes) and is always followed by an acknowledge bit, Ac for VL53L4CX acknowledge and Am for controller acknowledge (host bus controller). The internal data is produced by sampling SDA at a rising edge of SCL. The external data must be stable during the high period of SCL. The exceptions to this are start (S) or stop (P) conditions when SDA falls or rises respectively, while SCL is high. A message contains a series of bytes preceded by a start condition, and followed by either a stop or repeated start (another start condition but without a preceding stop condition), followed by another message. The first byte contains the device address (0x52) and also specifies the data direction. If the least significant bit is low (that is, 0x52) the message is a controller-write-to-the-target. If the LSB is set (that is, 0x53) then the message is a controller-read-from-the-target.
Figure 10. I²C device address: 0x52 LSBit MSBit
0 1 0 1 0 0 1 R/W All serial interface communications with the Time-of-Flight sensor must begin with a start condition. The VL53L4CX module acknowledges the receipt of a valid address by driving the SDA wire low. The state of the read/write bit (LSB of the address byte) is stored and the next byte of data, sampled from SDA, can be interpreted. During a write sequence, the second byte received provides a 16-bit index, which points to one of the internal 8-bit registers.
DS13805 - Rev 6 page 12/38
Control interface
As data are received by the target, they are written bit by bit to a serial/parallel register. After each data byte has been received by the target, an acknowledge is generated, the data are then stored in the internal register addressed by the current index. During a read message, the contents of the register addressed by the current index is read out in the byte following the device address byte. The contents of this register are parallel loaded into the serial/parallel register and clocked out of the device by the falling edge of SCL.
Figure 12. Data format (read)
0x52 (write) S ADDRESS[7:0] As INDEX[15:8] As INDEX[7:0] As P 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am P At the end of each byte, in both read and write message sequences, an acknowledge is issued by the receiving device (that is, the VL53L4CX for a write, and the host for a read). A message can only be terminated by the bus controller, either by issuing a stop condition or by a negative acknowledge (that is, not pulling the SDA line low) after reading a complete byte during a read operation. The interface also supports auto increment indexing. After the first data byte has been transferred, the index is automatically incremented by 1. The controller can therefore send data bytes continuously to the target until the target fails to provide an acknowledge or the controller terminates the write communication with a stop condition. If the auto increment feature is used, the controller does not have to send address indexes to accompany the data bytes.
DS13805 - Rev 6 page 13/38
Control interface Figure 14. Data format (sequential read)
0x52 (write) ADDRESS[7:0] S INDEX[15:8] As INDEX[7:0] As As P 0x53 (read) S ADDRESS[7:0] DATA[7:0]
| I²C interface -Timing characteristics explanation of the Timings are given for | S | ADDRESS[7:0] | As | INDEX[15:8] | As | INDEX[7:0] | As | P | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| I²C interface -Timing characteristics explanation of the Timings are given for | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | ||||||||||||||||
| I²C interface -Timing characteristics explanation of the Timings are given for | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | ||||||||||||||||
| I²C interface -Timing characteristics explanation of the Timings are given for | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | ||||||||||||||||
| I²C interface -Timing characteristics explanation of the Timings are given for | I²C interface -Timing characteristics explanation of the Timings are given for | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) |
| I²C interface -Timing characteristics explanation of the Timings are given for | I²C interface -Timing characteristics explanation of the Timings are given for | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) | 0x53 (read) S ADDRESS[7:0] As DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am P timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an parameters used. all PVT conditions. Table 5. I²C interface -timing characteristics for fast mode plus (1 MHz) |
| Symbol | Parameter | Parameter | Parameter | Parameter | Parameter | Parameter | Minimum | Typical | Typical | Typical | Maximum | Maximum | Maximum | Maximum | Maximum | Maximum | Unit |
| FI2C | Operating frequency | Operating frequency | Operating frequency | Operating frequency | Operating frequency | Operating frequency | 0 | - | - | - | 1000 | 1000 | 1000 | 1000 | 1000 | 1000 | kHz |
| tLOW | Clock pulse width low | Clock pulse width low | Clock pulse width low | Clock pulse width low | Clock pulse width low | Clock pulse width low | 0.5 | - | - | - | - | - | - | - | - | - | μs |
| tHIGH | Clock pulse width high | Clock pulse width high | Clock pulse width high | Clock pulse width high | Clock pulse width high | Clock pulse width high | 0.26 | - | - | - | - | - | - | - | - | - | μs |
| tSP | Pulse width of spikes that are suppressed by the input filter | Pulse width of spikes that are suppressed by the input filter | Pulse width of spikes that are suppressed by the input filter | Pulse width of spikes that are suppressed by the input filter | Pulse width of spikes that are suppressed by the input filter | Pulse width of spikes that are suppressed by the input filter | - | - | - | - | 50 | 50 | 50 | 50 | 50 | 50 | ns |
| tBUF | Bus free time between transmissions | Bus free time between transmissions | Bus free time between transmissions | Bus free time between transmissions | Bus free time between transmissions | Bus free time between transmissions | 0.5 | - | - | - | - | - | - | - | - | - | μs |
| tHD.STA | Start hold time | Start hold time | Start hold time | Start hold time | Start hold time | Start hold time | 0.26 | - | - | - | - | - | - | - | - | - | μs |
| tSU.STA | Start setup time | Start setup time | Start setup time | Start setup time | Start setup time | Start setup time | 0.26 | - | - | - | - | - | - | - | - | - | μs |
| tHD.DAT | Data in hold time | Data in hold time | Data in hold time | Data in hold time | Data in hold time | Data in hold time | 0 | - | - | - | 0.9 | 0.9 | 0.9 | 0.9 | 0.9 | 0.9 | μs |
| tSU.DAT | Data in setup time | Data in setup time | Data in setup time | Data in setup time | Data in setup time | Data in setup time | 50 | - | - | - | - | - | - | - | - | - | ns |
| tR | SCL/SDA rise time -- | SCL/SDA rise time -- | SCL/SDA rise time -- | SCL/SDA rise time -- | SCL/SDA rise time -- | SCL/SDA rise time -- | - | - | - | - | 120 | 120 | 120 | 120 | 120 | 120 | ns |
| tF | SCL/SDA fall time | SCL/SDA fall time | SCL/SDA fall time | SCL/SDA fall time | SCL/SDA fall time | SCL/SDA fall time | - | - | - | - | 120 | 120 | 120 | 120 | 120 | 120 | ns |
| tSU.STO | Stop set-up time | Stop set-up time | Stop set-up time | Stop set-up time | Stop set-up time | Stop set-up time | 0.26 | - | - | - | - | - | - | - | - | - | μs |
| Ci/o | Input/output capacitance (SDA) | Input/output capacitance (SDA) | Input/output capacitance (SDA) | Input/output capacitance (SDA) | Input/output capacitance (SDA) | Input/output capacitance (SDA) | - | - | - | - | 10 | 10 | 10 | 10 | 10 | 10 | pF |
| Cin | Input capacitance (SCL) | Input capacitance (SCL) | Input capacitance (SCL) | Input capacitance (SCL) | Input capacitance (SCL) | Input capacitance (SCL) | - | - | - | - | 4 | 4 | 4 | 4 | 4 | 4 | pF |
| CL | Load capacitance | Load capacitance | Load capacitance | Load capacitance | Load capacitance | Load capacitance | - | 140 | 140 | 140 | 550 | 550 | 550 | 550 | 550 | 550 | pF |
DS13805 - Rev 6 Symbol Parameter Minimum Typical Maximum Unit
F I2C Operating frequency 0 - 1000 kHz
t LOW Clock pulse width low 0.5 - -
t HIGH Clock pulse width high 0.26 - -
t SP Pulse width of spikes that are suppressed by the input filter - - 50
t BUF Bus free time between transmissions 0.5 - -
t HD.STA Start hold time 0.26 - -
t SU.STA Start setup time 0.26 - -
t HD.DAT Data in hold time 0 - 0.9
t SU.DAT Data in setup time 50 - -
t R SCL/SDA rise time - - - - 120
t F SCL/SDA fall time - - 120
t SU.STO Stop set-up time 0.26 - -
Ci/o Input/output capacitance (SDA) - - 10
Cin Input capacitance (SCL) - - 4
C L Load capacitance - 140 550 μs ns μs ns μs pF page 14/38
Control interface Table 6. I²C interface - timing characteristics for fast mode (400 kHz)
Symbol Parameter Minimum Typical Maximum Unit
F I2C Operating frequency 0 - 400 kHz
t LOW Clock pulse width low 1.3 - -
t HIGH Clock pulse width high 0.6 - -
t SP Pulse width of spikes that are suppressed by the input filter - - 50
t BUF Bus free time between transmissions 1.3 - -
t HD.STA Start hold time 0.26 - -
t SU.STA Start setup time 0.26 - -
t HD.DAT Data in hold time 0 - 0.9
t SU.DAT Data in setup time 50 - -
t R SCL/SDA rise time - - - - 300
t F SCL/SDA fall time - - 300
t SU.STO Stop set-up time 0.6 - -
Ci/o Input/output capacitance (SDA) - - 10
Cin Input capacitance (SCL) - - 4
C L Load capacitance - 125 400 μs ns μs ns μs pF Figure 15. I²C timing characteristics stop start start ... SDA t BUF SCL t LOW t R V IH V IL t HD.STA t F V IH stop
IL t HD.STA t HD.DAT t HIGH t SU.DAT t SU.STA t SU.STO
IL or V IH .
All timings are measured from either V IL or V IH .
DS13805 - Rev 6 page 15/38
Control interface
The registers shown in the table below can be used to validate the user I²C interface.
Table 7. Reference registers Note:
| Register name | Index | Value | |
|---|---|---|---|
| Model_ID | 0x010F | 0xEB | |
| Module_Type | 0x0110 | 0xAA | |
| The I²C read/writes can be 8, 16 or 32-bit. Multibyte reads/writes are always addressed in ascending order with MSB first as shown in the following table. The customer must use the VL53L4CX software driver for easy and efficient ranging operations to match performance and accuracy criteria. Hence, full register details are not exposed. The customer should refer to the VL53L4CX user manual. Table 8. 32-bit register example | |||
| Register address | Register address | Byte | Byte |
| Address | Address | MSB | MSB |
| Address + 1 | Address + 1 | - | - |
| Address + 2 | Address + 2 | - | - |
| Address + 3 | Address + 3 | LSB | LSB |
Address + 3 LSB page 16/38
Thermal characteristics
Warning: Stresses above those listed in the following table may cause permanent damage to the
device. These are stress ratings only. Functional operation of the device is not implied at these or any other conditions above those indicated in the operational sections of the specification. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
The storage temperature (T STG ) is the ambient temperature at which the device can be stored with no voltage applied.
Table 9. Absolute maximum rating conditions
Parameter Min. Max. Unit
Storage temperature (T STG ) -40 125 °C
| Parameter | Min. | Max. | Unit | |||
|---|---|---|---|---|---|---|
| Storage temperature (TSTG ) | -40 | -40 | 125 | 125 | °C | °C |
| Ambient operating temperature The ambient operating temperature is the temperature at which the device may be powered and can operate without any damage. Table 10. Recommended operating temperature | Ambient operating temperature The ambient operating temperature is the temperature at which the device may be powered and can operate without any damage. Table 10. Recommended operating temperature | Ambient operating temperature The ambient operating temperature is the temperature at which the device may be powered and can operate without any damage. Table 10. Recommended operating temperature | Ambient operating temperature The ambient operating temperature is the temperature at which the device may be powered and can operate without any damage. Table 10. Recommended operating temperature | Ambient operating temperature The ambient operating temperature is the temperature at which the device may be powered and can operate without any damage. Table 10. Recommended operating temperature | Ambient operating temperature The ambient operating temperature is the temperature at which the device may be powered and can operate without any damage. Table 10. Recommended operating temperature | Ambient operating temperature The ambient operating temperature is the temperature at which the device may be powered and can operate without any damage. Table 10. Recommended operating temperature |
| Parameter | Parameter | Min. | Min. | Max. | Max. | Unit |
| Ambient operating temperature | Ambient operating temperature | -30 | -30 | 85 | 85 | °C |
Ambient operating temperature -30 85 °C page 17/38
Electrical characteristics
Warning: Stresses above those listed in the following table may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 11. Absolute maximum ratings
| Parameter | Min. | Typ. | Max. | Unit | ||||
|---|---|---|---|---|---|---|---|---|
| AVDD | AVDD | -0.5 | -0.5 | - | - | 3.6 | 3.6 | V |
| SCL, SDA, XSHUT and GPIO1 | SCL, SDA, XSHUT and GPIO1 | -0.5 | -0.5 | - | - | 3.6 | 3.6 | V |
| Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. Table 12. Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. | Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. Table 12. Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. | Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. Table 12. Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. | Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. Table 12. Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. | Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. Table 12. Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. | Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. Table 12. Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. | Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. Table 12. Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. | Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. Table 12. Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. | Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. Table 12. Recommended operating conditions There are no power supply sequencing requirements. The I/Os may be high, low or floating when AVDD is applied. The I/Os are internally failsafe with no diode connecting them to AVDD. |
| Parameter | Min. | Min. | Typ. | Typ. | Max. | Max. | Unit | Unit |
| Voltage (AVDD) | 2.6 | 2.6 | 2.8 | 2.8 | 3.5 | 3.5 | V | V |
| IO (IOVDD)(1) | 1.6 | 1.6 | 1.8/2.8 | 1.8/2.8 | 3.5 | 3.5 | V | V |
| 1. XSHUT should be high level only when AVDD is on ESD The VL53L4CX is compliant with electrostatic discharge (ESD) values presented in the following table. Table 13. ESD performances | 1. XSHUT should be high level only when AVDD is on ESD The VL53L4CX is compliant with electrostatic discharge (ESD) values presented in the following table. Table 13. ESD performances | 1. XSHUT should be high level only when AVDD is on ESD The VL53L4CX is compliant with electrostatic discharge (ESD) values presented in the following table. Table 13. ESD performances | 1. XSHUT should be high level only when AVDD is on ESD The VL53L4CX is compliant with electrostatic discharge (ESD) values presented in the following table. Table 13. ESD performances | 1. XSHUT should be high level only when AVDD is on ESD The VL53L4CX is compliant with electrostatic discharge (ESD) values presented in the following table. Table 13. ESD performances | 1. XSHUT should be high level only when AVDD is on ESD The VL53L4CX is compliant with electrostatic discharge (ESD) values presented in the following table. Table 13. ESD performances | 1. XSHUT should be high level only when AVDD is on ESD The VL53L4CX is compliant with electrostatic discharge (ESD) values presented in the following table. Table 13. ESD performances | 1. XSHUT should be high level only when AVDD is on ESD The VL53L4CX is compliant with electrostatic discharge (ESD) values presented in the following table. Table 13. ESD performances | 1. XSHUT should be high level only when AVDD is on ESD The VL53L4CX is compliant with electrostatic discharge (ESD) values presented in the following table. Table 13. ESD performances |
| Parameter | Parameter | Specification | Specification | Specification | Specification | Conditions | Conditions | Conditions |
| Human body model | Human body model | JS-001-2012 | JS-001-2012 | JS-001-2012 | JS-001-2012 | ± 2 kV, 1500 ohms, 100 pF | ± 2 kV, 1500 ohms, 100 pF | ± 2 kV, 1500 ohms, 100 pF |
| Charged device model | Charged device model | JESD22-C101 | JESD22-C101 | JESD22-C101 | JESD22-C101 | ± 500 V | ± 500 V | ± 500 V |
Charged device model JESD22-C101 ± 500 V page 18/38
Electrical characteristics
Table 14. Power consumption at ambient temperature
All current consumption values include silicon process variations. Temperature and voltage are nominal conditions (23°C and 2v8). All values include AVDD and AVDDVCSEL.
| Parameter | Min. | Typ. | Max. | Unit | |||||
|---|---|---|---|---|---|---|---|---|---|
| HW STANDBY | HW STANDBY | 3 | 3 | 5 | 5 | 7 | 7 | μA | μA |
| SW STANDBY | SW STANDBY | 4 | 4 | 6 | 6 | 9 | 9 | μA | μA |
| Active ranging average consumption (including VCSEL)(1) (2) | Active ranging average consumption (including VCSEL)(1) (2) | 19 | 19 | 21 | 21 | mA | mA | ||
| 1. Active ranging is an average value, measured using default driver settings. 2. Peak current (including VCSEL) can reach 40 mA Digital input and output Table 15. Digital I/O electrical characteristics | 1. Active ranging is an average value, measured using default driver settings. 2. Peak current (including VCSEL) can reach 40 mA Digital input and output Table 15. Digital I/O electrical characteristics | 1. Active ranging is an average value, measured using default driver settings. 2. Peak current (including VCSEL) can reach 40 mA Digital input and output Table 15. Digital I/O electrical characteristics | 1. Active ranging is an average value, measured using default driver settings. 2. Peak current (including VCSEL) can reach 40 mA Digital input and output Table 15. Digital I/O electrical characteristics | 1. Active ranging is an average value, measured using default driver settings. 2. Peak current (including VCSEL) can reach 40 mA Digital input and output Table 15. Digital I/O electrical characteristics | 1. Active ranging is an average value, measured using default driver settings. 2. Peak current (including VCSEL) can reach 40 mA Digital input and output Table 15. Digital I/O electrical characteristics | 1. Active ranging is an average value, measured using default driver settings. 2. Peak current (including VCSEL) can reach 40 mA Digital input and output Table 15. Digital I/O electrical characteristics | 1. Active ranging is an average value, measured using default driver settings. 2. Peak current (including VCSEL) can reach 40 mA Digital input and output Table 15. Digital I/O electrical characteristics | 1. Active ranging is an average value, measured using default driver settings. 2. Peak current (including VCSEL) can reach 40 mA Digital input and output Table 15. Digital I/O electrical characteristics | 1. Active ranging is an average value, measured using default driver settings. 2. Peak current (including VCSEL) can reach 40 mA Digital input and output Table 15. Digital I/O electrical characteristics |
| Symbol | Parameter | Parameter | Min. | Min. | Typ. | Typ. | Max. | Max. | Unit |
| Interrupt pin (GPIO1) | Interrupt pin (GPIO1) | Interrupt pin (GPIO1) | Interrupt pin (GPIO1) | Interrupt pin (GPIO1) | Interrupt pin (GPIO1) | Interrupt pin (GPIO1) | Interrupt pin (GPIO1) | Interrupt pin (GPIO1) | Interrupt pin (GPIO1) |
| VIL | Low level input voltage | Low level input voltage | — | — | — | — | 0.3 IOVDD | 0.3 IOVDD | V |
| VIH | High level input voltage | High level input voltage | 0.7 IOVDD | 0.7 IOVDD | — | — | — | — | V |
| VOL | Low level output voltage (IOUT = 4 mA) | Low level output voltage (IOUT = 4 mA) | — | — | — | — | 0.4 | 0.4 | V |
| VOH | High level output voltage (IOUT = 4 mA) | High level output voltage (IOUT = 4 mA) | IOVDD-0.4 | IOVDD-0.4 | — | — | — | — | V |
| FGPIO | Operating frequency (CLOAD = 20 pF) | Operating frequency (CLOAD = 20 pF) | 0 | 0 | — | — | 108 | 108 | MHz |
| I2C interface (SDA/SCL) | I2C interface (SDA/SCL) | I2C interface (SDA/SCL) | I2C interface (SDA/SCL) | I2C interface (SDA/SCL) | I2C interface (SDA/SCL) | I2C interface (SDA/SCL) | I2C interface (SDA/SCL) | I2C interface (SDA/SCL) | I2C interface (SDA/SCL) |
| VIL | Low level input voltage | Low level input voltage | -0.5 | -0.5 | — | — | 0.6 | 0.6 | V |
| VIH | High level input voltage | High level input voltage | 1.12 | 1.12 | — | — | 3.5 | 3.5 | V |
| VOL | Low level output voltage (IOUT = 4 mA) | Low level output voltage (IOUT = 4 mA) | — | — | — | — | 0.4 | 0.4 | V |
| IIL/IH | Leakage current(1) | Leakage current(1) | — | — | — | — | 10 | 10 | V |
| IIL/IH | Leakage current(2) | Leakage current(2) | — | — | — | — | 0.15 | 0.15 | μA |
— — 0.4 Leakage current (1) — 10
Leakage current (2) — 0.15 V μA
DS13805 - Rev 6 page 19/38
Ranging performances
In all the measurement tables of this document, it is considered that: • • • • • • • • •
All ranging performances are measured with the target covering the full FoV. Charts used as targets are: gray (17% reflectance, N4.74 Munsell) and white (88% reflectance N9.5 Munsell). The nominal voltage is 2.8 V and the temperature is 23°C. The device is controlled through the driver using the default settings (refer to the user manual for driver settings description). Indoor (no IR) means that there is no contribution of light in the band 940 nm ± 30 nm Outdoor overcast corresponds to an ambient light level of 10 kcps/SPAD. For reference, this corresponds to a 1.2 W/m 2 at 940 nm following the AM1.5G spectrum and is equivalent to 5 klx daylight as reflected by a gray 17% chart at 40 cm. No cover glass is present. Typical samples are used. Offset correction is made at 100 mm from a sensor with gray 17% target.
The minimum detection distance is 0 mm. The minimum ranging distance with a linear response is 10 mm.
The following table shows the ranging specification for the VL53L4CX bare module, without cover glass, at room temperature (23°C), with nominal voltage (2.8 V) and full FoV covered.
Table 16. Max. ranging capabilities with 33 ms timing budget Target reflectance level, full FoV
(reflectance %)
White target (88%)
Light gray target (54%)
Gray target (17%)
Indoor Outdoor overcast (detection rate %) (detection rate %)
Typical: 5000 mm @ 90% min Typical: 1600 mm @ 90% min Typical: 6000 mm @ 50% min Typical: 1800 mm @ 50% min
Typical: 4200 mm @ 90% min Typical: 1400 mm @ 90% min Typical: 4600 mm @ 50% min Typical: 1600 mm @ 50% min
Typical: 2100 mm @ 90% min Typical: 1100 mm @ 90% min Typical: 2500 mm @ 50% min Typical: 1300 mm @ 50% min Detection rate is a statistical value indicating the worst case percentage of measurements that return a valid ranging. For example, taking 1000 measurements with 90% detection rate gives 900 valid distances. The 100 other distances may be outside of the specification and are flagged with an error status. Note:
DS13805 - Rev 6 The ranging distances reported in the table are the ones reported by the driver by the parameter called RangeMilliMeter.
page 20/38
Ranging performances
The figure below illustrates how range accuracy is defined over distance.
The ranging accuracy is a direct evaluation of the measurement error, including offset errors and output noise. At least 90% of the ranging values are within the declared ranges. This quality indicator includes measure-tomeasure and part-to-part dispersion.
Table 17. Typical ranging accuracy with 33 ms timing budget
| Target reflectance level, full FoV | Distance (mm) | Indoor (no infrared) | Outdoor overcast |
|---|---|---|---|
| White target (88%) | 10-110 | ± 8 mm | ± 9 mm |
| White target (88%) | >110 | ± 3% | ± 5% |
| Lite gray target (54%) | 10-110 | ± 8 mm | ± 9 mm |
| Lite gray target (54%) | >110 | ± 4% | ± 6% |
| Gray target (17%) | 10-110 | ± 7 mm | ± 8 mm |
| Gray target (17%) | >110 | ± 5% | ± 8% |
page 21/38
Ranging performances
When the temperature increases, the ranging value is affected by an offset of 1.3 mm per degree Celsius change. This value is an offset and not a gain, and it does not depend on the target distance. The device embeds a feature that allows compensation for the temperature variation effect. When the ranging is started, a self-calibration is performed once and this allows to remove the ranging drift. To get the most accurate performances, perform a self-calibration when temperature varies. To self-calibrate, call the functions “stop” and “start”, in sequence.
DS13805 - Rev 6 page 22/38
Outline drawings
STMicroelectronics delivers any of the two alternative dual source cap assemblies as detailed in the drawings below. Both versions are transparent for the customer, since the pad and substrate design are identical for both versions and have no impact on customer PCB design. Ranging performances, reflow, and technical parameters are identical for both module designs presented in the second figure below. Note: The module drawings below are based on DM00726192, rev 4.0.
DS13805 - Rev 6 page 23/38
Outline drawings
Note: For more information, refer to Table 2. VL53L4CX pin description.
DS13805 - Rev 6 page 24/38
Outline drawings
DS13805 - Rev 6 page 25/38
Field of view (FoV) and field of illumination (FoI)
The Rx (or collector) exclusion zone includes all module assembly tolerances and is used to define the cover window dimensions. The cover window opening must be equal to or wider than the exclusion zone. The detection volume represents the applicative or system FoV in which a target is detected, and a distance measured. It is determined by the Rx lens or the Rx aperture, and is narrower than the exclusion zone.
Table 18. FoV angles
| Setting | Target at 100 mm (white 88%) | Target at 1000 mm (white 88%) |
|---|---|---|
| Detection volume (°) | 22° | 18° |
| Collector exclusion cone (°) | 25° | |
Collector exclusion cone (°) 25° 25° Note: Detection volume depends on the environment and sensor configuration as well as target distance, reflectance,
ambient light level, sensor timing budget, distance mode, and tuning parameters. Note: The detection volume of Table 18. FoV angles has been measured with a white 88% reflectance perpendicular
target. Measurements are taken in full FoV, located at 100 mm and 1000 mm from the sensor, without ambient light (dark conditions), using the default driver configuration. The VCSEL FoI is shown in the figure below. The X-axis is 16° and the Y-axis is 16° (1/e²).
DS13805 - Rev 6 page 26/38
Laser safety
This product contains a laser emitter and corresponding drive circuitry. The laser output is designed to meet Class 1 laser safety limits under all reasonably foreseeable conditions including single faults in compliance with IEC 60825-1:2014. Do not increase the laser output power by any means. Do not use any optics to focus the laser beam. Caution: Use of controls or adjustments, or performance of procedures other than those specified herein may result in
hazardous radiation exposure.
This product complies with: • • • • DS13805 - Rev 6 IEC 60825-1:2014 21 CFR 1040.10 and 1040.11, except for conformance with IEC 60825-1:2014 as described in the laser notice number 56, dated May 8, 2019. EN 60825-1:2014 including EN 60825-1:2014/A11:2021 EN 50689:2021, however STMicroelectronics does not guarantee compliance with the requirement of clause 5 from EN50689 regarding child appealing products. If designing a child appealing product, contact STMicroelectronics' technical application support.
page 27/38
Packing and labeling
A two-line product marking is applied on the backside of the module (that is, on the substrate). The first line is the silicon product code, and the second line, the internal tracking code.
The labeling follows the ST standard packing acceptance specification. The following information will be on the inner box label: • • • • • •
Assembly site Sales type Quantity Trace code Marking Bulk ID number
At the customer level, it is recommended to mount the device in a clean environment to avoid foreign material deposition. To help avoid any foreign material contamination at the product assembly level, the module is shipped in a tape and reel format. The tape is described in Section 10.4: Tape outline drawing. The packing is vacuum sealed and includes a desiccant.
DS13805 - Rev 6 page 28/38
Packing and labeling
The pictures below show the tape outline drawings for modules without and with liner. The pin1 of the module is referenced by a red star in the figures.
Caution:
DS13805 - Rev 6 For sensors with the liner option, the liner must be removed during assembly of the customer device, just before mounting the cover glass. The liner is compliant with a reflow at 260°C (as per JEDEC-JSTD-020-C).
page 29/38
Handling, moisture, and reflow precautions
Sensor modules house numerous internal components that are susceptible to shock damage. If a unit is subject to excessive shock, is dropped on the floor, or a tray/reel of units is dropped on the floor, it must be rejected, even if no apparent damage is visible.
Handling must be done with non-marring ESD safe carbon, plastic, or teflon tweezers. Ranging modules are susceptible to damage or contamination. The customer is advised to use a clean assembly process after removing the tape from the parts, and until a protective cover glass is mounted.
A maximum compressive load of 25 N should be applied on the module.
Moisture sensitivity is level 3 (MSL) as described in JEDEC JSTD-020-C. For devices that are classified to the levels defined in JEDEC JSTD-020-C, JEDEC JSTD-033-C provides: • • DS13805 - Rev 6 Manufacturers and users with standardized methods for handling, packing, and shipping. Standardized methods for using moisture/reflow and process sensitive devices.
page 30/38
Handling, moisture, and reflow precautions
Table 19. Recommended solder profile and Figure 27. Solder profile show the recommended and maximum values for the solder profile. Customers have to tune the reflow profile depending on the PCB, solder paste and material used. We expect customers to follow the recommended reflow profile, which is specifically tuned for the VL53L4CX package. For any reason, if a customer must perform a reflow profile, which is different from the recommended one (especially peak >240°C), this new profile must be qualified by the customer at their own risk. In any case, the profile must be within the “maximum” profile limit described in JEDEC JSTD-020-C and the following table. Note: The temperature mentioned in the following table is measured at the top of the VL53L4CX package.
Table 19. Recommended solder profile
| Parameters | Recommended | Maximum | Unit |
|---|---|---|---|
| Minimum temperature (TS min) | 130 | 150 | °C |
| Maximum temperature (TS max) | 200 | 200 | °C |
| Time ts (TS min to TS max) | 90-110 | 60-120 | s |
| Temperature (TL) | 217 | 217 | °C |
| Time (tL) | 55-65 | 55-65 | s |
| Ramp up | 2 | 3 | °C/s |
| Temperature (Tp-10) | - | 250 | °C |
| Time (tp-10) | - | 10 | s |
| Ramp up | - | 3 | °C/s |
| Peak temperature (Tp) | 240 | 260 max | °C |
| Time to peak | 30 | 300 | s |
| Ramp down (peak to Tl) | -4 | -6 | °C/s |
Note: The component should be limited to a maximum of three passes through this solder profile. Note: As the VL53L4CX package is not sealed, only a dry reflow process should be used (such as convection reflow).
Vapor phase reflow is not suitable for this type of optical component. Note: The VL53L4CX is an optical component and as such, it should be treated carefully. This would typically include
using a ‘no wash’ assembly process.
DS13805 - Rev 6 page 31/38
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
DS13805 - Rev 6 page 32/38
Ordering information
The VL53L4CX is currently available in the formats below. More detailed information is available on request.
Table 20. Order codes DS13805 - Rev 6 Order codes Package Packing Minimum order quantity
| Order codes | Package | Packing | Minimum order quantity |
|---|---|---|---|
| VL53L4CXV0DH/1 | Optical LGA12 with liner | Tape and reel | 4500 pcs |
| VL53L4CXV9DH/1 | Optical LGA12 without liner | Tape and reel | 4500 pcs |
Acronyms and abbreviations
DS13805 - Rev 6
| Acronym/abbreviation | Definition |
|---|---|
| AF | autofocus |
| API | application programming interface |
| ESD | electrostatic discharge |
| FoV | field of view |
| I²C | inter-integrated circuit (serial bus) |
| MSB | most significant bit |
| PDAF | phase-detection autofocus |
| SCL | serial clock line |
| SDA | serial data line |
| SPAD | single photon avalanche diode |
| ToF | Time-of-Flight |
| VCSEL | vertical cavity surface emitting laser |
VCSEL vertical cavity surface emitting laser page 34/38
Acronyms and abbreviations
Table 21. Document revision history
| Date | Version | Changes |
|---|---|---|
| 05-Nov-2021 | 1 | Initial release |
| 21-Mar-2022 | 2 | Updated Tape outline drawing |
| 29-Jun-2022 | 3 | Updated Figure 13. Data format (sequential write) |
| 24-Nov-2022 | 4 | Added Figure 23: Class 1 laser product label 1 Updated Figure 24: Class 1 laser product label 2 Added laser compliancy references (IEC 60825:2014, EN 60825-1:2014, EN60825-1:2014/A11:2021, and EN 50689:2021). |
| 29-Apr-2024 | 5 | Section 3: Control interface: Replaced master/slave with controller/target. Table 15. Digital I/O electrical characteristics: Updated maximum VIH value of the I²C interface (SDA/SCL). Section 7: Outline drawings: Updated introductory text, added two notes, updated outline drawings 1-4, and added outline drawing 5. Updated Section 9: Laser safety. Section 10.1: Product marking: Removed Figure 25: Example of prototype marking. Section 10.3: Packing: Updated text and added a note. Replaced Section 10.4: Tape outline drawing. Section 13: Ordering information: Added introductory text and updated Table 20. Order codes for option without liner. |
| 12-Jul-2024 | 6 | Added Section 4: Thermal characteristics. Updated Section 10: Packing and labeling. Added Section 11: Handling, moisture, and reflow precautions. |
DS13805 - Rev 6 page 35/38
Contents
1 2 3 4 5 6 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 Technical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2 System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Device pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 System functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 State machine description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.3 Customer manufacturing calibration flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.4 Device programming and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.5 Ranging mode description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.6 Digital processing and reading the results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.7 Reading the results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.8 Power sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.9 Ranging sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.10 Handshake management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Control interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.1 I²C interface - timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 I²C interface - reference registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.1 Absolute maximum rating (TSTG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 Ambient operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 5.1 Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 ESD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.5 Digital input and output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Ranging performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6.1 Measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.2 Minimum ranging distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3 Maximum ranging distance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 Ranging accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.5 Ranging drift with temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DS13805 - Rev 6 page 36/38
Contents 7 Outline drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 8 Field of view (FoV) and field of illumination (FoI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 9 Laser safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 10 Packing and labeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
10.1 Product marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2 Inner box labeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.3 Packing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.4 Tape outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Handling, moisture, and reflow precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 11.1 Shock precaution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.2 Part handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.3 Compression force . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.4 Moisture sensitivity level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 11.5 Pb-free solder reflow process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 12 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 13 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 14 Acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 DS13805 - Rev 6 page 37/38
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